implantation, each with different energy and dose conditions, were carried out on different devices. (Halo1, Halo2, Halo3 and No Halo). These different splits are ...
Impact of Process Options on Low Frequency Noise in Germanium-onInsulator (GeOI) high-K & Metal Gate pMOSFETs J. Gyani1, F. Martinez1, S. Soliveres1, M. Valenza1, C. Le Royer2, E. Augendre2 and L. Clavelier2, 1
IES - UNIVERSITE MONTPELLIER II - UMR CNRS 5214 Place E. Bataillon, 34095 Montpellier Cedex 5, FRANCE 2 CEA-LETI Minatec, 17 rue des Martyrs, 38054 Grenoble cedex 9, FRANCE
ABSTRACT This paper presents an experimental investigation of Low Frequency Noise (LFN) measurements performed on Germanium-On-Insulator (GeOI) PMOS transistors with different process splits. The front gate is composed of a SiO2/HfO2 stack with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front and back gate interfaces are characterized and the slow oxide trap densities are extracted. The obtained values are comprised between 5 1017 and 8 1018 cm-3eV-1. No correlation between front interface trap density and front interface mobility is observed. We underline a strong correlation between rear interface trap density and rear interface mobility degradation. The impact of Ge film thickness is studied. For thin films, the measured drain-current noise spectral density shows that LFN can be described by the carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctuation model and in strong inversion the LFN is described by the carrier fluctuation model. The H parameter for these devices is 1.2 10-3. These results are of importance for the future development of GeOI technologies. 1.
INTRODUCTION
New materials and architectures are being taken advantage of in order to improve future MOSFET performance. Germanium (Ge) is a promising candidate to achieve sub-22nm node high performance pMOSFETs thanks to its higher hole mobility compared to Silicon (Si). Furthermore, thin film fully depleted SOI MOSFET devices attract great interest as they present many advantages over bulk transistor technology such as high transconductance, improved sub-threshold slope and short channel effect (SCE) control and suppression of the latch-up in CMOS technology [1]. Germanium-On-Insulator (GeOI)
technology is therefore considered a serious contender to bulk silicon devices [2,3]. Nevertheless, parameters such as the threshold voltage, the mobility and the subthreshold slope can be influenced by the back interface quality in ultra-thin film devices due the coupling between front and back depletion regions. It is therefore crucial to be able to determine the impact of GeOI fabrication processes on the quality of the interfaces. In this contribution, we present results showing the influence of As ion implantation on the trap density at the Ge/buried oxide (BOx) interface in state of the art GeOI devices using low frequency noise characterization. We also show the impact of halo implantations on the front and back gate trap density. Finally we show the impact of the Ge film thickness on noise characterization. 2. EXPERIMENTAL DETAILS Low-frequency drain current noise investigations are performed on TiN/HfO2/SiO2 GeOI pMOSFETs with low equivalent oxide thickness (EOT) value. The studied devices are elaborated on 200mm GeOI substrates with a 40-140 nm thick Ge active layer obtained using SmartCutTM technology. The devices were fabricated using GeOI transistor processes similar to those reported in [2,3], with thin Si capping passivation (~1nm) between Ge and HfO2. The front gate stack exhibits an EOT of 1.8 nm. The SiO2 buried oxide layer (Box) has a thickness varying between 200nm and 300nm, depending on the wafer.
PolySi 4nm HfO2 TiN 10nm
P+ P++
Ge
Top interface SiO /Si 2
Bottom interface Ge ~80nm
P+ P++
Ge ~80nm BOx 200nm
BOx 200nm Si
Figure 1: Schematics (left) and TEM image (right) of GeOI pMOSFETs [2].
Device
Substrate Doping
Halo Implantation
A1 B1 C1 C2 C3 C4 C5 D1 D2 D3 D4
None None Doping1 Doping 1 Doping 2 Doping 2 Doping 2 Doping 1 None Doping 1 Doping 1
None None Halo2 None Halo1 Halo2 halo3 None None None None
having not undergone As ion implantation. For these devices, the back interface transistor is switched off by applying a back gate voltage of +60V to the bottom of the wafer and the measured current is attributed solely to the front interface transistor. The threshold voltage of the front interface transistor is between 0.2V and 0.5 V and is a function of gate length. The extracted mobilities are reported in figure 2. Values vary between 120 cm²/V.s. and 360 cm²/V.s. Noise measurements for front interface characterization were performed on thin Ge film devices (>80nm) with VFG varying between 0.5 V and -1.2 V, with VDS=-50 mV and VBG at +60V for non doped devices and 0V for doped devices. The measured spectra show that 1/f noise is predominant. Figure 2 shows typical normalized draincurrent noise power spectral density SI / I2D at f=1Hz D as a function of the drain current Id from weak to strong inversion. The observed behavior indicates that the noise fluctuations follow the N carrier number fluctuation model. 10-5 10-6
SI /ID2@1Hz (A²/Hz) D
These devices have shown large ON state current densities with a perfect 1/LG behaviour down to 120nm. These performances are due to large hole low field mobility, which has been shown to be constant with gate length scaling. The measured subthreshold slope is between 100 and 140mV/dec, which is larger than the kT/q limit=60mV/dec at room temperature. This is attributed to the interface state density (Dit) located at the interface between the Ge film substrate and the gate stack. In order to study the effects of doping, 3 different As ion implantations, each with different energy and dose conditions, were carried out on different devices (Doping1, Doping2 and No Doping). Furthermore, some devices also underwent halo implantation to control short channel effects. In order to study the effects of halo implantation 4 types of halo implantation, each with different energy and dose conditions, were carried out on different devices (Halo1, Halo2, Halo3 and No Halo). These different splits are shown Table 1.
10-7 10-8 10-9 Experimental data N Model
10-10 10-11 10-9
10-8
Table 1: Technological characteristics of studied devices.
It should be noted that the dopant implantation is carried out after the substrate elaboration but prior to gate stack deposition. Halo implantation is carried out after gate stack deposition. The studied devices have a width W=1 µm and a length L between 0.12 and 5 µm. A complete current-voltage characterization using an Agilent 4156C semiconductor parameter analyzer was performed prior to noise measurements. Low-frequency noise measurements were performed using a HP89410A dynamic signal analyzer loaded by a high sensitivity current/voltage converter EG&G 5182. In order to measure the electrical characteristics at the Ge/buried oxide (BOx) interface, the back of the substrate is polarised (VBG) in order to modulate back interface current. Furthermore, a voltage is applied to the front gate (VFG) to suppress the front interface channel conduction. Noise measurements were carried out at VDS=-50mV, and from weak to strong inversion. The front and back interface mobilities were extracted using the Y function method [4]. 3. RESULTS AND DISCUSSION A. Front trap interface characterization Typical DC drain current evolutions versus front gate voltage VFG have shown a back conduction due to an apparent p type doping in the Ge film for devices
10-7
10-6 10-5 ID (A)
10-4
Figure 2: Typical variation of the normalized front drain current noise power spectral density at f=1Hz as a function of the drain current ID from weak to strong inversion, comparison with N model, at VDS=-50 mV
The N model assumes that the fluctuation of the number of insulator charges induces fluctuations in the flat-band voltage. The relative drain current noise power spectral density is expressed as [5]:
SI
D
f gm 2
ID
2
SV f ID
(1)
FB
The fluctuation of the oxide charge per unit area induces the fluctuation of the surface potential which is modelled by an equivalent flat band voltage fluctuation. In the case where the slow oxide trap distribution is uniform in energy and in space we have a pure 1/f noise and the flat band voltage fluctuation PSD is expressed as [5]:
SV
FB
f =
q kT N t EF 2
2
(2)
WLCox f
where is the tunnelling constant and Nt(EF) is the slow oxide trap density. The value of was calculated using the Wentzel-Kramers-Brillouin (WKB) approximation of Schrödinger’s equation to take into account the physical parameters of the high-K gate stack ( 1/= 4.2 109 m-1). Following this model, the slow oxide trap density NT(EF) of the front oxide can be extracted. The obtained values
implantation is clearly shown; devices having undergone substrate doping show a three-fold reduction in rear channel mobility and up to a ten-fold increase rear interface trap density. 10-5
10-6
D
SI /ID²@1 Hz (Hz-1)
are comprised between 7 1017 cm-3eV-1.and 2 1018 cm3 eV-1. Figure 3 shows the trap density at the Ge/front oxide interface as a function of carrier mobility for the different studied devices. It can be seen that there is no correlation between the trap density and the mobility; the trap density remains fairly constant across the different devices. Furthermore, it can be seen that devices without substrate doping exhibit the highest mobility values. It can also be seen that devices having received halo implantation tend to have lower mobilities although sample C2 with no halo implantation also shows low mobility.
10-7
10-8
Experimental data Model
10-9
1e+19
Trap Density (cm-3eV-1)
10-10 No counter-doping Counter doping 1 Counter doping 2
10-11 10-9
C3 B1
10-6
10-5
10-4
Figure 4: Typical variation of the normalized back drain current noise power spectral density at f=1Hz as a function of the drain current ID from weak to strong inversion, comparison with N model at VDS=-50 mV.
A1
D3
C1
10-7
ID (A)
C2 C5 1e+18
10-8
D4
D2
D1
1e+19 1e+17 100
150
200
250
300
350
D1 D4
400
2 -1 -1
B. Back trap interface characterization The front interface transistor is switched off at VFG=0.5V and the measured current is solely attributed to the back interface transistor. VDS=-50 mV. The back interface drain current and conductance (g m) evolutions versus back gate voltage VBG for a given front gate voltage VFG show normal transistor operation. Back gate threshold voltage and carrier mobilities are extracted. For devices without substrate doping the threshold voltages are about 10 V, whereas for devices with substrate doping the threshold voltage are between -20 V to -30 V. The extracted mobilities are between 80 and 300 cm²/V.s. (see figure 4). Noise measurements for back interface characterization were performed under the same polarisation conditions than for the static measurements. Typical normalised drain current spectral density carried out at 1 Hz is reported as a function of drain current in Figure 4. The 1/f noise Power Spectral Density (PSD) measured at the back interface follows McWorter’s number fluctuation (ΔN) model described by equations (1) and (2), and is therefore attributed to charge trapping by slow oxide traps in the BOx. Following this model, the slow oxide trap density NT(EF) of the BOx can be extracted. The obtained values are comprised between 5 1017 and 8 1018 cm-3eV-1. Figure 5 shows the variation of the trap density at the Ge/buried oxide (BOx) interface as a function of the carrier mobility for the different studied devices. It can be seen that there is a correlation between the trap density and the mobility. Furthermore, the impact of substrate dopant
Trap Density (cm-3eV-1)
Mobility (cm V s )
Figure 3: Evolution of extracted front interface trap densities as a function of carrier mobility.
C5 C2 C1
No counter-doping Counter doping 1 Counter doping 2
C4 C3
B1 1e+18 D3
D2 A1
1e+17 50
100
150
200
250 2
300
350
-1 -1
Mobility (cm V s )
Figure 5: Evolution of extracted back interface trap densities as a function of carrier mobility
By comparing the trap densities as a function of mobility for front and back interfaces of the different devices, it can be seen that substrate doping ion implantation affects trap density at the rear interface only, suggesting that the actual ion implantation process creates defects at the rear interface through direct collision. C. Effect of Ge film thickness In order to study the impact of film thickness we measured devices with various Ge film thicknesses between 40nm and 140 nm. Front drain current Noise measurements have been performed from weak to strong inversion. Measurements are undertaken as a function of the Ge film thickness. Figure 6 shows typical normalized drain-current noise power spectral density SID / I2D at f=1Hz as a function of the drain current ID from weak to strong inversion. We observe two different behaviors in weak inversion, whereas in strong inversion the same behaviors are
observed. For thin films, the measured drain-current noise PSD shows that LFN can be described by carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctuation model and in strong inversion the LFN is described by carrier fluctuation model. This behaviour can be explained by the fact that for thicker devices the noise attributed to volume conduction is predominant compared to noise attributed to surface conduction. 10-4
10-5
10-6
10-7
D
SI /ID2@1Hz (/Hz)
(-1) slope
10-8 Thick film experimental data Thin film N model Thin film experimental data
10-9
10-10 10-9
10-8
10-7
10-6
10-5
10-4
ID (A)
Figure 6: Typical variation of the normalized drain current at f=1Hz as a function of the drain current ID from weak to strong inversion for thick and fin Ge film, comparison with N model data.
The µ model is associated with mobility fluctuations and is described by the following empirical relation proposed by Hooge [6]: (4) SID (f ) H I2D fN where H is the Hooge parameter used as a characteristic parameter for a given technology and N the total number of carriers under the gate. In weak inversion Rhayem et al [7] have shown that equation (4) becomes : qVD 2kT H SID (f ) ' ID th (5) 2 f 2 'kT L ’ is the ideality factor related to drain biases. For low drain biases, equation (5) can be written as q H SI (f ) ID VD (6) D L2 f According to equations (5) and (6), the normalized drain-current noise PSD SID / I2D exhibits a (-1) slope in weak inversion. This last equation is used to extract the value of Hooge’s parameter, which is found to be H= 1.2 10-3. This value is slightly above the range reported for conventional bulk CMOS devices (SiO2/poly-Si gate stack) [8], but is of the same order as that originally found by Hooge in germanium bars [9]. To the author’s knowledge, there are no published values of H for advanced Ge/High-K devices.
4. CONCLUSION We have investigated front and rear interface 1/f noise in Ge pMOSFETs from weak to strong inversion for several devices with various Ge film thicknesses between 40nm and 140 nm and having undergone various technological processes, including substrate doping and Halo implantations. For thin Ge film devices, from weak to strong inversion, we have found that noise originates in the fluctuation of the number of carriers (N model) caused by trapping and de-trapping via defects in the dielectric oxides. Front and rear trap densities were extracted for all devices and correlated to the extracted low-field carrier mobilities. For the front interface, no correlation is observed between trap densities and carrier mobilities. For the rear interface, we have shown the impact of ion implantation doping of the substrate film on the trap density. Trap densities are 10 times higher in samples having undergone ion implantation compared to those having not received implantation. The study also suggests substrate doping by ion implantation creates defects at the rear interface. The effect of halo implantation is shown to be negligible in this particular study in comparison to the effects of substrate doping. For thick Ge fim devices, noise measurements suggest volume conduction in weak inversion, described by the mobility fluctuation model and indicate surface conduction in strong inversion. Hooge’s parameter, is found to be H= 1.2 10-3. This value is slightly above the range reported for conventional bulk CMOS devices (SiO2/poly-Si gate stack) [9], but is of the same order as that originally found by Hooge in germanium bars [10]. Acknowledgements The authors thank French OSEO organisation for financial support. REFERENCES [1] T. Skotnicki, Microelectronic Engineering 2007; 84: 1845-52 [2] C. Le Royer et al., Solid-State Electronics 52 (2008) 1285-1290.K [3] K. Romanjek et al, SOI conference 2008, p. 147148. [4] Ghibaudo, Haddara H., editor. Kluwer Academic Publishers; 1995 (chapter 1) [5] G. Ghibaudo, Solid-State Electron 1987, Volume 30, p. 1037 [6] F.N. Hooge, Phys. Lett. A., 1969, 29, p. 139. [7] J. Rhayem et al, J. Appl. Phys., Vol. 89, N0 7, pp 4192-4194, 2001. [8] M. V. Haartman and M. Hostling, Dordrecht, Netherlands: Springer, 2007. [9] F. N. Hooge et al, Rep. Prog. Phys., 1981, 44 (5), pp. 497-532.
