13.6 Physics-Based GaN HEMT Transport and Charge Model

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source charge and channel-injection-velocity that captures the essential FET ... VS – Transport and charge model for intrinsic transistor. The VS model is a ...

Physics-based GaN HEMT Transport and Charge Model: Experimental Verification and Performance Projection Ujwal Radhakrishna, Lan Wei, Dong-Seup Lee, Tomás Palacios, Dimitri Antoniadis Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA 02139, USA {ujwal, lanwei, dongseup, tpalacios, daa}@mit.edu Introduction GaN-based high electron mobility transistors (HEMTs) are rapidly emerging as front-runners in high-power mm-wave circuit applications. For circuit design with current devices and to allow sensible future performance projections from device engineering in such a rapidly evolving technology, physics-based compact device models are essential. This paper presents a new GaN HEMT model that accomplishes these goals. The model is based on the concept of the virtualsource charge and channel-injection-velocity that captures the essential FET device physics with a small number of device parameters that have straightforward physical meanings. The new model is calibrated and validated with experimental DC I-V and S-parameter measurements of fabricated devices. Using the model, a projection of cut-off frequency (fT) of GaN-based HEMTs with scaling is performed to highlight performance bottlenecks. VS – Transport and charge model for intrinsic transistor The VS model is a recently developed, simple but accurate semi-empirical short-channel FET, all-region of operation model [1, 2]. In the VS model concept, the current in any FET in saturation is calculated as the product of the charge areal density at the virtual source (Qixo) and the injected carrier velocity at the virtual source (vx) (Fig. 1c and Eqs. (14)). Transition from linear to saturation regime is governed by an empirical function (Fsat) as given in (5) [1]. The model has been validated with experimental bulk-Si MOSFETs and InGaAs HEMTs [3], and ETSOI MOSFETs [4]; it is adapted here to capture transport in short-channel GaN-based HEMTs. 1


ln 1



2 3 4





6 ,


U.S. Government work not protected by U.S. copyright


Figure 1. (a) Cross-sectional schematic of the fabricated InAlGaN/GaN HEMTs on SiC. (b) Equivalent circuit for the model and (c) Schematic of energy band diagram of the intrinsic region in saturation. The virtual source is at or near the maximum of the energy barrier for electrons in the channel. VY and VX are the intrinsic drain and source voltages, respectively, and vx is the carrier velocity and Qi,xo is the charge areal density at the virtual source point; the current density is the product of the two [1]. The potential profile determines the charge density along the channel (Qi’(x)) by enforcing current density continuity and energy conservation.

Effects such as non-linear access region behavior [5], device self-heating and GaN material-specific effects such as optical phonon scattering [6, 7] have been included. Mobility and velocity dependence on self-heating is given in (6)-(7). Velocity degradation due to strong electron-optical-phonon interaction and interface scattering in GaN HEMTs is modeled as Qixo-dependent vx. The full matrix of voltage-dependent capacitances is derived from intrinsic charges at each terminal by following [3]. By assuming linear or parabolic channel potential profile and enforcing energy conservation and current continuity along the channel, the voltage-dependent charges are selfconsistently solved with the transport model (8)-(9) [3]. QS and QD are channel charges associated with source and drain, with charge partitioning assuming linear longitudinal channel potential profile, respectively (10) [3]. Gate to source capacitance (Cgs) and gate to drain capacitance (Cgd) are derivatives of QS and QD respectively. Parasitic capacitances namely inner fringing (Cgs) and outer fringing (Cgd) capacitances are also included in the model.




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nted in Verilog-A and The HEMT model is implemen simulated in Virtuoso-Spectre. The model is calibrated to g length GaN on SiC experimental 105 nm and 42 nm gate devices; these devices are similar to those reported in [8]. nding output and transfer Figs. 3 and 4 show the correspon characteristics along with outtput conductance and transconductance characteristics. Key K model parameters are listed in Table 1. Notably, all fitting parameters are consistent for the two gate length devices.



Results and Discussion



Access region model In devices that are not self-aligned, access regions limit the saturation current at high bias (Figs. 3, 4). In order to study the behavior of access regions, experimenntal velocity vs. lateral field plots were obtained from I--Vs of un-gated transmission-line-model (TLM) structures.. Corrections to account for voltage drops in the contact resistances were accounted for in calculating the lateral fieldd. Fig. 2a shows velocity vs. lateral field plots for TLM structtures. The profile was obtained from I-Vs of TLMs with lenggths of 5, 10, 15, 20 and 25 µm. From the figure it is cleear that electron velocity quasi-saturation occurs at low eleectric field. This effect is taken into account by modeling aaccess regions as non-linear resistors with non-linearity causeed by both quasisaturation of velocity and device self-heeating (11)-(12). ,





, ,



11 12

is In (11), RS, D are non-linear access region resistances, is sheet resistance oof access regions contact resistance, and , are access region lengths. EC-S,D in ((12) is the critical electrical field for velocity quasi-saturationn including selfheating and is the self-heating temperaature coefficient. Modeled electron velocities fit the measureements very well (Fig. 2). The slight differentiation of the veelocity curves for different lengths at high E-field is due to selff-heating.

Figure 2. (a) Velocity vs. field plot of un-gated TLM M structures compared with model. Inset shows the schematic I-V of non-lineaar resistors as a result of saturated velocity vs. linear resistors wheree velocity increases proportionally with E-field. (b) Although high saturattion fields have been reported in the literature for velocity saturation, quasi--saturation of velocity shown in Fig. 2(a) happens at much lower fields. Thhis corresponds to the portion of Fig. 2(b) that is identified as ‘region of innterest’ in the Monte Carlo simulation results and measurements [5].


Figure 3. Output, transfer, output conductaance, and transfer conductance plots of Lg=105 nm device. Good agreementt has been achieved between the model (curves) and measurement (circles). As shown, non-linear access region resistance and contact resistance bou und the output curves. The steep reduction of gm after peak is due to Rs/Rd and high-field velocity degradation.

Figure 4. Similar to Fig. 4, for Lg=42 nm deevice, larger SCE causes further reduction in peak gm. The model matches weell with the measurement.


A slight reduction in peak gm in the 42 nm ggate length device when compared with the 105 nm gate lengthh device is due to increased short channel effects (SCE) such as DIBL, degraded SS, and modest punch-through. To improve the current-gain cut-off frequency (fT) withh scaling would therefore require suppression of SCE.

Figure 5. Effect of access region and contact resistancess on gm. Intrinsic, gm,int (black dot-dash line) has 66% higher peak value than exxtrinsic gm (blue solid line). Dip after the peak in gm is present even in intrrinsic gm due to Qixodependent velocity. Extrinsic peak gm is reduced from m peak intrinsic gm by both contact and access resistances. At high Vgs, resisttance non-linearity of access regions causes sharper gm reduction.

Figure 6. Gate capacitance (Cgg = Cgs + Cgd) vs. Vgs at Vds=0.1, 1 and 2 V for (a) Lg=105 nm device and (b) Lg=42 nm dev vice. (c) The small signal circuit model used to extract Cgg from S-parameteers. (d) Extraction procedure of fringing capacitances is shown. The capacitan nces calculated by the VS model with the fitted Cif and Cof (Table 1) match well w with the measured data for both devices.

Contact and access region resistances also have significant impact on peak transconductance (gm) as sshown in Fig. 5. The model shows 66% reduction in peak gm compared to peak intrinsic, gm,int. Thus without any other changes, reduction of contact resistance and gate self--alignment would be sufficient to significantly increase gm. However, sharp drop in gm above certain Vg is due to Qixo-deppendent vx, which could be due to interface scattering and optical phonon interaction [6, 7]. The latter is a GaN material-specific phenomenon and it might not be possible to eliminate this through device scaling [6].

Projection of fT

Fig. 6(a)-(b) shows the plot of gate capacitannce (Cgg) vs. Vg of 105 nm and 42 nm devices. Cgg was obbtained from Sparameters measured from 400 MHz to 40 G GHz with Agilent N5230A. The system was calibrated with aan off-wafer linereflect match (LRM) calibration standard, annd on-wafer open and short patterns were used to de-embed parasitic pad capacitances and inductances from thee measured Sparameters. Fringing capacitances (Cif, Cof) aare extracted from Cgg in strong and weak inversion regimes as shown in Fig. 6(d). Intrinsic channel charge density and hhence capacitance values depend inversely on carrier velocity aalong the channel. This is captured by (8)-(9) via the ““energy transfer parameter” ( ), (shown here for the linear channel potential assumption). = 0.19, with m*~0.2m0 ffor the electron effective mass in GaN, gives a good matcch with measured data which means that only roughly 20% of energy due to drain bias converts to kinetic energy; thiss may be due to scattering [6]. ).

fT is calculated from the model usin ng (13). Here gm,int and go are intrinsic transconductance an nd output conductance, respectively. , ,

13 ,

Fig. 7 shows comparison of fT’s caalculated from the model and those from S-parameter measurrement. Good agreement has been achieved for all devices fro om two separate lots with Lg from 28 nm to 105 nm. Devicees from lot 2 have lower fringing capacitances [8] than thosee in lot 1 due to improved line edge roughness. As shown in Fig. 8, scaling-down source access region (LS) and drain access region (LD) and suppressing SCE can both effectiveely improve fT. Scalingdown LS and LD reduces RS and d RD, which essentially decreases parasitic delay and thus t improves fT (13). Suppressing SCE, on the other hand, enhances fT by increasing gm,int while reducing go. With LS + Ld = 1 μm, and poor SCE (DIBL = 380 mV/V and SS=260 mV/dec) at gy (lot 2) provides fT of Lg=23 nm, the base-line technolog 290 GHz. Scaling-down LS and LD to 40 nm, which can be potentially achieved by adopting self-aligned s structure [9], would help in boosting fT to 340 GHz. Recent technology advancements such as use of back barriers have resulted in suppression of SCE [10]. Assuming improved dec, fT can be increased to DIBL=150 mV/V and SS=150 mV/d 380 GHz. Devices combining thee two improvements, are expected to show fT‘s above 400 GH Hz at Lg=23 nm.



The authors acknowledge Kopin Corporation C for supplying wafers, Triquint for helping with th he ohmic contact regrowth process and Omair Saadat for helping with the RF measurements. Table 1: Key parameters for transport an nd charge fitted to HEMTs Parameters

42 nm

105 nm


Lg (nm)



Channel length

Ls (um)



Source access region length

Ld (um)



Drain D access region length

Geometric param meters

Figure 7. (a) Current-gain dependence on frequency. D De-embedded fT from S-parameters is extracted for 42 nm and 105 nm devvices (lot 1). (b) Deembedded fT obtained from S-parameters is compared with fT estimated by model for 42 nm and 105 nm devices (lot 1). The moddel also fits well with another set of similar devices with somewhat lower frinnging capacitances (lot 2). Details of fringing capacitances can be found in [9]. (Passivation layer thickness is 10 nm)

Parameters extractable from measuremeents and device characteristics Cg (F/cm2)



Areal gate capacitance

Rsh (ohm/sq.)



Sheeet resistance of access region

RC (ohm-mm)



Contact resistance




Low-field mobility

Vt0 (V)



Th hreshold voltage for Vd~0V

Eco (V/cm)



Saturation electrical field

Cof [fF/mm]



Outer O fringing capacitance

Cif [fF/mm]



Inner I fringing capacitance

Fitting parameters (VS model m specific)

Figure 8. Projection of fT assuming suppressed SCE and/or scaled LS and LD with lot 2 devices as baseline devices. At Lg=23 nnm, fT of 340 GHz is achieved if LS and LD are scaled down to 40 nm (as in [9]) to reduce the source/drain resistance while maintaining the same SC CE as in the base line technology. On the other hand, if SCE could be improvved (DIBL=150 mV/V and SS=150 mV/dec) by possible technology innovvations such as back barrier [10] while LS and LD are kept identical as in the baseline devices, fT is boosted to 380 GHz. Assuming a scenario with both suppressed SCE and scaled LS and LD, fT at Lg=23 nm can be further inncreased to 400 GHz, according to the model.



Sub-tthreshold transition parameter








DIBL L saturation parameter with Vd

SS [V/Dec]



Sub-threshold swing




Punch through factor

Fitting parameters (Ga aN specific) xVxo (cm/s)

Conclusions A physics-based compact transport and ccharge model for GaN HEMTs has been developed. The modeel includes effects such as self-heating, non-linear access rregion behavior, electron-phonon interaction etc. The moodel is validated against fabricated devices and is used to evaluate fT improvements in short channel devices. Thee model is also a suitable base for GaN FET circuit sim mulation compact models. Acknowledgement T SMART-LEES This work was supported by the MIT program, the FCRP MSD-Center program m, the MIT GaN Energy Initiative and the DARPA NEXT proogram.




Velocity at VS point



Lateeral-field saturation parameter



Velocity y degradation parameter with Vgs



Energy E transfer parameter



Self-heating parameter



Mo obility self-heating parameter

VS model specific fitting parameter naames are consistent with [1]. GaN-specific fitting parameters for diffferent Lg devices are nearly identical.

References [1] A. Khakifirooz, O.M. Nayfeh, and D.A. Antoniaadis, TED (2009), pp.1674-1680. [2] C-.W. Jeong, D. A. Antoniadis, and M. S. Lundttrom, TED (2009), pp. 2762-2769. [3] L. Wei, O. Mysore and D.A. Antoniadis,TED (2012), ( 59(5), pp.1263-1271. [4]Y. Liu et al. IEEE TED(2012), pp 994-1001. [5] T. Palacios et al., IEEE Elec. Dev. Lett., 52(10),, 2117 (2007). [6] D. Jena and S. Rajan, IEEE Elec. Dev. Lett., 33((5), pp.709-711, (2012). [7] A. Matulionis et al., Proceedings of the IEEE, 98 8(7), pp.1118-1126,(2010). [8] D. S. Lee et al., IEEE EDL, PP(99), pp.1-3 (2012) (Early access). [9] K. Shinohara et al., IEDM Tech. Dig., pp.453-45 56 (2011). [10] D. S. Lee et al., IEEE EDL, 32, pp. 617-619 (2011).