fungsi suhu dikaji untuk mengetahui kebolehpercayaan peranti semasa operasi dalam masa yang panjang. Kata kunci: Transistor filem nipis organik; OTFT; ...
Sains Malaysiana 37(3)(2008): 295-298
Reliability Issues of Bottom-Contact Pentacene Thin-Film Transistors (Isu-isu Kebolehpercayaan Transistor Filem Nipis Pentasen dengan Sentuhan Bawah) JONG DUK LEE, BYUNG-GOOK PARK & KEUM-DONG JUNG
ABSTRACT
Bottom-contact pentacene OTFTs are fabricated using cross-linked poly(vinyl alcohol) (PVA) insulator and its reliability characteristics are analyzed. The hysteresis of the OTFTs is mainly caused by the electrons that are injected from the gate electrode to the cross-linked PVA insulator. To block the injection of electrons, plasma-enhanced chemical vapor deposition (PECVD) SiO2 layer is inserted between the gate electrode and the cross-linked PVA layer, so that the minimum hysteresis can be obtained. In addition, the effects of the gate bias stress as a function of time is investigated to examine the longterm reliability of the device during the operation. Keywords: Organic thin-film transistors; OTFT; bottom-contact; reliability; hysteresis ABSTRAK
Pentasen dengan sentuhan bawah OTFT telah difabrikasi dengan menggunakan penebat poli(vinil alkohol) (PVA) rangkaian silang. Ciri-ciri kebolehpercayaannya telah dianalisis. Histeresis dalam OTFT sebahagian besarnya disebabkan oleh elektron yang disuntik daripada elektrod get ke penebat rangkaian silang PVA. Untuk menghalang suntikan elektron, lapisan SiO2 yang didepositkan melalui kaedah wap kimia terbantu plasma (PECVD) diselitkan antara elektrod get dengan lapisan rangkaian silang PVA supaya histeresis adalah minimum. Disamping itu kesan tegasan dari pincangan get sebagai fungsi suhu dikaji untuk mengetahui kebolehpercayaan peranti semasa operasi dalam masa yang panjang. Kata kunci: Transistor filem nipis organik; OTFT; sentuhan bawah; kebolehpercayaan; histeresis INTRODUCTION
EXPERIMENTS
As a novel device, organic thin film transistors (OTFTs) have been researched widely because of their potential to be used in flexible displays (Mizukami et al. 2006), low-cost RF ID tag (Baude et al. 2003), or large-area sensors (Someya et al. 2005). Many previous studies have proved that the performance of OTFTs is equal or better than hydrogenated amorphous silicon TFTs(a-Si:H TFTs) which have driven the success of liquid crystal display (Dimitrakopoulos 2002). The low fabrication cost due to low processing temperature is another advantage of OTFTs and it can be even lowered when using advanced fabricating methods such as inkjet printing or roll-to-roll processing (Song et al. 2007). However, researches on the reliability of OTFTs are still demanded for the manufacturing of OTFTs. Among many reliability issues, hysteresis and bias-stress effects of OTFTs have been one of main problems (Sekitani et al. 2005) because not only they introduce significant errors when evaluating the electrical characteristics of the device, but also they can cause instable and abnormal operation of the devices. In this paper, the hysteresis and bias-stress effects of bottom-contact OTFTs are reported. In addition, the origin and the method to reduce the hysteresis are discussed.
To evaluate the reliability of bottom-contact OTFTs, two kinds of devices are fabricated as shown in Figure 1. On the oxidized silicon substrate, 30 nm-thick titanium gate electrodes are defined with photolithography and wet etching. For the single layer insulator, poly(vinyl alcohol) (PVA) are chosen among various organic insulators because of its easy process and high-k properties. After spin coating of an aqueous PVA solution mixed with ammonium dichromate photo-sensitizer, the PVA is cross-linked by ultraviolet exposure. For the double layer insulator, a plasma-enhanced chemical vapor deposition (PECVD) SiO2 layer of 35 nm is deposited before the spin-coating of PVA. The insulator of each device is patterned by photolithography and dry etching. Gold source/drain electrodes are patterned by photolithography and lift-off process. Finally, pentacene, the organic semiconductor is thermally evaporated at a high vacuum and substrate temperature of 80°C through a shadow mask. To evaluate the circuit operation, an inverter consisting of an enhancement-mode driver and an enhancement-mode load is also fabricated.
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FIGURE 1.
Structures of bottom-contact OTFTs. Two kinds of gate insulator are fabricated: (a) cross-linked PVA single layer insulator, (b) PECVD SiO2/cross-linked PVA double layer insulator
I-V characteristics of the devices are measured using Agilent 4156C parameter analyzer in a light-shielded probe station in air ambient. To measure the hysteresis characteristics, the gate voltage is swept bidirectional starting from a positive voltage. To investigate the bias stress effect, negative gate bias of -10 V is applied for some time, I-V characteristic is quickly measured, then the bias stress is applied again. Drain voltage is fixed at -0.1 V to minimize the effect of drain bias during the I-V measurement. For the evaluation of circuit operation, voltage transfer curves(VTC) of the inverter are measured with bidirectional input voltage. RESULTS AND DISCUSSION In Figure 2(a), the hysteresis characteristics of an OTFT with a cross-linked PVA single layer insulator are shown. Considerable threshold voltage (VTH) shift is observed from -1.9 V for the forward sweep to -0.2 V in backward. The field-effect mobility which is measured from the linear fit of I-V curve also shows a significant difference more than 70 %. Moreover, the hysteresis characteristics becomes more severe when the gate bias range increases or the sweep step is small (Lee et al. 2006). Therefore, reliable evaluation of the device cannot be done using a device which shows hysteresis characteristics. Figure 2(b) illustrates the bias stress effects of the device. The main effects of the negative gate bias stress are positive threshold voltage shift and the degradation of subthreshold slope. The threshold voltage changed more than 15 V with bias stress of 2000 seconds, resulting about four times oncurrent change. After relaxation of 1 day, the threshold voltage recovers to the initial value, which shows reversible characteristics of the bias stress effects. Figure 2(c) shows the voltage transfer curves of the inverters for various load transistor widths. The inverters also show considerable hysteresis regardless of the load width. In conclusion, the devices with the cross-linked PVA single layer insulator can not be used practically due to large hysteresis and bias stress effects not only for a single device, but also for an integrated circuit. Three possible mechanisms responsible for the positive threshold voltage shift are electron injection from
the gate electrode into the gate insulator, polarization effect of the insulator, and migration of mobile ion such as chromium ions in the insulator. The hysteresis direction in Figure 2 can be explained with any of these mechanisms. However, it is uncertain whether the mobile ions, especially heavy ions such as chromium ions, can move in the crosslinked PVA bulk in such a short sweep time at room temperature. Also, the polarization effect may not be a major reason because the hysteresis does not saturate although the gate voltage sweep range is increased. From the considerations above, it can be assumed that the charge injection and trapping may be the main origin of the hysteresis whereas the other two factors still have possibility. If the polarization and ion migration is the origin of the hysteresis, the cross-linked PVA itself should be improved because the two mechanisms originate from the internal properties of the insulator. However, if the charge injection and trapping mechanism is responsible for the hysteresis, another insulator layer between the gate electrode and insulator can effectively block the injected charge as shown in Figure 3. The hysteresis characteristics of a cross-linked PVA and PECVD SiO2 double layer insulator OTFT are shown in Figure 4(a). In contrast to the results in Figure 2(a), the hysteresis characteristics are reduced considerably. This result shows that the main origin of the hysteresis is electron injection from the gate electrode and the PECVD SiO2 layer effectively blocks the charge injection. The effects of other factors may still exist, but those are negligible in this case. The thickness of the blocking layer also affects the hysteresis because blocking efficiency changes with the oxide thickness. The lowest hysteresis is obtained at 35 nm among the oxide thickness of 10, 35, 70 and 100 nm (Park et al. 2006). The extracted electrical parameters such as threshold voltage and mobility are more reliable in this case. Figure 4(b) shows the reduced bias stress effect of the double layer insulator OTFT . Considerably reduced positive VTH shift and no degradation of subthreshold slope is observed compared to the results in Figure 2(b). However, a negative VTH shift is observed after bias stress of 200 seconds. This may due to the holes injected from the pentacene and trapped in the defect states of cross-linked PVA/pentacene interface. After relaxation
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2. (a) Hysteresis characteristics of OTFT with cross-linked PVA single layer insulator. (b) Transfer characteristics during the negative gate bias stress and after relaxation. (c) Voltage transfer curves of single layer insulator inverter
FIGURE
FIGURE
3. PECVD SiO2 layer can block the electrons injected from the gate electrode into the cross-linked PVA
of 1 day, the I-V characteristics almost recover to the initial value. In Figure 4(c), voltage transfer curves of the inverters with double layer insulator show considerably reduced hysteresis compared with that with single layer insulator. The reduced hysteresis in the inverter is attributed to the negligible hysteresis of the OTFTs.
CONCLUSION Reliable pentacene OTFTs are fabricated using a PECVD SiO2/ cross-linked PVA double layer insulator. A considerable reduction in hysteresis and bias stress effects is achieved by the insertion of charge blocking layer between the gate electrode and the insulator. On the basis of electrically stable OTFTs, more reliable organic inverters are fabricated.
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FIGURE
4. (a) Hysteresis characteristics of OTFT with PECVD SiO2 and cross-linked PVA double layer insulator. (b) Transfer characteristics during the negative gate bias stress and after relaxation. (c) Voltage transfer curves of double layer insulator inverter
REFERENCES Baude, P.F., Ender, D.A., Haase, M. A., Kelley, T.W., Muyres, D. V. & Theiss, S. D. 2003. Pentacene-based radio-frequency identification circuitry. Appl. Phys. Lett. 82: 3964-3966. Dimitrakopoulos, C.D. & Malenfant, P. R. L. 2002. Organic thin film transistors for large area. Electronics. Adv. Mat. 14: 99117. Lee, C.A, Park, D.W., Jin, S.H., Park, I.H., Lee, J.D. & Park, B.G.2006. Hysteresis mechanism and reduction method in the bottom-contact pentacene thin-film transistors with crosslinked poly(vinyl alcohol) gate insulator. Appl. Phys. Lett. 88: art. no. 252102. Mizukami, M., Hirohata, N., Iseki, T., Ohtawara, K., Tada, T., Yagyu, S., Abe, T., Suzuki, T., Fujisaki, Y. Inoue, Y. Tokito, S. & Kurita, T. 2006. Flexible AM OLED Panel Driven by Bottom-Contact OTFTs. IEEE Electron Device Lett. 27: 249251. Park, D.-W., Lee, C. A., Jung, K.-D., Park, B.-G., Shin, H. & Lee, J. D. 2006. Low hysteresis pentacene thin-film transistors using SiO2/cross-linked poly(vinyl alcohol) gate dielectric. Appl. Phys. Lett. 89: art. no. 263507. Sekitani, T., Iba, S., Kato, Y., Noguchi, Y., Someya, T. & Sakurai, T. 2005. Suppression of DC bias stress-induced degradation
of organic field-effect transistors using postannealing effects. Appl. Phys. Lett. 87: art no. 073505. Someya, T., Sakurai, T., & Sekitani, T. 2005. Flexible, large-area sensors and actuators with organic transistor integrated circuits. IEEE International Electron Device Meeting Technical Digest 4-7. Song, D.H., Choi, M.H., Kim, J.Y., Jang, J. & Kirchmeyer, S. 2007. Process optimization of organic thin-film transistor by ink-jet printing of DH4T on plastic. Appl. Phys. Lett. 90: art. no. 053504.
Jong Duk Lee Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering Seoul National University, Republic of Korea Byung-Gook Park and Keum-Dong Jung San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742 Republic of Korea Received : 12 June 2007 Accepted : 27 December 2007
