2.6 GHz GaN-HEMT Doherty Power Ampliﬁer Integrated Circuit with 55.5% Efﬁciency Based on a Compact Load Network Hwiseob Lee, Wonseob Lim, Jongseok Bae, Wooseok Lee, Hyunuk Kang, and Youngoo Yang School of Electronic and Electrical Engineering, Sungkyunkwan University, Suwon, 16419, Korea, Email: [email protected]
, [email protected]
Abstract—This paper presents a GaN-HEMT DPA IC based on a compact load network for LTE small cells. The gate widths of the transistors for the carrier and peaking ampliﬁers are optimized to have the same load impedance of 100 Ω. A shunt inductor is added to compensate for the output capacitor of each transistor with parallel resonance. A π-type high-pass impedance transformer based on lumped components is used to modulate the load impedance. Parallel inductors from the resonant circuit and the impedance transformer are merged for further simpliﬁcation. As a result, only two inductors remain in the load network. For veriﬁcation, a 2.6 GHz DPA IC with an on-chip load network and input matching networks was designed and fabricated using a 0.4 μm GaN-HEMT process. The DPA IC exhibited a peak output power of 43.9 dBm. For an LTE signal with a signal bandwidth of 10 MHz and a PAPR of 6.5 dB, a high drain efﬁciency of 55.5% with an ACLR of –30 dBc was obtained at an average output power of 37.4 dBm. Index Terms—Doherty power ampliﬁer integrated circuit, GaN-HEMT, compact load network, small cell base stations.
I. I NTRODUCTION In wireless communication systems, demand for small cell base stations such as those made of pico- or femto cells is increasing as small cells allow for broadening of communication coverage. Power ampliﬁers (PAs) for small cell base stations must have good RF performances and small sizes. Therefore, many PA integrated circuits (ICs) that use a gallium nitride high-electron-mobility transistor (GaN-HEMT) process for high power density and efﬁciency relative to other processes have been designed –. Doherty power ampliﬁers (DPAs) are widely used for base transceiver systems owing to their simple structures and the high-efﬁciency characteristics of modulated signals with a high peak-to-average power ratio (PAPR) ,. For proper load impedance modulation of a DPA, quarter-wave transmission lines for impedance transformation and offset lines are necessary parts of the load network. Lumped networks, equivalent to those in transmission lines, can be employed for their smaller form factors –. In , an off-chip load network, which has a size disadvantage, was adopted for the PA IC. In –, integrated load networks were proposed that use multiple on-chip inductors and capacitors. Since on-chip inductors have relatively low quality factors, their performance in terms of efﬁciency and output power can be degraded. To reduce loss and size, a compact load network with a reduced number of inductors is required. In this paper, we propose a high-efﬁciency GaN-HEMT DPA IC that includes an integrated compact load network.
A shunt inductor is employed at the drain of each transistor that has parallel resonance with the output capacitor and a pure real load impedance after it. Thus, real-to-real load impedance modulation can be achieved using a π-type highpass impedance transformer. After simpliﬁcation by merging the parallel inductors, the load network has just two shunt inductors and two series capacitors including one for DC blocking. The two shunt inductors are implemented using short lines and bond-wires to produce a high quality factor. For veriﬁcation, a GaN-HEMT DPA IC was designed and implemented for the 2.6 GHz band. The IC includes on-chip input matching networks and a load network. The design and measured performance are presented below. II. C IRCUIT D ESIGN A. Gate width optimization Selection of the gate width of the transistor used in the DPA IC is ﬂexible, while there are limited choices for hybrid circuits where commercial discrete components must be used. To obtain high output power and efﬁciency, the optimum gate width with an appropriate load resistance must be determined using load-pull simulation. From Cree’s 0.4 μm GaN-HEMT process, gate widths were optimized via simulations to have high efﬁciency and output power according to various load resistances. Optimum combinations of a gate width, a load resistance, and a consequent output power are presented in Table I. To have a load resistance of 100 Ω, a total gate width of 2,160 μm must be selected for an output power of about 41.5 dBm. TABLE I O PTIMUM G ATE W IDTHS WITH R ESPECTIVE O PTIMUM L OAD R ESISTANCES AND C ONSEQUENT O UTPUT P OWER Gate width 1,080 1,440 1,800 2,160 2,520 2,880 3,240 (μm) Output power 38.5 39.8 40.7 41.5 42.3 42.8 43.3 (dBm) Optimum load resistance 188 142 115 100 82 70 61 (Ω)
B. Design of the compact load network Fig. 1 shows schematic diagrams of the original (in (a)) and simpliﬁed (in (b)) conﬁgurations of the proposed load network. The output capacitance, COU T , of the transistor is compensated for by parallel resonance with a shunt inductor,
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9'' (b) Fig. 1. Proposed load network of the DPA: (a) original, (b) after simpliﬁcation. (PPL: peak-power level, LPL: low-power level)
LP , which has a value of 1/ ω 2 COU T . The load impedance becomes a pure real value after the resonance circuit. The optimum load resistances shown in Table I were determined after the parallel resonance circuit. Since the output impedance goes close to inﬁnity after the resonance, the peaking ampliﬁer does not need an extra offset line for sufﬁcient load impedance modulation of the carrier ampliﬁer in the low-power level. For load impedance modulation of the carrier ampliﬁer, a π-type high-pass network based on lumped components is employed to function as a quarter-wave transformer with a characteristic impedance of RT and an electrical length of −90◦ . The load network has no series inductor which could result in large size and insertion loss. The values of the series capacitor and the two shunt inductors for the high-pass impedance transformer are given as follows: 1 + cos θ 1 CT = , (1) ωRT 1 − cos θ −RT , (2) LT = ω sin θ where θ and RT are an electrical length of the network and the characteristic impedance of the line, respectively. For the
high-pass network, θ must be a negative value in degrees . By substituting RT with 100 Ω and θ with −90◦ , a CT of 0.61 pF and an LT of 6.12 nH are obtained. Since there are two pairs of shunt inductors, LP and LT , in parallel at the carrier and peaking ampliﬁer sides, each pair can be merged to a single shunt inductor, LP , as shown in Fig. 1(b). Since the value of LP should be smaller than that of either LP or LT , the circuit becomes more compact and loss can be reduced by implementing inductors with higher quality factors. In addition, a drain bias can be supplied through LP for both the carrier and peaking ampliﬁers. III. I MPLEMENTATION AND M EASUREMENT R ESULTS Fig. 2 shows the schematic diagram of the DPA IC with its evaluation circuits. Because of the proposed compact load network, no on-chip series inductor is used. The input matching networks are fabricated on-chip as well. The gate bias circuits adopt a series L-C resonance for the second harmonic such that it has a short circuit and a parallel L-C resonance for the fundamental to produce an open circuit. An off-chip input splitter is used. A delay line is added to the input of the carrier ampliﬁer to compensate for the phase shift of −90◦ from the high-pass impedance transformer at the load network. Fig. 3 shows the photograph of the fabricated GaN-HEMT DPA IC including the proposed load network and input matching networks. 3-D electromagnetic (EM) simulation was conducted to design the load network and matching networks. The effect of bond-wires was determined using the 3-D EM simulation and applied to the circuit design. The DPA IC was fabricated using Cree’s 0.4 μm GaN-HEMT process and has a chip size of 1.9×1.8 mm2 including bond pads. The DPA IC was mounted on a printed circuit board (PCB) based on RO4350B with a thickness of 0.5 mm.
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Fig. 3. Chip photograph of the fabricated GaN-HEMT DPA IC.
TABLE II P ERFORMANCE C OMPARISON WITH G A N-HEMT DPA IC S FROM P REVIOUS P UBLICATIONS
power ratio (ACLR) of −30 dBc were obtained at an average output power of 37.4 dBm. The experimental performances are summarized in Table II and compared to previously published results. This work used the fewest on-chip inductors at the load network, which resulted in a small chip size and an excellent DE.
Fig. 5. Measured power gain and DE for the LTE signal.
Reference     This work Frequency (GHz) 2.14 2.60 2.14 2.65 2.60 Load network Off-chip On-chip On-chip On-chip On-chip implementation # of inductors N/A 5 5 4 2 at the load network POUT (dBm) 36.5 33.4 33.2 33.1 37.4 DE (%) 39.7 41.9 51.8 49.0 55.5 ACLR* (dBc) –25.3 N/A –34.7 –27.1 –30.0 Size (mm2 ) 2.5×2.7 3.5×1.9 3.3×2.6 2.65×1.7 1.9×1.8 Modulated signal WCDMA LTE LTE LTE LTE *w/o linearization
2XWSXWSRZHUG%P Fig. 4. Simulated and measured power gains and DEs for the 2.6 GHz CW signal.
The carrier ampliﬁer is biased to have a quiescent current of 40 mA for Class-AB operation, while the peaking ampliﬁer displays Class-C operation. Both ampliﬁers have the same drain bias of 48 V. Fig. 4 shows the simulated and measured performances for the 2.6 GHz continuous wave (CW) signal. A peak output power of 43.9 dBm and a high drain efﬁciency (DE) of 57.4% at the 6 dB output power back-off level were obtained. The simulated and measured performances match well; there are only very small differences, which may be caused by inaccuracies in the transistor model. Fig. 5 shows the measured power gain and DE of the implemented DPA IC for the 2.6 GHz downlink long-term evolution (LTE) signal that has a channel bandwidth of 10 MHz and a PAPR of 6.5 dB. A power gain of 14.0 dB, an outstanding DE of 55.5%, and an adjacent channel leakage
IV. C ONCLUSIONS In this paper, a compact load network for GaN-HEMT DPA IC was proposed. Through use of an optimized gate width and a shunt inductor at the drain of the transistor, the carrier and peaking ampliﬁers can operate with a load resistance of 100 Ω. A π-type high-pass network based on lumped components was employed to perform real-to-real impedance transformation. Due to the high-pass impedance transformer, the load network has no series inductor. Since the parallel shunt inductors are merged for further simpliﬁcation, the load network becomes more compact and has low loss with only two on-chip inductors, which is the fewest relative to those described in previous publications.
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For veriﬁcation, a 2.6 GHz GaN-HEMT DPA IC was designed and implemented for LTE small cell application. The proposed DPA IC was fabricated using a 0.4 μm GaN-HEMT process and has a small size of 1.9×1.8 mm2 . The DPA IC was evaluated using a 2.6 GHz downlink LTE signal with a channel bandwidth of 10 MHz and a PAPR of 6.5 dB. A very high DE of 55.5% with an ACLR of −30 dBc was achieved at an average output power level of 37.4 dBm. ACKNOWLEDGMENT This work was supported by the National Research Foundation of Korea (NRF) funded by the Korean Government (MSIP) under Grant 2014R1A5A1011478. R EFERENCES  J. Komiak, “GaN HEMT: Dominant Force in High-Frequency Solid-State Power Ampliﬁers,” IEEE Microw. Mag., vol. 16, no. 3, pp. 97–105, Apr. 2015.  J. Lee, D. Lee, and S. Hong, “A Doherty Power Ampliﬁer With a GaN MMIC for Femtocell Base Stations,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 3, pp. 194–196, Mar. 2014.  S. Jee, J. Lee, B. Park, C. Kim, and B. Kim, “GaN MMIC Broadband Doherty Power Ampliﬁer,” in Asia-Paciﬁc Microw. Conf. Dig., Nov. 2013, pp. 603–605.  C. Kim, S. Jee, G. Jo, K. Lee, and B. Kim, “A 2.14-GHz GaN MMIC Doherty Power Ampliﬁer for Small-Cell Base Stations,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 4, pp. 263–265, Apr. 2014.  S. Jee, J. Lee, J. Son, S. Kim, C. Kim, J. Moon, and B. Kim, “Asymmetric Broadband Doherty Power Ampliﬁer Using GaN MMIC for Femto-Cell Base-Station,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 9, pp. 2802–2810, Sep. 2015.  Y. Yang, J. Cha, B. Shin, and B. Kim, “A Fully Matched N –Way Doherty Ampliﬁer With Optimized Linearity,” IEEE Trans. Microw. Theory Techn., vol. 51, no. 3, pp. 986–993, Mar. 2003.  V. Camarchia, M. Pirola, R. Quaglia, S. Jee, Y. Cho, and B. Kim, “The Doherty Power Ampliﬁer: Review of Recent Solutions and Trends,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 2, pp. 559–571, Feb. 2015.  I. Bahl, Lumped Elements for RF and Microwave Circuits. Boston, MA: Artech House Inc., 2003.
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