Introduction. High voltage GaN HEMTs are leading cont conversion and switching applications [1 physics-based compact device model for technology is ...
High Voltage GaN HEMT ccompact model: Experimental verificattion, Field plate optim mization and Charge trapping Ujwal Radhakrishna, Danieel Piedra, Yuhao Zhang, Tomás Palacios, Dimitrri Antoniadis Microsystems Technology Laboratoories, Massachusetts Institute of Technology, Cambridge, MA 02139, USA {ujwaal, dpiedra, yzhang, tpalacios, daa}@mit.edu Introduction High voltage GaN HEMTs are leading conttenders for power conversion and switching applications [11]. An accurate physics-based compact device model forr this emerging technology is essential for device and circuiit design. Several GaN HEMT compact models have been disccussed but are not physics-based [2]-[3]. Here, a new physics-based compact model for HV-GaN HEMTs, the MIT Virtual Source HV) is proposed. GaNFET- High Voltage model (MVS-G-H The model is geometry scalable and capptures static and dynamic device behavior through self-consiistent current and charge expressions. The access regions, whiich are important in device linearity [4] and reverse voltagge blocking, are modeled as implicit-gated transistors. The m model includes the effect of field plates and can be used to maxximize the BV2 Gon figure-of-merit. In addition, ‘knee-walkout’’ in these devices is captured in the model through a simpple trap-transistor model. The model requires a small numbeer of parameters with straightforward physical meanings aand is validated against DC–IV, S-parameter, breakdow wn and pulsed measurements of fabricated devices.
velocity saturation with gate length scaling is achieved using n charges in (Eqs. 3a-3b), Fvsat (Eq. 2). The source and drain have similar form as in [5]. .
2
.
2
(
1
)
(
1
(3a)
,
)
,
(3b)
Here Ff,s and Ff,d are Fermi-like fu unctions [5] which enable threshold voltage shift between strrong and weak inversion regimes, n is the subthreshold facttor and ϕt is the thermal voltage. The MVS-G-HV formulation resembles the EKV model [6] in the long-channel limitt and the MIT-VS model [5] in the short-channel limit. Time dependent self-heating is t (Eq. 4) using RC included in the model parameters through (=RthCth) thermal network. T
1
;
(1
,
ΔT)
(4)
The channel charges and their derrivatives, Cgs and Cgd are self-consistently solved as in (Eq qs. 5a-5b) using current continuity, GCA and charge partitioning. ,
,
,
,
,
,
,
,
,
,
,
,
,
,
(5a) (5b)
Access region and field plated regiion model
Figure 1. (a) Cross-sectional schematic of the fabricaated HV-AlGaN/GaN HEMTs on Si. (b) The equivalent circuit for the model with intrinsic transistor and implicit-gate access region transistors is sshown.
Fig. 1 shows the cross-sectional schematic of fabricated device without field plate along wiith the sub-circuit model. The access regions are modeled sim milar to the intrinsic device using (Eqs. 1-5). There is no physiical gate in these regions and an implicit-gate-overdrive (VIg –Vt0,I) is linked to the 2DEG sheet resistance (Rsh) as in (E Eq. 6). ,
Transport and charge model for intrinsic transistor The intrinsic transistor current (ID) in MVS-G-HV (Eq.1) has a similar form as in [5] which is a modell for scaled gate length RF-GaN HEMTs. /
(
. )
.
(
.
(1) .
)/ /
(
.
.
(2)
)/
Here vsat is saturation velocity, μ is mobilityy and Cg is arealgate-capacitance. Drift-diffusion transport is captured by employing gradual channel approximation (GCA) resulting in ID which has dependency on drain chargge in addition to charge at the virtual source. The transition ffrom pinch-off to
978-1-4799-2306-9/13/$31.00 ©2013 IEEE
(6)
CIg
CIg is the implicit-gate capacitan nce which is the only additional parameter needed for modeling the access regions. This model captures source and drrain-end depletion of the 2DEG in the device that is responsible for non-linear access region behavior and hence affectss device linearity [4]. In addition to potential continuity, fieeld continuity is ensured between different regions of the device using an analytical solution to quasi-2D Poisson equaation (Eqs. 7a-7b) which gives the peak field at intrinsic draain (Edi) and the channellength-modulation length (Lclm). Here is GaN is the average 2D DEG thickness which is a permittivity, fitting parameter.
32.7.1
Λ
(
)
,
(7a)
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,
cosh
;Λ
/
(7b)
h measurements using the derivatives give a good match with same CgI parameter used for the TLM Ms.
The source- and/or gate-connected fieldd plate regions depicted in Fig. 2 are also modeled usingg (Eqs. 1-6) with their own gate capacitances (Cggfp, Cgsfp) and threshold voltages (Vtgfp, Vtsfp), which can be exxtracted through independent CV measurements.
Figure 3. (a) Current voltage characteristiics of ungated TLM structures compared with implicit-gate transistor modell. The profile was obtained from I-Vs of TLMs with lengths of 6, 10, 15, 20 and 25 µm. The non-linear behavior is captured by pinch-off and velocity saturation. (b) The contact (Rc) and sheet resistance (Rsh) were extraacted from low field resistance measurements of TLMs as shown.
Figure 2. (a) Cross sectional schematic of the fabricaated device with field plates is shown. (b) The field plates are connected to either source or gate and the two configurations are modeled using the sub-ccircuit models shown. Field continuity in addition to potential continuity iss ensured at intrinsic nodes by solving quasi-2D-Poisson equation.
Field continuity at intrinsic nodes gives an acccurate picture of peak fields in different regions (similar too Eqs. 7a-7b for other regions), which can be used to estiimate breakdown voltage (BV) for different field plate configuurations. Simple charge trapping model The phenomenon of current collapse and asssociated increase in Ron in these devices has been attributed too charge trapping and virtual-gate formation in the drain acceess region next to the gate [7]-[8]. The MVS-G-HV model caaptures this effect by including a trap-transistor of gate length (Lg,trap) as in (Eq. 8a) whose gate-overdrive voltage is affectted by the stress field in the quiescent off state in pulsed modde of operation as given in (Eq. 8b). (8a)
, ,
CIg
Figure 4. Output, transfer, output and transsconductance plots of Lg=2 µm and Lgd= 16 µm (no field plate) device. Goo od agreement has been achieved between the model and measurement. The drrop in gm beyond Vt is caused in the model by the non-linear access region beh havior and device self-heating.
The charge model is validated again nst gate capacitance (Cgg) as shown in Fig. 5, which was obttained from S-parameters measured with Agilent N5230A.
(8b)
Here is the gate overdrive of thhe trap-transistor , and VdQ and VgQ are off-state quiescent draain and gate bias voltages respectively. Since trapping is heavily technology dependent, the model in (Eqs. 8a-8b) is pphenomenological with the fitting parameter dependent on faabrication process and device specifics. Results and discussion The implicit-gate model is compared againsst TLM structures as shown in Fig. 3. With the same set off parameters, the model gives good match with measuremennts. The model is then compared against Lg=2μm HEMT devvice (without any field plate connection) as shown in Fig. 4. T The current and its
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Figure 5. Charge model is verified from gatee capacitance fits of the model to device measurements obtained from S-paraameter measurements. Fringing capacitance (Cof = 2.5 pF/mm) extracted from f measurements is the only additional parameter needed for the fits.
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The field plated version of the model is ccompared against source- and gate-connected field plateed devices (the schematic shown in Fig. 5) on the same die. The fits are shown in Figs. 6 and 7 and give goood match with measurements employing the same set off parameters that were used for the fits in Fig. 4.
given Lgd as more of the drain accesss region is covered by the field plate with lower 2DEG densitty. The potential drops in different regions of the device shown in Fig. 8b are significantly affected by the presencce of field plates but show no change with the length of the field plate (Lsfp) due to he peak fields however, pinch-off in different regions. Th change with Lsfp and can be used to estimate the BV as a function of Lsfp (BV is the voltagee when peak field in the device reaches 3 MV/cm). Withou ut field plate, the device breaks at gate edge at a low BV of about a 65 V as seen in Fig. 8c and for Lsfp =6 μm, BV is abou ut 110 V with breakdown field occurring at the field plate edge. As Lsfp is increased, the Esfpi) drops while the field peak field in the field plate region (E at drain edge (Ed) rises. At Lsfp =10 0 μm, breakdown shifts to drain edge and BV=450 V can be b achieved. Beyond this length, Ed continues to rise, causing breakdown to be reached at lower voltage. The optimum Lsfpp, which is 10 μm, can be found from the plot of BV, as shown n in Fig. 8d.
Figure 6. The device fits for a source-connected fielld plated device with Lg=2 µm and Lgd= 16 µm and Lsfp= 6 µm. The above fitts were obtained using the same set of parameters used for the non-field platedd device shown in Fig. 4 along with additional field plate transistor parameteers namely: The gate capacitance of source field plate transistor (Cgsfp) and its threshold voltage (Vtsfp) which are extracted though independent measurem ments.
Figure 8. (a) The increase in Ron with increasing field plate length is demonstrated using the model for a source-connected field plated device with Lgd= 16 µm. As Lsfp is made longer, the drain n access region resistance increases due to the 2DEG depletion below increasingly longer field-plated region. (Here Vt0,sfp has been increased from -39 V to -19 V to show a clear increase of Ron) (b) The off-state voltage distribution in different d regions of the device is affected by field plate but shows no change for f Lsfp >= 3 µm. (c) The peak field distribution changes significantly with Lsfp. As A Lsfp is increased, the BV field (~3 MV/cm) shifts from source field plate edg ge to drain edge, increasing BV. (d)The BV predicted by the model matchees closely with the measured BV. Since there is a trade-off between Ron and BV V, the figure-of-merit (BV2 Gon) has an optimum maximum point at Lsfp = 10 µm.
Figure 7. The device fits for a gate-connected field plaated device with Lg=2 µm and Lgd= 16 µm and Lgfp= 3 µm. The gate capacitannce of gate field plate transistor (Cggfp) and its threshold voltage (Vtgfp) are the additional parameters.
The benchmarked model can be used to studdy the Ron vs. BV trade-off that exists in field plate design. F For this study we chose the source connected field plate structuure. From Fig. 8a it is clear that Ron increases with field plate llength (Lsfp) for a
Pulsed IV measurements were done on MOS-HEMTs without post-gate SiN passivation (but with 20 nm Al2O3 gions) using Auriga-4750 gate-oxide covering the access reg and the effect of drain (VdQ) and gate g (VgQ) off-state stress voltages on the on-state current aree shown in Figs. 9a. The devices exhibit ‘knee-walkout’ resullting in increasing Ron and reduced Ion. The Auriga pulse sy ystem was simulated in Spectre and the model with the traap transistor (as shown in Fig. 9b) exhibits a similar ‘kneee-walkout’ behavior with
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stress voltages, which matches well with measurements as can be seen from Fig. 9c. Since de-trapping effects cannot be seen from pulsed IV measurements betweenn 500 ns to 10 μs, the effect is shown using the model as prooof-of-concept in Fig. 9d. Key model parameters for the fits arre in Table 1.
[4] K. Shinohara et. al, IEDM, pp. 27.2.1-27.2.4, Dec. 2012. [5] U. Radhakrishna et.al, IEDM, pp. 13.6.1-13.6.4, Dec. 2012. [6] M. Bucher et. al, LEG, EPFL, 1997. [7] R. Vetury et. al, IEEE. TED, Vol. 48, No.. 3, Mar. 2001. [8] D. Jin et. al, ISPSD 24, Jun. 2012.
nd charge fitted to HEMTs Table 1: Key parameters for transport an Parameters
Values
Notes
Extracted param meters Lg (μm)
2
Channel length
Ls (μm)
1.5
So ource access region length
Ld (μm)
16
Drain access region length
Cg (F/cm )
3.5e-7
Areal gate capacitance
Rsh (ohm/sq.)
480
Sheet resistance of access region
2
RC (ohm-mm)
Figure 9. Pulsed IV measured for VgNQ=0V under differrent off state (a) drain stress (VdQ) and gate stress (VgQ) is shown. As the stresss voltage is increased the Ron increases and the well-known knee-walkkout phenomenon is observed. (b) This is modeled by using a simple trap transistor next to the gate on the drain side to mimic charge-trapping effect. The model is tested against the pulsed IV measurements with typical ddrain and gate pulse waveforms used for simulations as shown. (c) The moodel results (lines) are compared against measurements (data points) for differrent VdQ as in (a) and shows similar behavior as measurements. (d) The eeffect of de-trapping lifetime (tdt) on Ion is shown using the model as prooof-of-concept using a simple RC (=tdt) network. The Model is not calibratedd, as measurements of fabricated devices do not show significant lifetime deependencies for pulse widths from 500 ns to 10 µs indicating larger tdt. Thhe model can capture significant Ron change with tdt.
References [1] U. K. Mishra et.al, Proc. of IEEE, 90(6): 1022-1031, Jun. 2002. [2] L. Dunleavy et. al, Microwave Mag.,vol. 11, No. 6, ppp. 82-96, Oct. 10. [3] I. Angelov et.al, Proc. APM Conf., pp. 279–282, Deec. 2006.
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Contact resistance
1600
Low-field mobility
Vt0 (V)
-3.3
Thrreshold voltage for Vd~0V
Cgsfp, Cggfp [F/mm]
3e-8
Fieeld plate areal capacitance
Vt0,sfp ,Vt0,gfp (V)
-39
Field-plaate threshold voltage for Vd~0V
Electrostatic fitting parameters
(V/V) SS [V/Dec]
3.5
Sub-th hreshold transition parameter
0.01
Draiin-induced-barrier-lowering
0.14
Sub-threshold swing
Transport fitting parameters Vxo (cm/s)
Conclusions A physics-based compact transport and chargge model for HVGaN HEMTs has been developed and vvalidated against experimental data. The model is implementted in Verilog-A, and is suitable for GaN FET circuit simulatioons.
0.6
(cm2/Vs)
1.1e7
Saturation velocity
1.5
Laterral-field saturation parameter
1.9
Trapping parameter
(W/K)
100
Thermal resistance
(K. s/W)
100
Thermal Capacitance
2.3
Mob bility self-heating parameter
Acknowledgements The authors would like to thank D. S. Lee and O. I. Saadat for helping with measurements and Prof. J. D. Alamo for his review and comments. This work was w supported by the MIT SMART-LEES program, the FCR RP MSD-Centre program, the MIT GaN Energy Initiative an nd the ARPA-E ADEPT program.
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