3D Silicon Integration - IEEE Xplore

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IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New ... IBM Systems and Technology Group, 1000 River Street, Essex Junction, ...

3D Silicon Integration J.U. Knickerbocker, P.S. Andry, B. Dang, R.R. Horton, C S. Patel, R.J. Polastre, K. Sakuma*, E.S. Sprogis**, C.K. Tsang, B.C. Webb, and S.L. Wright IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598 * IBM Tokyo Research Laboratory, 1623-14 Shimo-tsuruma, Yamato, Kanagawa 242-8502 ** IBM Systems and Technology Group, 1000 River Street, Essex Junction, Vermont 05452 Email: [email protected], Tel: 914-945-3306 Abstract Three-dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Integration options can leverage stacked die and/or silicon packages depending on applications. The enabling technology elements include: (i) through-silicon-vias (TSV) with thinned silicon wafers, (ii) fine pitch wiring, (iii) fine pitch interconnection between stacked die, (iv) fine pitch test for known-good die, and (v) power delivery, distribution and thermal cooling technology. Applications may range from miniaturization of portable electronics like image sensors and cell phones to power efficient, high performance computing solutions such as servers and super computers. Silicon based packaging and 3D stacked die technologies have been in research studies for more than a decade at IBM and in industry, universities & consortia. IBM research experiments have included test vehicle design, build, characterization and modeling. Robust structures and processes have been developed based on (i) process learning for silicon based structures, (ii) assembly process comparisons for fine pitch chip interconnection, (iii) electrical, mechanical and thermal characterization and (iv) reliability & accelerated stress characterization. TSV technology investigations have included composite, copper and tungsten metallurgies. Wiring demonstrations ranged from sub-micron fine pitch wiring line widths & spaces to larger dimensions. I/O interconnections investigated feature sizes such as 100 I/O / mm2, 400 I/O/mm2, and interconnection features sizes which support 2500 I/O / mm2. In addition, integrated decoupling capacitors of one hundred ten nano-farads per mm2 per layer and assembly of module structures on silicon packages with ceramic or organic base packages were demonstrated. Examples of robust TSV structures and characterization, single die with silicon interposers, multiple die on a silicon package and stacked die assemblies are given along with highlights of characterization including aspects of electrical, mechanical and reliability results. This research paper describes recent advances in industry and reports advancements from IBM in the design, technical challenges and progress toward 3D chip integration structures. In addition, examples of potential applications that may take advantage of 3D integration are discussed. Introduction Future products may benefit from use of three dimensional chip integration for a variety of applications. For portable electronic systems using a portable cell phone as one

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example, opportunities for increased function and longer battery life may be important. Product design for higher end cell phones may wish to add function such as multiple wireless communications protocol for global travelers, add music function, camera function, and multimedia function while keeping the product at the same physical size and minimizing power consumption. Product design for entry cell phones may have higher priority to minimize cost and also minimize power consumption. In either case, 3D chip integration may offer the opportunity for the cell phone system to be tailored to meet product objectives. As CMOS scaling slows down, continued performance scaling for high performance computing may benefit from 3D chip integration [1, 2]. 3D integration may also provide opportunity for power efficiency, increased bandwidth interconnection and reduced latency operation [3, 4]. Similarly, 3D chip integration technology has opportunity for product advancement in applications such as image sensors, emerging bio-electronics, and other new applications. Heterogeneous 3D integration of technology may open up new product opportunities and shrinkage of size or form factors that previously were not possible or were cost prohibitive. Key technology elements include: (i) through-silicon-vias (TSV) with thinned wafers (ii) fine pitch wiring or signal redistribution, (iii) fine pitch interconnection between stacked die (Si stack or die to Si package), (iv) fine pitch test for known-good die and (v) power delivery, distribution and thermal cooling solutions. Multiple test vehicles have been designed, built, assembled and characterized. These technology demonstrations which are run at various integration densities have led to initial 3D groundrules which are believed viable for product consideration. From the research studies, materials, structures, build, assembly and test processes as well as physical, mechanical, electrical and reliability characterization have been performed. This paper will report on 3D industry advancements and report on results from IBM test vehicle demonstrations. Examples of potential applications and technology trends are also discussed. Industry Advancements in 3D Silicon Technology Semiconductor technology has driven not only lithography advancements for decades but also increased density with added wiring levels on wafer, in packages and in board technologies. For decades transistor doubling on chip every 12 to 18 months has also led to on chip circuit integration density which has far outstripped off chip interconnection to packages and boards. Over the last 5


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decades, three dimensional module integration included semiconductor die, packages and printed wiring board advancements. The first stages of 3D microelectronic modules began with the introduction of multiple wiring levels on wafer, multi-layer packaging and dual sided boards in the 1960’s. Manufacturing volumes scales during the 1960’s and 1970’s [5, 6]. During the 1980’s and 1990’s, more advanced multi-layer ceramic and organic packages were introduced, higher layer count board technologies evolved and wirebond chip stacks and system in package (SIP) technology emerged [7, 8, 9, 10]. However in each of these cases, the interconnection densities were limited to package level interconnection densities of 103 I/O per cm2 compared to on chip interconnection densities of 108 interconnections / cm2. In the 1990’s and 2000’, continued advancement in 3D chip integration has led to fine pitch, though-silicon-vias (TSV), thinned silicon used in die stacks and silicon packaging, fine pitch silicon to silicon interconnections, and an evolving growth in materials, equipment and infrastructure to support 3D silicon integration. These new class of 3D silicon integration technologies offer the ability to reduce circuit to circuit interconnection length, improve power efficiency and provide improved bandwidth similar to on chip interconnection (108 interconnections / cm2) even for heterogeneous chip interconnection. First products using TSV are beginning to enter manufacturing while the infrastructure to leverage new 3D stacked silicon integration technologies is still emerging. New 3D architecture, design tools, TSV fabrication tools, bond and assembly technologies and tools, test and manufacturing volumes for 3D are still evolving. 3D design tools exist which can support some level of mechanical and thermal modeling, however full 3D electrical design tools and 3D trade-off tools need to be developed. Similarly, alignment and bonding tools today can support some level of chip to chip, chip to wafer and wafer to wafer processing, however these tools and processes are likely to continue to evolve to reach more robust manufacturing levels. Examples of TSV research published from IBM include: (i) small sizes and silicon thickness of < 0.2 um diameter and SOI to few microns silicon thickness, respectively [11, 12], (ii) 1 to 20 um diameter or width and silicon thickness of a few microns to about 100 um thickness [13, 14], and (iii) large TSV with 20 um to 90 um diameter and silicon thickness of 50 to 300 um [13, 14, 15, 16]. Results have been published from Fraunhofer Institute (Germany), ASET (Japan), IMEC (Europe), SEMATECH (USA-International) and many other Universities, Consortia and individual companies from around the world. Numerous processes from via’s first, vias middle and via’s last processing have been discussed along with a variety of structures and conductors such as copper, tungsten, doped poly-silicon and composite vias. First manufacturing products using TSV’s have been announced by IBM [17] and Toshiba [18] to be shipped in 2008. Examples of thinned silicon and fine pitch interconnection research reported from IBM have included oxide to oxide bonding, copper to copper bonding and tin or solder enhanced metal bonding for wafer to wafer processes

[11, 12]. For die to die and die to wafer fine pitch interconnections, joining processes have included solder attach, copper to copper and adhesive joining [19, 20, 21]. Examples of IBM 3D Test Vehicle Design, Build, Assembly & Characterization Dating from technology review meetings in the 1990’s, system roadmaps and from more recent science and technology roadmaps [1, 2], IBM has continued to (i) advance CMOS technology, (ii) driven 3D subsystem integration including: 3D silicon chip integration, 3D packaging and optical integration, (iii) pursued post CMOS technology and (iv) advanced toward quantum computing. From the technology reviews and roadmap planning, 3D silicon research investigations were expanded in the 1990’s and have continued to present. IBM Research has pursued 3D silicon integration technology through efforts in (i) wafer to wafer processing, (ii) die on silicon wafer, (iii) die on silicon package and (iv) die on die technologies. A schematic representation of 3D die stacking and 3D packaging is shown in Figure 1. A variety of test vehicles have been utilized to help develop 3D technology elements including the TSV with thinned silicon, fine pitch wiring, fine pitch interconnection, fine pitch test and characterization including: electrical, mechanical, thermal and reliability assessments. Depending on application requirements, options in design and system architecture can be balanced against the structure, process and, assembly approach which might best meet the product objective with reasonable manufacturing yields and costs. Therefore, in order to establish these structures, materials and processes, specific designs were created to permit comparison of design ground-rules, assess wafer fabrication, assess assembly, assess test and develop data libraries from measurements and models. Results from these studies have helped develop robust processes to meet future product needs. A Cooling


Decoupling Capacitors

B Die Stack TSV Vertical Interconnection

Si Pkg or Pkg


Substrate or PWB

Figure 1: Schematic cross section for A. 3D silicon package and B. 3D die stacks or 3D integrated test structure.


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This paper will report on a few of these test vehicles. Figure 2 provides examples of test vehicles used for demonstrations. One of many TSV test vehicle is shown in Figure 2A and a fine pitch interconnection test vehicle with fine pitch wiring which supports electrical characterization and reliability studies is shown in Figure 2B.. Figure 2C shows a TSV and integrated passive function test vehicle having integrated decoupling capacitors and an optoelectronic transceiver is shown in Figure 2D. Collectively, these test vehicles and others have provided substantial process learning, assembly learning, module characterization and reliability data. Results have led to robust design rules, processes and structures with a database including electrical, mechanical and thermal, yield and reliability characteristics. A compilation of data from these and ongoing studies are providing new data into a design library, permit the comparison of measured data with ongoing 3D simulations against electrical, mechanical and thermal models. Output from the measurements and simulations help support next generations of CMOS compatible products.



Top view

Chain links Cross-section

B Microbump

Area array connections & wiring


Test Chain

Cooling Chip

Substrate D Silicon Thruvia

Design and Interconnection Density Design for 3D and interconnection density architecture is important for a variety of reasons. At the silicon layer or strata level, the design and interconnection density between these strata can be impacted by TSV and interconnection density from a circuit density and utilization efficiency, macro-design, wafer fabrication, assembly, test, yield and cost perspectives. For two or more silicon layers or strata, the design and interconnection density can be important from a power delivery, cooling, interconnection length and electrical parametric perspective and can impact system performance, power efficiency, layer design or co-design, cooling design, time to market and costs. As the industry begins to advance 3D technology, many elements of 3D stacked structures may also become important from a standards and common practice across foundries, packaging, assembly and test companies. For example, integration across one or more heterogeneous technologies coming from one or more foundries may help drive the need for common interconnection density footprints as well as common design platforms from which to create silicon based 3D integrated products to avoid added redistribution wiring between silicon layers or strata.. Even within one company, developing CMOS compatible structures at IBM has evolved across multiple three dimension integration teams. The 3D teams, collaborate and compliment one another for results from test vehicle demonstrations and technology studies. For example two research teams have driven studies which cover a wide range of feature sizes for CMOS compatible structures. A relative comparison of the interconnection densities was previously reported in 2005 compared to traditional off chip packaging interconnection densities [14] and has been updated in 2008 [4]. A relative comparison of feature sizes and function is shown in Table 1. One can see that the 3DIC integration investigations cover a range in interconnection and TSV feature sizes from about 0.14 microns diameter to about 10 microns size and SOP/3D integration studies have captured feature sizes from about 1 micron to about 100 microns diameter. For this paper, a focus is placed on the SOP/3D stacking test vehicles and results.

Decoupling Capacitors




Organic Chip Package Figure 2: Examples of demonstration test vehicles including: A. Through silicon via (TSV) & Stacking test vehicle, B. Fine pitch wiring, fine pitch interconnection & reliability test vehicle, C. TSV & Integrated passives TV, and D. Electro-Optic Transceiver TV.



Via Size (smallest) Via Size (largest) Via Pitch (smallest) Via Pitch (largest) Interconnection Density Silicon thickness (Min) Silicon Thickness (Max) Passive Function Active circuits

0.14 µm 10 µm 0.4 µm 200 µm 105 – 108/cm2 SOI – 2.0 µm 70 µm Yes Yes

SOP/3D Stacking 1.0 µm 90 µm 10 µm 200 µm 101 – 106/cm2 4.0 µm 50 – 300 µm Yes Yes

TABLE 1 : Relative Interconnection density comparison [4, 11, 12, 13, 14].


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Through-silicon-vias (TSV) Through silicon vias (TSV’s) have been fabricated in a variety of test vehicles with different structures such as circular holes, annular vias and bar vias with a specified diameter, width and height of the targeted silicon strata or silicon layer thickness. TSV’s with different geometric shapes have been fabricated and are reported in more detail elsewhere [13, 14, 15, 16, 17]. For silicon thickness of 50 to 300 µm, the fabrication process, geometry, dielectric, adhesive and barrier layers and conductor can have impact on the TSV characteristics such as electrical properties, mechanical properties, thermal properties as well as reliability. Examples of cross sections, fabrication processes and reliability at 50 µm silicon thickness (Figure 2A), 150 µm and 300 µm have already been reported [14, 15]. Fine pitch interconnection , assembly and die stacking For die stacking and high bandwidth connections between silicon die and silicon packages, , fine pitch interconnection between silicon layers or strata is needed in addition to through silicon vias (TSV’s). Interconnection studies have included copper to copper bonding as well as fine pitch solder or transient liquid solder interconnections [21, 23, 24]. Small area interconnections have unique challenges compared to traditional interconnections and also depend on the approach for bond and assembly. Figure 3 shows a relative comparison for assembly approaches including chip to chip, chip to wafer and wafer to wafer bonding. Choice of the appropriate bonding approach is dependent upon many factors such as die size, interconnection density, planarity, die yield, alignment and bonding yield to name a few.

Chip to Chip

Chip to Wafer

Wafer to wafer


Flexible, use of KGD

Flexible, use of KGD

Low cost


Handling and bonding

Handling and bonding

Overall yield, chip size

Wafer thickness

< 4 µm to > 150 µm

< 4 µm to > 150 µm

< 4 µm to > 150 µm

Bonding technolo gy



Metal to Metal

Metal to Metal

Solder or Metal



Oxide bonding Adhesive

Figure 3 Alignment, bond and assembly comparison for die to die, die to wafer and wafer to wafer assembly.

Test vehicles have been used to study die stacks such as contact resistance in electrical chains consisting of TSV, silicon to silicon interconnections and links. Examples of these die stacks are reported along with electrical characteristics [23, 25]. Figure 4 shows an example of thinned, stacked silicon with TSV and thin silicon to silicon interconnections. Six high stacked die had 70 µm thickness per silicon strata or layer and interconnections of less than 6 70 µm thickness. Similarly studies on fabrication, assembly, electrical and optical characterization have been reported on optoelectronic module assemblies as depicted in Figure 2D [15].

Figure 4 shows six high thinned silicon layers with TSV and thin silicon interconnections [23]. Fine pitch wiring and integrated function Results from studies of silicon electrical wiring based on test vehicle fabrication, measurements and models have been established with frequency domain and time domain results. From the studies electrical characterization for TSV’s, fine pitch interconnections such as micro-bumps and fine pitch wiring have been evaluated. Data include signal integrity versus distance, data rate and cross talk noise for distances from a less than 3 mm to 75mm. Results showed a relative 10x to 100X increase in wiring density and approximately 8x to over 50x increase in relative bandwidth is possible with silicon packaging compared to traditional packages [15, 26]. Additional results are planned for publication in 2008 [25]. As previously reported, test vehicles can include passive and active circuit function in addition to TSV’s, power distribution and/or wiring [26]. As depicted in the Figure 2C schematic and shown in assembled module hardware stack shown in Figure 5, a test vehicle with integrated decoupling capacitors was designed, fabricated, assembled and characterized. Measurements showed the test vehicle with TSV and trench decoupling capacitors showed a capacitance level of greater than 12 microfarads / cm2. Application of the silicon-based interposer with decoupling capacitors can provide low inductance decoupling capacitance for high performance chips and reduce or eliminate the need for discrete decoupling capacitors based on electrical modeling. Electrical testing thinned silicon packages and die Testing of thin silicon wafers can be accomplished prior to thinning, while the thinned silicon is attached to a mechanical handle wafer and after attaching the thinned wafer


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Summary 3D silicon integration using TSV’s, thinned silicon and silicon to silicon interconnections continues to be studied in the industry and at IBM. First product announcements indicate products shipments will begin in 2008. Advancements in groundrules and continued development of stacked structures are likely to be utilized in future products as systems architects determine optimal designs. Application designs can lead to improvements in performance, power efficiency and cost reductions. 3D test vehicles at IBM are continuing to provide a means to study structures and processes as well as provide data for improved electrical, mechanical, thermal and reliability understanding. These studies and results will help to drive groundrules which can be used by designers for system use of 3D silicon integrated modules. Examples of 3D test vehicles include TSV, fine pitch interconnection, chip stacking, and integrated passives test vehicles. New applications such as image sensors and future computing applications and miniaturized form factors for portable electronics are likely to benefit from 3D silicon products.

A Chip Si Interposer


Figure 5 showing a silicon chip mounted on the thinned silicon interposer with integrated decoupling capacitors (5A) and the stacked structure mounted on an organic substrate (5B). to another wafer or individual thinned silicon components to a substrate or silicon die / die stack. A testing methodology for any given application will depend on factors such as cost tradeoffs for benefit of pre-testing for known good die, die stacks and / or packages versus test once the assembled structure or product can be socket tested and burned in. Power delivery, distribution and thermal cooling Another important consideration in 3D integration (such as die stacks and high density interconnected packages with heterogeneous assembled die) is power delivery, distribution and 3D thermal cooling. For 3D stacked die, power delivery to each die or silicon strata level is important and requires adequate power and ground vias and power buses to feed the 3D structure without causing significant voltage swings during operation. In addition, the effectiveness of the architecture and design utilization for circuits versus TSV and interconnections can be important. Just as it is important to consider power delivery and distribution, design considerations and planning is important for thermal cooling in the stack. Examples of thermal and thermal-mechanical modeling have been reported [14, 27]. Liquid cooling may also be important as circuit density is increased in 3D die stacks and for integrated die or die stacks on silicon packages. Examples of liquid cooling with micro-channel coolers have been shown to support > 400 watts/cm2 cooling [28].

Acknowledgments This work has been partially supported by Maryland Procurement Office (MPO) – Contract H98230-04-C-0920 and Contract H98230-07-C-0409.. We acknowledge the support from research MRL and CSS groups, the IBM analytical group in East Fishkill, NY, the development and support teams in East Fishkill, NY and Burlington, VT. We would also like to acknowledge the management support of T. Chainer, D. Seeger and T.C. Chen. References 1. T. Agerwala and M. Gupta, “ Systems research challenges, A scale-out perspective,” IBM J. Res. & Dev., Vol 50, NO 2/3 (2006) 2. T.C. Chen, “Where Si-CMOS is Going: Trendy Hype vs Real Technology, “Keynote ISSCC 2006. 3. Philip Emma et al., submission IBM J R&D, 2008. 4. J.U. Knickerbocker et al., submssion IBM J R&D, 2008 5. Fundamentals of Microsystems Packaging, R. R. Tummala Ed., McGraw-Hill, New York, 2001. 6. Microelectronics Packaging Handbook, R. R. Tummala, E. J. Rymaszewski and A. J. Klopfenskin, Eds., Van Nostrand Reinhold, New York, 1989. 7. A. J. Blodget, A Multilayer Ceramic Multichip Module,” IEEE Trans. Components, Hybrids Manufact. Technology, CHMT-3 May 1980. 8. Y.F. Yao et al., “Assembly Process Development of 50um Fine Pitch Wire Bonded Devices,” ECTC 2004, p 365-371 (2004). 9. Muhannad S. Bakir and James D. Meindl, “Integrated Electrical, Optical, and Thermal High Density and Compliant Wafer-Level Chip I/O Interconnections for Gigascale Integration SIP reference,” ECTC pp 1-6 (2004)


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10. Y. Orii and T. Nishio, “Ultra-Thin POP Technologies using 50 3m pitch Flip Chip C4 Interconnections,” ECTC 2007. 11. K.W. Guarini et al., “Electrical Integrity of State-of-theArt 0.13 um SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication,” IEDM Tech Dig., 943-945 (2002). 12. A. W. Topol et al. “Three- Dimensional Integrated Circuits,” IBM J. Res. Dev., Manuscript submitted for 2006 publication. 13. Andry, P., et al, “A CMOS-compatible process for fabricating electrical through-vias in silicon,” Proc 56th Electronic Components and Technology Conf., San Diego, CA, 2006. 14. J. U. Knickerbocker et al, “Development of nextgeneration systeom-on-package (SOP) technology based on silicon carriers with fine-pitch interconnection,” IBM J. Res. Dev. 49(4/5), 2005, pp. 725-754. 15. C. S. Patel, et al, “Silicon Carrier with Deep ThroughVias, Fine Pitch Wiring, and Through Cavity for Parallel Optical Transceiver,” Proceedings of the 55th ECTC, 2005. p. 1318.C. Patel et al., ECTC 2005. 16. C. Tsang et al., “CMOS-Compatible Silicon Throughvias for 3D Process Integration,” MRS, 2006. 17. A. Joseph et al., submission to IBM J. Res. & Dev., 2008 18. K. Takahashi and M. Sekiguchi, “Through Silicon Via and 3-D Wafer/Chip Stacking Technology, VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on Volume , Issue , 2006 Page(s):89 – 92 19. M. Umemoto et al. (ASET), Electronic Components and Technology Conference 2004 20. M. Hunter et al., “Assembly & Reliability of Flip Chip Solder Joints Using Miniaturized Au/Sn Bumps”, ECTC 2004 21. S.L. Wright et al., “Characterization of Micro-bump C4 Interconnections for Si-Carrier SOP Applications,” Electronic Components and Technology Conference, pp 633-640 (2006). 22. Klump et al., “ Vertical System Interconnection by Using Inter-Chip Vias and Solid-Liquid Interdiffusion Bonding,” Jap. J. Applied Physics, Vol 43, No 7A, 2004 pp 829-830 23. K. Sakuma et al., “3D Chip Stacking Technology with Low-Volume Lead-Free Inerconnections,” Electronic Components and Technology Conference, 2007, pp 627632. 24. K. Sakuma et al., ‘‘Characterization of Stacked Die using Die-to-Wafer Integration for High Yield and Throughput,’’ Submitted ECTC 2008. 25. B. Dang et al., “Assembly, Characterization, and Reworkability of Pb-free Ultra-Fine Pitch C4s for System-on-Package,” Electronic Components and Technology Conference, 2007, pp 42-48. 26. C. Patel , submission IBM J R&D,2008. 27. J.U. Knickerbocker et al, “System-on-Package (SOP) Technology, Characterization and Applications,” ECTC 2006, pp 415-421

28. S. Sri-Jayantha et al., submission IBM J R&D 2008. 29. E.G. Colgan et al., “A Practical Implementation of Silicon Microchannel Coolers for High Power Chips “, IEEE SEMITHERM 2005, pp.1-7.


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