69-5 title_copyright.indd

Semiconductors, Dielectrics, and Metals for Nanoelectronics 13 Editors: S. Kar K. Kita D. Landheer D. Misra

Sponsoring Divisions: Dielectric Science & Technology Electronics and Photonics

Published by

TM

The Electrochemical Society 65 South Main Street, Building D Pennington, NJ 08534-2839, USA tel 609 737 1902 fax 609 737 2743 www.electrochem.org

Vol. 69, No. 5

Copyright 2015 by The Electrochemical Society. All rights reserved. This book has been registered with Copyright Clearance Center. For further information, please contact the Copyright Clearance Center, Salem, Massachusetts. Published by: The Electrochemical Society 65 South Main Street Pennington, New Jersey 08534-2839, USA Telephone 609.737.1902 Fax 609.737.2743 e-mail: [email protected] Web: www.electrochem.org ISSN 1938-6737 (online) ISSN 1938-5862 (print) ISSN 2151-2051 (cd-rom) ISBN 978-1-62332-312-7 (CD-ROM) ISBN 978-1-60768-670-5 (PDF) Printed in the United States of America.

Preface The papers included in this issue of ECS Transactions were originally presented in the symposium “Semiconductors, Dielectrics, and Metals for Nanoelectronics 13”, held during the 228th meeting of The Electrochemical Society, in Phoenix, AZ, from October 11 to October 15, 2015.

iii

ECS Transactions, Volume 69, Issue 5 Semiconductors, Dielectrics, and Metals for Nanoelectronics 13

Table of Contents

Preface

iii

Chapter 1 High Mobility Channel Optimized Novel Indium Antimonide Quantum Well Field Effect Transistor for High-Speed and Low Power Logic Applications R. Islam, M. M. Uddin, M. A. Matin

3

HfO2/Al2O3/InGaAs MOSCAP Structures and InGaAs Plasma Nitridation Elaborated in a 300mm Pilot Line M. Billaud, J. Duvernay, H. Grampeix, B. Pelissier, M. Martin, S. David, C. Vallée Sr., Z. Chalupa, H. Boutry, T. Baron, M. Cassé, T. Ernst, M. Vinet, G. Reimbold, O. Faynot

9

(Invited) Towards a Vertical and Damage Free Post-Etch InGaAs Fin Profile: Dry Etch Processing, Sidewall Damage Assessment and Mitigation Options U. Peralagu, X. Li, O. Ignatova, Y. C. Fu, D. A. J. Millar, M. J. Steer, I. M. Povey, K. Hossain, M. Jain, T. G. Golding, R. Droopad, P. K. Hurley, I. G. Thayne

15

(Invited) MOS Interface Control Technologies for Advanced III-V/ Ge Devices S. Takagi, C. Y. Chang, M. Yokoyama, K. Nishi, R. Zhang, M. Ke, J. H. Han, M. Takenaka

37

(Invited) Border Trap Density in Al2O3/InGaAs MOS: Dependence on Hydrogen Passivation and Bias Temperature Stress K. Tang, R. Droopad, P. C. McIntyre

53

(Invited) Surface Passivation of High-k Dielectric Materials on Diamond Thin Films K. K. Kovi, S. Majdi, M. Gabrysch, N. Suntornwipat, J. Isberg

61

v

Chapter 2 Nano Technology (Invited) Defects and Dopants in Silicon and Germanium Nanowires M. Fanciulli, M. Belli, S. Paleari, A. Lamperti, A. Molle, M. Sironi, A. Pizio

69

(Invited) Topological States in Multi-Orbital Honeycomb Lattices of HgTe (CdTe) Quantum Dots W. Beugeling, E. Kalesaki, C. Delerue, Y. M. Niquet, D. Vanmaekelbergh, C. Morais Smith

81

Utilization of a Non-Ionic Surfactant in the Fabrication of Water-Borne Polymeric Semiconductor Nanoparticles for High-Performance, Green Organic Electronics J. Cho, S. Yoon, J. Ha, D. S. Chung

89

Enhanced Charge-Transport Behavior on PbS Nanocrystals Capped with Atomic Ligands S. Yoon, J. U. Ha, J. Cho, D. S. Chung

95

Chapter 3 Gate Metal (Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI) D. Triyoso, R. Carter, J. Kluth, S. Luning, A. Child, J. Wahl, B. Mulfinger, K. Punchihewa, A. Kumar, L. Kang, R. Sporer, X. Chen, S. Straub, G. Bohra, S. Patil, X. Zhang, A. Chen, M. Togo, R. Pal

103

Chapter 4 Dielectrics Electrical Studies on Parylene-C Columnar Microfibrous Thin Films I. H. Khawaji, C. Chindam, W. Orfali, O. O. Awadelkarim, A. Lakhtakia

vi

113

Chapter 5 Memory The Effect of CoSi2 Formation Process on the CMOS Transistor Electrical Properties for Sub 100nm Memory Applications J. H. Park, S. J. Kim, J. H. Lee, C. J. Yoo, H. J. Kang, B. C. Lee, J. G. Jeong

123

(Invited) Variability in FinFET SRAM Cells K. Endo, S. O'uchi, T. Matsukawa, Y. Liu, M. Masahara

141

(Invited) Intrinsic Unipolar SiOx-Based Resistive Switching Memory: Characterization, Mechanism and Applications Y. F. Chang, B. Fowler, F. Zhou, J. C. Lee

149

(Invited) Novel Selector and 3D RRAM Development for High Density Non-Volatile Memory H. Yang, C. C. Tan, W. He, M. Li, Y. Jiang, Y. Yang

165

(Invited) White-Light-Induced Annihilation of Percolation Paths in SiO2 and High-k Dielectrics - Prospect for Gate Oxide Reliability Rejuvenation and Optical-Enabled Functions in CMOS Integrated Circuits D. S. Ang, T. Kawashima, Y. Zhou, K. S. Yew, M. K. Bera, H. Zhang

169

Three-Dimensional Fully-Coupled Electrical and Thermal Transport Model of Dynamic Switching in Oxide Memristors X. Gao, D. Mamaluy, P. R. Mickel, M. Marinella

183

Chapter 6 Interfaces, Traps, and Reliability (Invited) The Influence of Defects on the Electronic Properties of Hafnia D. R. Islamov, V. A. Gritsenko, T. V. Perevalov

197

(Invited) The Assessment of Border Traps in High-Mobility Channel Materials E. Simoen, A. Alian, H. Arimura, D. Lin, H. Mertens, J. Mitard, S. Sioncke, W. Fang, J. Luo, C. Zhao, A. Mocuta, N. Collaert, A. Thean, C. Claeys

205

Quantitative Characterization of Near-Interface Oxide Traps in 4H-SiC MOS Capacitors by Transient Capacitance Measurements Y. Fujino, K. Kita

219

vii

Chapter 7 Characterisation Negative Gate Transconductance in MIS Tunnel Diode Induced by Peripheral Minority Carrier Control Mechanism C. S. Liao, J. G. Hwu

229

Nanoscale Potential Fluctuation in Non-Stoichiometric Hafnium Suboxides O. M. Orlov, G. J. Krasnikov, V. A. Gritsenko, V. N. Kruchinin, T. V. Perevalov, V. S. Aliev, D. R. Islamov, I. P. Prosvirin

237

Tunneling Current Induced Frequency Dispersion in the C-V Behavior of Ultra-Thin Oxide MOS Capacitors C. F. Yang, J. G. Hwu

243

Physically Based Analytical Modeling of 2D Electrostatic Potential for Symmetric and Asymmetric Double Gate Junctionless Field Effect Transistors in Subthreshold Region I. Ahmed, Q. D. M. Khosru

249

Non-Uniform Hole Current Induced Negative Capacitance Phenomenon Examined by Photo-Illumination in MOS(n) H. H. Lin, Y. K. Lin, J. G. Hwu

261

Chapter 8 Ge, SiGe, GeSn Channel CMOS Compatible Growth of High Quality Ge, SiGe and SiGeSn for Photonic Device Applications M. A. Alher, A. Mosleh, L. Cousar, W. Dou, P. Grant, S. A. Ghetmiri, S. Al-Kabi, W. Du, M. Benamara, B. Li, M. Mortazavi, S. Q. Yu, H. A. Naseem

269

Enhancement of Material Quality of (Si)GeSn Films Grown by SnCl4 Precursor A. Mosleh, M. A. Alher, L. Cousar, H. Abusafe, W. Dou, P. Grant, S. Al-Kabi, S. A. Ghetmiri, B. Alharthi, H. Tran, W. Du, M. Benamara, B. Li, M. Mortazavi, S. Q. Yu, H. A. Naseem

279

(Invited) Effects of Ge Substrate Annealing in H2 on Electron Mobility as well as on Junction Leakage in n-channel Ge MOSFETs A. Toriumi, C. Lee, T. Nishimura

287

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Non-Thermal Equilibrium Formation of Ge1-xSnx (0≤x≤0.2) Crystals on Insulator by Pulsed Laser Annealing K. Moto, R. Matsumura, H. Chikita, T. Sadoh, H. Ikenoue, M. Miyao

297

Ultra-Low Temperature (~180°C) Solid-Phase Crystallization of GeSn on Insulator Triggered by Laser-Anneal Seeding R. Matsumura, K. Moto, Y. Kai, T. Sadoh, H. Ikenoue, M. Miyao

301

(Invited) Fabrication of High-Quality Ge-on-Insulator Structures by Lateral Liquid Phase Epitaxy T. Shimura, Y. Suzuki, M. Matsue, K. Kajimura, K. Tominaga, T. Amamoto, T. Hosoi, H. Watanabe

305

Electrical Characterization of Dry and Wet Processed Interface Layer in Ge/High-K Devices Y. M. Ding, D. Misra, M. Bhuyian, K. Tapily, R. D. Clark, S. Consiglio, C. S. Wajda, G. J. Leusink

313

Chapter 9 2D Channel (Invited) Excellent Wetting Behavior of Yttria on 2D Materials R. Addou, M. Batzill, R. M. Wallace

325

(Invited) Is the Silicene a 2D Dirac Material? T. Shirasawa

337

(Invited) Initial State of Graphene Growth on Ge(001) Surfaces J. Dabrowski, G. Lippert, G. Lupina

345

(Invited) Vertical Field Effect Transistor Based on Graphene/Transition Metal Dichalcogenide Van Der Waals Heterostructure R. Moriya, T. Yamaguchi, Y. Inoue, Y. Sata, S. Morikawa, S. Masubuchi, T. Machida

357

ix

(Invited) Electronic Properties of Self-Assembled Trimesic Acid Monolayer on Graphene Layers F. Shayeganfar

365

Author Index

371

x

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The online version is considered the final version and is fully citable with articles assigned specific page numbers within specific issues. The date of online publication is the official publication date of record. Electrochemistry Letters — (EEL) is one of the newest journals from ECS launched in 2012. It is dedicated to the rapid dissemination of peer-reviewed and concise research reports in fundamental and applied areas of electrochemical science and technology. Articles are published online as soon as possible after undergoing the peer-review process. The online version is considered the final version and is fully citable with articles assigned specific page numbers within specific issues. The date of online publication is the official publication date of record. Solid State Letters — (SSL) is one of the newest journals from ECS launched in 2012. It is dedicated to the rapid dissemination of peerreviewed and concise research reports in fundamental and applied areas of solid state science and technology. Articles are published online as soon as possible after undergoing the peer-review process. The online version is considered the final version and is fully citable with articles assigned specific page numbers within specific issues. The date of online publication is the official publication date of record. Electrochemical and Solid-State Letters — (ESL) was the first rapid-publication electronic journal dedicated to covering the leading edge of research and development in the field of solid-state and electrochemical science and technology. ESL was a joint publication of ECS and IEEE Electron Devices Society. Volume 1 began July 1998 and contained six issues, thereafter new volumes began with the January issue and contained 12 issues. The final issue of ESL was Volume 16, Number 6, 2012. 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Chapter 1 High Mobility Channel

ECS Transactions, 69 (5) 3-8 (2015) 10.1149/06905.0003ecst ©The Electrochemical Society

Optimized Novel Indium Antimonide Quantum Well Field Effect Transistor for High-Speed and Low Power Logic Applications R. Islama, M. M. Uddinb, M. A. Matina a

Department of Electrical & Electronic Engineering, Chittagong University of Engineering & Technology (CUET), Chittagong-4349, Bangladesh b Department of Physics, Chittagong University of Engineering & Technology (CUET), Chittagong-4349, Bangladesh

An optimized InSb QWFET with a very high electron mobility 4.42 m2V-1s-1 and density 1.47×1015 m-2 at Vg= 0V have been calculated using quantum corrected SchrödingerPoisson (QCSP) solution which is at least ~180 times greater than that of Si NMOS. Particularly noteworthy is that the 2DEG in 20 nm QW is completely depleted by a very small Vg= -0.25 V (pinch-off voltage Vp). A giant gate controllability ratio of dns/dVg is found to be ~ 5.2×1015 m-2 V-1. It indicates that the Fermi level EF is smoothly tuned by the Vg due to a very low interface state density Dit (7.8×1014-3.7×1016 m-2eV-1) at the interface between Al2O3 and Al0.1In0.9Sb top layer of the InSb QWFET, resulting a giant dns/dVg. The minimum value of capacitance in the CV curve has also been confirmed Vp=-0.25V where the channel is in off-state. . Introduction The physical gate length LG of the Si transistors are shrinking day by day to meet Moore’s law that states the number of transistors per integrated circuit doubles in every 24 months (1). It is projected that LG may be down to ∼20 nm. Therefore, it is urgent need to be “energy efficient” which operates with the lowest switching power. Several industry and academic research groups are investigating alternative structures and materials to circumvent this limit. III-V compound semiconductor is one of the leading candidates to replace main-stream Si as n-channel material due its much higher electron mobility. The lack of high-quality, thermodynamically stable gate dielectric insulators on III-V semiconductor that can maintain device quality similar SiO2 on Si. This is the main obstacle remains to realizing III-V QWFETs technology. However, a direct Schottky metal gate has been used in currently all of the devices due to lack of gate dielectric insulators, which results in a large parasitic gate leakage. Much effort has been paid to incorporate III-V nanoelectronics on the silicon platform due to highest intrinsic electron mobility. The InSb quantum well field effect transistor (QWFET) is a promising candidate for future high performance and low power logic applications (2, 3). Among III-V semiconductor materials InSb has the smallest effective mass of electrons results high electron mobility. InSb-based devices are attractive for high-speed (quantum well) field effect transistors, magnetic field sensors, ballistic transport devices, quantum

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ECS Transactions, 69 (5) 3-8 (2015)

devices, and spintronic applications. Moreover, the high electron mobility in the InSb quantum-well channel increases the switching speed and lowers the required supply voltage. Recent success in depositing high-quality Al2O3 gate dielectrics by atomic layer deposition (ALD) on the InSb quantum wells (QWs) and completely depletion of the two-dimensional electron gas (2DEG) confined in the InSb QW opens the prospects to fabricate high- quality InSb QWFET (4, 5). The device structure is one of the key parameters to achieve standard and effective FET characteristics of the InSb QWFET that requires optimizing the device structure. An optimized InSb QWFET device structure with high-performance and low power consumption is reported.

Device Structure The cross-sectional schematic of the proposed optimized device structure of an ALD Al2O3/Al0.1In0.9Sb QWFET with 20 nm InSb Quantum well as channel layer is shown in Figure. 1. A 2 nm Si δ-doped with 1×1012 cm-2 donor density is located 25 nm above the QW. A 10 nm thick Al2O3 layer was deposited using ALD technique. Indium was then evaporated for the ohmic contacts and the top gate.

Figure 1. Cross section of optimized InSb QWFET layer structure with LG=100 nm and Si δ-doping (dashed line).

Simulation Details In quantum well, discrete energy levels, the so called energy sub bands occur. The electronic sub bands of the conduction band and the corresponding envelope functions can be determined by solving the Schrödinger equation self-consistently with the Poisson equation (6, 7). The potential is calculated first due to the resulting charge distribution, adding it to the original band-edge potential, solving Schrödinger equation again, and so on until the update is below a certain limit, thus convergency is reached. According to the Matthiessen’s rules, the total mobility considering all scattering process and defined as

4

is computing by


[1]

where, [2]

[3]

[4] and [5]

[6] The symbols are bearing their usual meaning.

Results and Discussion

2.5

4.4

2.0

4.2

1.5

4.0

1.0

3.8 0

0.5 5 10 15 20 25 30 35 40 45 Spacer Width, nm

Electron density, ns (x1015 m-2)

Electron Mobility, µ (m2/Vs)

Spacer layer thickness optimization in barrier layer of device is essential. Electron density (ns) and mobility (µ) as function of space width is presented in Figure 2. It shows that 25 nm spacer layer with 45 nm barrier layer are optimum by considering highest µ with standard amount of ns. Barrier layer is varying over a range of 30 nm to 55 nm.

Figure 2. Spacer layer dependence of the electron density (ns) and mobility (µ) of the InSb QWFET for fixed 45 nm barrier layer.

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The room temperature conduction band (CB) and valance band (VB) profile of the proposed structure (Figure 1.) at Vg= 0 and -0.25V are calculated by QCSP as shown in Figure 3. Since the CB edge of the QW moves to higher energy at negative Vg, therefore ns in the QW decreases as shown in Figure 4. At Vg = -0.25V, the CB is lifted at enough higher energy and the QW reaches above the Fermi level (EF) which is confirmed complete depletion of the ns as shown in Figure 3. Moreover, the hole accumulation prevents as the VB doesn’t touch the EF. 0.4 Vg = 0V Vg = - 0.25V

Si δ-doping Energy (eV)

0.2 Ec

0.0

EF EV

-0.2 Al0.1In0.9Sb

-0.4 0

20

InSb

40

60

Al0.1In0.9Sb

80

100

Depth (nm)

Figure 3. Band diagram of the InSb QWFET is calculated by the quantum corrected selfconsistent Schrödinger-Poisson simulation. The depth is along the growth direction. The Fermi energy EF is set to 0 eV in this simulation, and Ec and Ev denote the conductionband minimum and the valence-band maximum, respectively. The Si δ-doped regions in AlInSb layers (please see bottom axis) are guided by vertical arrows. Gate voltage (Vg) dependent electron density (ns) and mobility (µ) of the InSb QWFET is shown in Figure 4. A very high electron mobility 4.42 m2V-1s-1 at Vg = 0V is achieved which is at least ~180 times greater than that of Si NMOS. The confined 2DEG in the InSb QW is completely depleted with a very small Vg = -0.25V (is called the pinch-off voltage, Vp). The slope of the ns-vg yields a giant gate controllability ratio of dns/dVg = ~ 5.2 × 1015 m-2V-1 (estimated in the range of -0.2V ≤Vg ≤ 0V) which indicates the good interface between the ALD-grown Al2O3 and the Al0.1In0.9Sb layer with a very low interface trap density, Dit.

6


4.5

T = 300K

4.0

0.9

3.5

ns (x1015 m -2)

1.2

µ (m 2/Vs)

1.5

3.0

0.6

2.5

0.3

2.0

Vp

0.0 -0.4

-0.3

-0.2 -0.1 Vg(V)

0.0

1.5

Figure 4. Electron density (ns) and mobility (µ) of the InSb QWFET as a function of gate bias (Vg) at 300 K. The dashed line points to the pinch-off voltage Vp. The Dit has been calculated using the equation Dit= -(dQit / (e × d(EF - EV))) where Qit is the net charge in oxide subtracted semiconductor charge (4). Energy dependent Dit and corresponding gate voltage (Vg) is shown in Figure 5. The value of Dit is found to be 7.8 × 1014 - 3.7 × 1016m-2eV- 1 at the interface between Al2O3 and Al0.1In0.9Sb top layer of the InSb QWFET. It indicates that the EF is smoothly tuned by the Vg due to a very low Dit.

-10

-2

4

V)

-5

-15

2

-20

Vg(× 10

Dit (x1016 m-2eV-1)

6

-25

0 0.22

0.24 0.26 EF-Ev(eV)

0.28

Figure 5. The interface trap density (Dit) and Vg (V) as a function of EF-EV. The capacitance-voltage (C-V) calculation has also been performed as shown in Figure 6. The curve shows the standard C-V characteristics. It also shows minimum capacitance value at Vg= -0.25V where the QWFET channel is in off state i.e., ns in the QW is completely depleted. This result is well compared with the obtained Vp from the Figure 3.

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Capacitance, C (× 10

-17 F)


8 6 4 2 0 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 Gate Voltage, Vg (V)

Figure 6. Capacitance-voltage (C-V) characteristics of the InSb QWFET.

Conclusion In conclusion, an optimized InSb QWFET with standard FET characteristics has been presented. Very high electron mobility has been obtained which represents high-speed transistor characteristics of the proposed InSb QWFET. The channel is in off-state at very low voltage (Vp= -0.25V) which is illustrated low power consumption of the proposed InSb QWFET. Therefore, the proposed InSb QWFET could be promising candidates in nanoelectronics field and future high- speed electronics.

Acknowledgments Authors are grateful to S. Birner for fruitful discussion.

References 1. ITRS. "International Technology Roadmap for Semiconductors," http://www.itrs.net/Links/2007ITRS/Home2007.htm. 2. T. Ashley et al. Proceedings 7th International Conference on Solid-State and Integrated Circuits Technology (SSICT), 2253 (2004). 3. S. Datta, Microelectronic Engineering, 84, 2133 (2007). 4. M. M. Uddin et al., Appl. Phys. Lett.,101, 233503 (2012). 5. M. M. Uddin et al., Appl. Phys. Lett.,103, 123502 (2013). 6. S. Birner, Ph. D. thesis, Technical University of Munich, Germany, (2011). 7. I-H Tan, G. L. Snider, D. L. Chang and E. L. Hu, J. Appl. Phys., 68, 4071 (1990).

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HfO2/Al2O3/InGaAs MOSCAP Structures and InGaAs Plasma Nitridation Elaborated in a 300mm Pilot Line M.Billauda,b, J.Duvernaya, H. Grampeixa, B. Pelissierb, M.Martinb, S.Davidb, C.Valléeb, Z.Chalupaa, H.Boutrya, T.Baronb, M.Casséa, T.Ernsta, M. Vineta, G. Reimbolda, O. Faynota a

Univ. Grenoble Alpes, F-38000 Grenoble, France CEA-LETI, MINATEC Campus, F-38054 Grenoble, France b Univ.Grenoble Alpes, LTM, F-38000 France CNRS, LTM, F-38000 Grenoble, France We report on electrical characteristics of HfO2/Al2O3 gate dielectric on InGaAs as a function of Al2O3 ALD cycles. We also investigate the effect of a NH3 treatment in a 300mm PEALD chamber equipped with a capacitive plasma. It is shown that 8 Al2O3 cycles are required to achieve a high level capacitance (1.75µF/cm²) and an interface trap density (Dit) around 6×1012cm-²eV-1. The NH3 plasma treatment through an Al2O3 layer is able to integrate nitrogen at the InGaAs interface and to form an oxynitride GaOxNy.without deterioration of the C-V characteristics. Introduction

InGaAs has been extensively studied as a good candidate for III-V high-mobility n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (1)(2). To this purpose, the achievement of a good high-k oxide/InGaAs interface quality is a key challenge to obtain high performance devices. Al2O3 deposited by ALD is well-known for its self-cleaning effect leading to a low defects density interface. However, its dielectric constant (~8.7) is rather low compared to other high-k materials like HfO2 (εr~20). Associating both materials in a bilayer oxide is then interesting to benefit from the good interface quality obtained with Al2O3 and the better electrostatic control achievable with HfO2. Furthermore, some recent work evidenced the reduction of the interface trap density (Dit) by using a plasma nitridation process (4). We evaluated the passivation properties of a bilayer Al2O3/HfO2 and a nitridation treatment on industrial equipment compatible with 300mm Si wafers. Two issues were studied. First, we investigate the number of Al2O3 ALD cycles needed to obtain a good interface, offering the best compromise between a low thickness and good electrical characteristics. Second, we evaluate the effect of various nitridation treatments on the Al2O3/InGaAs interface properties. MOSCAP Fabrication Metal oxide semiconductor capacitor structures were fabricated on a 25 nm thick n-type (residual doping) In0.53Ga0.47As epitaxial layer grown by metalorganic vapor phase epitaxy (MOCVD) on 100mm n-InP substrates. The growth was performed in a 300mm Applied Materials MOCVD reactor. After degreasing in acetone, isopropanol and deionized water, the samples were cleaned in a NH4OH solution (4%) for 1 min at room temperature and rinsed in deionized water. This simple cleaning recipe was chosen for its better process integration compatibility. Then, Al2O3 and HfO2 films were deposited in a Pulsar® XP ALD chamber from ASM at 300°C with trimethylaluminium (TMA), Hafnium tetrachloride (HfCl4) and H2O as precursors. The ALD cycle numbers for Al2O3 were 0, 3, 5, 8 or 10 and 32 for HfO2. A postdeposition annealing was carried out at 370°C for 30 min in N2 ambient. For the nitridation study, samples were treated with NH3 or N2 plasma for 120 s at 50W in a PEALD chamber after 10 cycles of Al2O3 deposition. One sample was treated with NH3 plasma directly on the InGaAs surface without the Al2O3 protection layer. PEALD is equipped with a capacitively coupled plasma generated by a RF power delivery system. After the plasma treatment, Al2O3 was again deposited to reach a 8 nm-thick layer for electrical characterization. The PEALD and ALD chambers are connected so there is no air break between the plasma and the second Al2O3

9


deposition. A Ni/Au (40/60 nm) gate electrode was deposited through a shadow mask by e-beam evaporation, completing the MOS structure. The X-ray photoelectron spectroscopy (XPS) measurements were performed using 100 eV pass energy in Parallel Angle Resolved mode (pARXPS) in a Thermo Fisher Theta 300 chamber. The emission angle used was 46° to the surface normal for In, N and Ga and 68° for As to accentuate the oxide component. Results and Discussion Al2O3/HfO2 Capacitors Figure 1 shows the transmission electron microscopy (TEM) cross-sections of the oxide/InGaAs interfaces without and with Al2O3 (10 cycles). Both samples show a good quality interface. The HfO2 layer grown directly on InGaAs is about 3 nm thick which is close to the expected thickness. The bright interface is due to image conditions.

HfO2 – 3 nm

InGaAs 5 nm

(a)

(b)

Figure 1: TEM cross-section images of HfO2 (32 cycles)/InGaAs (a) and HfO2 (32 cycles)/Al2O3 (10 cycles)/InGaAs (b) interfaces. The whole Al2O3/HfO2 bilayer is ~3.4 nm thick. It can be seen that Al2O3 is quite rough and represents almost half of the dielectric layer (~1.5 nm). The HfO2 layer is thinner on Al2O3 than on InGaAs, likely due to a growth delay when deposited on Al2O3. Figure 2 shows the C-V measurements of the various Al2O3 ALD cycles MOSCAP structures performed with frequencies varying from 10 kHz up to 1 MHz. The sample with no Al2O3 (a) present very distorted profiles, especially at 10 kHz, sign of a poor interface quality. Depositing three Al2O3 cycles (b) allows a limited improvement of the characteristics.

Figure 2: C-V characteristics measured from 10 to 1000 kHz of the samples with (a) no Al2O3, (b) 3, (c) 5, (d) 8 and (d) 10 ALD Al2O3 cycles.

10


The dispersion in accumulation of the 10 and 30 kHz curves is reduced but no clear accumulation plateau can be seen. From 5 to 10 cycles, samples (c-e), the situation is strongly improved with a clear accumulation regime. The capacitance levels at Vg=2V are 1.9, 1.75 and 1.25 µF/cm2 for the 5, 8 and 10 cycles samples respectively. The interface trap densities (Dit) were estimated using the classic conductance method (5) and were found equal to ~11, 6.1 and 5.46 ×1012 cm-2eV-1 for the 5, 8 and 10 cycles samples respectively. A clear improvement is obtained from 5 to 8 cycles while only a slight amelioration is obtained from 8 to 10 cycles. Finally, the best compromise between low Dit and high level capacitance appears to be with 8 Al2O3 cycles. Nitridation Treatment The in situ nitridation treatment was performed in a PEALD chamber equipped with a direct plasma system and linked to the ALD chamber for the dielectric deposition. We investigate the plasma parameters required to reach the effect induced by a remote plasma. The figure 3 shows the C-V characteristics measured from 2 to 1000 kHz of the samples (a) without nitridation treatment, (b) with N2 plasma treatment after 10 Al2O3 cycles, (c) with NH3 plasma treatment without Al2O3 protection and (d) NH3 plasma treatment after 10 Al2O3 cycles.

Figure 3: C-V characteristics measured from 2 to 1000 kHz of the samples (a) without nitridation treatment, (b) with N2 plasma treatment after 10 Al2O3 cycles, (c) with NH3 plasma treatment without Al2O3 protection and (d) with NH3 plasma treatment after 10 Al2O3 cycles. With the protective Al2O3 layer, it can be observed that the maximum capacitance in accumulation is decreased after the N2 plasma while it is not affected with the NH3 plasma treatment. Without the Al2O3 protection, the plasma induces a large frequency dispersion in accumulation due to defects generation, typically attributed to border traps. The best conditions are then obtained with NH3 plasma through an Al2O3 layer. The Dit value after nitridation is around 2×1012 eV-1cm-2 so the interface is not damaged by the direct plasma. To further investigate the effect of the nitridation on the traps distribution, low temperature measurement should be performed. The effect of the NH3 plasma was also studied by ARXPS as a function of the treatment duration. The figure 4 shows (a) N1s, (b) As3d, (c) Ga2p3/2 and (d) In3d5/2 spectra without plasma treatment and with NH3 treatment trough the Al2O3 layer during 30s, 60s and 120s. The N1s spectrum shows the increase of nitrogen with treatment time, until reaching 5 at.% after 120s.The figure 4(a) shows that 60s are required to clearly detect nitrogen. As seen on the figure 4(c), the Ga3+ component also increases with nitridation after 60s of nitridation. On the contrary, a spread

11


out peak corresponding to the As oxide is reduced as soon as the 30s duration without any change for longer treatment. Finally no influence of the nitridation can be seen on the In oxide peak. The figure 4(e) shows the atomic ratios as a function of the nitridation time. The N/Al ratio points out the introduction of nitrogen with plasma duration. The As oxide ratio decreases after 30s as the oxides are reduced by NH3. The plasma does not affect the In bonds. The only bond affected by the nitridation is Ga3+ which indicates the formation of an oxynitride GaOxNy. The NH3 plasma treatment is then able to introduce nitrogen at the InGaAs/Al2O3 interface, creating bonds with Ga without damaging the electrical properties.

(a)

(b)

(c)

(e)

(d)

Figure 4: XPS (a) N1s, (b) As3d, (c) Ga2p3/2 and (d) In3d5/2 spectra after different NH3 plasma treatment time through an Al2O3 layer. The emission angle is 46° to the surface normal for In, N and Ga and 68° for As to accentuate the oxide component. Atomic ratios are plotted as a function of nitridation time (e) for Ga (up triangle), In (down triangle), As (diamond) and N (square). Conclusion In conclusion, a Al2O3/HfO2 bilayer for high-k gate stack was optimized on a 300mm equipment to achieve a Dit around 6×1012cm-²eV-1 and high level capacitance (1.75 µF/cm²). It was shown that 8 Al2O3 ALD cycles are required to obtain a good interface between InGaAs and the Al2O3/HfO2 bilayer. A NH3 plasma treatment performed on a 300mm capacitive plasma tool integrates nitrogen at the InGaAs surface without deterioration of the C-V characteristics. This in situ nitridation treatment elaborated in a 300mm PEALD chamber offers opportunities to further decrease the Dit on industrial equipment.

12


Acknowledgment This work has been partially supported by the LabEx Minos ANR-10-LABX-55-01 and by the French Government program ”Investissements d’Avenir” managed by the National Research Agency (ANR) under the contract number ANR-10-IQPX-33. References 1. P. K. Hurley and É. O. Connor, IEEE, vol. 13, no. 4, pp. 429–443, 2013. 2. R. Suzuki and N. Taoka, Appl. Phys. Lett., vol. 100, no. 13, p. 132906, 2012. 3. C. L. Hinkle and E. M. Vogel, Curr. Opin. Solid State Mater. Sci., vol. 15, no. 5, pp. 188–207, Oct. 2011. 4. T. Hoshii and S. Lee, J. Appl. Phys., vol. 112, no. 7, p. 073702, 2012. 5. R. Engel-Herbert and Y. Hwang, Appl. Phys. Lett., vol. 97, no. 6, p. 062905, 2010.

13


Towards a Vertical and Damage Free Post-Etch InGaAs Fin Profile: Dry Etch Processing, Sidewall Damage Assessment and Mitigation Options U. Peralagua, X. Lia, O. Ignatovaa, Y. C. Fua, D. A. J. Millara, M. J. Steera, I. M. Poveyb, K. Hossainc, M. Jainc, T. G. Goldingc, R. Droopadd, P. K. Hurleyb, and I. G. Thaynea a

School of Engineering, University of Glasgow, Glasgow, G12 8LT, United Kingdom Tyndall National Institute, University College Cork, Lee Maltings, Prospect Row, Cork, Ireland c Amethyst Research Incorporated, 123 Case Circle, Ardmore, Oklahoma 73401, USA d Ingram School of Engineering, Texas State University, San Marcos, Texas 78666, USA

b

Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins.

Introduction For close to half a century, the success of the microelectronics industry has been driven by the continued dimensional scaling of the Si complementary-metal-oxide-semiconductor (CMOS) transistor, resulting in increased logic performance and device density at reduced manufacturing costs (1-3). However, conventional transistor scaling has encountered a serious impediment owing to the high power consumption of logic chips. The power problem is two-fold, the first being leakage currents due to short channel effects (SCE) which increases with further dimensional scaling (4). The other is the saturation of the supply voltage at around 1V. While a reduction in supply voltage would ease power consumption, this comes at the cost of switching speed (1-3). Novel device architectures and new channel materials, technologies referred to as being disruptive to mainstream CMOS (3), are therefore required for continued transistor scaling and supply voltage reduction to enable higher device densities, faster logic switching and energy efficiency. The first of these disruptive technologies has already been embraced at the 22nm technology node (4,5) with the planar metal-oxide-semiconductor field-effect-transistor (MOSFET) evolving to a FinFET, a three-dimensional device architecture which provides for improved electrostatic integrity (3,4). While FinFETs are likely to feature in the logic

15


roadmap for at least three generations, Si is only expected to feature for another two generations as the channel material. To counteract the performance loss of Si at the 7nm technology node, novel channel materials - a second disruptive technology - would be required. These new materials must be able to deliver higher performance than Si at the same operating voltage (3). III-V materials due to their high electron injection velocities appear highly promising as the n-channel solution for post-Si CMOS (1,3). To make this a reality, substantial undertaking has gone into finding solutions for the technological challenges facing III-V MOSFETs (1,6). InGaAs, in particular, has been the centre of extensive research effort with remarkable progress being made in the in the critical areas of gate stack (7,8), parasitic resistance (9) and III-V/Si heterointegration (10). Recent impressive transistor performances (11-13) clearly demonstrate the extent to which III-V nMOSFET technology has matured. Despite these advances, further improvements are still needed to make III-Vs a viable CMOS option. The addition of a third dimension to the device architecture further requires dry etch processing, a top-down approach, for the fabrication of III-V fins. Dry etching is a complex process, with its employment for pattern transfer being highly experimental and empirical. The choice of gas chemistry and the control of process parameters dictate the quality of the etch process in terms of selectivity, anisotropy, etch rate and uniformity (14-20). The utilization of dry etch processing, however, carries with it the inherent risk of damage to the semiconductor due to energetic ion bombardment and the presence of reactive ion species (18,19,21). Etch-induced damage can manifest in various forms such as lattice defects (traps, vacancies and interstitials), lattice disordering (amorphisation) and surface roughness due to ion bombardment (19,21,22), surface contamination resulting from polymer deposition (21), dopant passivation by atomic hydrogen (21-23) and changes in surface stoichiometry due to preferential etching or layer intermixing (23-25). These effects can degrade the optical and electrical properties of the semiconductor, of detriment to the final device performance. The development of dry etch processing for nanometre-scale fin definition in III-V transistors demands two key requirements to be met; realisation of vertical sidewalls and a high quality sidewall MOS interface. The improved electrostatic integrity of FinFETs featuring vertical sidewalls as opposed to tapered sidewalls aid in minimising SCE, thereby enhancing device performance (26). A smooth sidewall presenting with minimum etch damage enables a sidewall MOS interface of high quality to be obtained (27). However, satisfying both criteria is a challenging prospect. Highly anisotropic dry etching required for sidewall verticality is more damaging due to the physical nature of the process (21). Unlike Si, the induced damage cannot be cured by post etch annealing in III-Vs (1,19). In this work, we will first report on the dry etch processing systematically investigated for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. The electrical damage arising from the most promising etch processes are evaluated from MOS capacitor (MOSCAP) measurements. Transmission electron microscopy (TEM) and atomic force microscopy (AFM) techniques are also used to determine structural and morphological properties. We will then present results on the mitigation of etch-induced sidewall damage. By means of dry etch process optimization we demonstrate a reduction in etch damage without compromising on sidewall verticality. Some examples of nanowires realized using this optimized process will also be shown.

16


Two post-etch sidewall passivation schemes are further explored to alleviate damage. Details of the passivation schemes and the associated results are presented and discussed.

Dry Etch Processing for Fin Formation and the Associated Damage Fin Etching Hydrogen silsesquioxane (HSQ) was used as the etch mask for the transfer of fin patterns onto (100) oriented In0.53Ga0.47As. Resist linewidths in the nanometric range were patterned by electron beam lithography using a Vistec VB6 UHR-EWF on HSQ limited to a thickness of 80nm. A HSQ etch mask with a range of linewidths between 10nm and 100nm was obtained with this process as shown in Fig. 1. This etch mask is used for all fin etch investigations presented in this paper.

HSQ

100 nm

InGaAs

100 nm

Figure 1. SEM of a HSQ etch mask, with linewidths in the range of 10nm to 100nm, for fin pattern transfer. Chlorine-based plasmas (e.g. Cl2, BCl3, SiCl4) and alkane/hydrogen-based plasmas (e.g. CH4/H2) are the two main gas chemistries used for etching III-V materials (14-18). Depending on the target III-V material to be etched and the specific application, various combinations of gas mixtures are derived from these basic chemistries with the inclusion of additive gases (e.g. Ar, N2, O2) to improve some aspect of the etch process (19,20). The initial fin etch experiments were carried out using a reactive ion etching (RIE) process based around a silicon tetrachloride (SiCl4) gas chemistry. An Oxford Instruments PlasmaLab System 100 RIE tool was used for the investigation. Despite an expansive exploration of the parameter space including flow rate, power, chamber pressure, table temperatures and etch times, it proved impossible to find a process window that would yield high resolution In0.53Ga0.47As fins with vertical sidewalls and clean etch surfaces. A truncated version of the experiments undertaken is presented here. In this study, four samples were etched at a constant gas flow rate of 25sccm while power and the corresponding self-bias, pressure, temperature and etch time were varied. The RIE parameters used for each sample are listed in Table I. The SEM micrographs relating to the etched samples are shown in Fig. 2. It is evident that all four etched samples have a rough surface morphology likely due to the In-enrichment of the surface owing to the low volatility of InCl (18,19). The sidewalls are also observed to be deteriorated by the rough

17


morphology. This would significantly compromise the quality of the sidewall MOS interface. TABLE I. Summary of RIE etch conditions, based around a SiCl4 chemistry, investigated for fin etching. Sample Gas Flow Power Pressure Bias Temperature Duration (sccm) (W) (mTorr) (V) (°C) (s) RIE-A 25 50 8 182 37 240 RIE-B 25 150 8 375 39 120 RIE-C 25 150 4 400 39 120 RIE-D 25 150 4 388 100 120

(a)

(b)

(c)

(d)

Figure 2. SEM of fins etched in In0.53Ga0.47As using a SiCl4 gas chemistry, for the RIE process conditions of (a) RIE-A, (b) RIE-B, (c) RIE-C and (d) RIE-D listed in Table I.

In the next set of fin etching experiments, a variety of chlorine-based chemistries were examined using an inductively coupled plasma (ICP) etch process. These experiments were conducted in an Oxford Instruments PlasmaPro System 100 ICP180 RIE tool. Based on a larger experimental matrix, the process conditions of four In0.53Ga0.47As samples etched in Cl2/BCl3, Cl2/BCl3/Ar and Cl2/CH4/H2 chemistries are summarized in Table II. The SEM micrographs of samples subject to the different etch recipes are shown in Fig. 3. It is notable that all etched samples present with a smooth surface morphology, a drastic improvement from the RIE process using a SiCl4 chemistry. Despite the smooth surfaces, it proved challenging to obtain vertical fins with Cl2/BCl3 and Cl2/BCl3/Ar etch processes. Sample ICP-A etched in Cl2/BCl3 yielded a 56.8° sidewall-to substrate angle (Fig. 3(a)). For the same gas chemistry, a reduction in coil/platen power and pressure resulted in a lower sidewall angle of 49.8° for sample ICP-B (Fig. 3(b)). There is no significant improvement in the slope of the sidewall (55.7°) for sample ICP-C etched using Cl2/BCl3/Ar (Fig. 3(c)),

18


TABLE II. Summary of ICP etch conditions, for a variety of chlorine-based chemistries, investigated for fin etching. Sample Etch Flow Coil/Platen Pressure Bias Temperature Duration Chemistry (sccm) Power (mTorr) (V) (°C) (s) (W) ICP-A Cl2/BCl3 15/3 800/30 10 120 60 30 ICP-B Cl2/BCl3 15/3 400/15 2 62 60 120 ICP-C Cl2/BCl3/Ar 12/3/6 400/15 2 62 60 120 ICP-D Cl2/CH4/H2 6/10/15 500/75 2 182 60 30

despite the addition of Ar to the chemistry which should in essence provide for better anisotropic etching due to increased ion sputtering (28). The Cl2/CH4/H2 process, however, does show significantly more promise with the sidewall being within 3° of vertical in the top half of the fin while the bottom half presents with a sidewall angle of 73° (Fig. 3(d)). This improvement in verticality could be partly due to the enhanced sidewall passivation provided by H2 and CH4 in the chemistry (20,29). On the other hand, physical sputtering is likely enhanced by the high platen power of the process resulting in more anisotropic etching (18,21). The quality of etching was further analysed by AFM. Shown in Fig. 4 are the AFM scans of an unetched sample and samples blanket etched using the etch recipes

(a)

(b)

(c)

(d)

HSQ InGaAs

20nm

Figure 3. SEM of fins etched in In0.53Ga0.47As using a variety of chlorine-based chemistries, for the ICP process conditions of (a) ICP-A, (b) ICP-B, (c) ICP-C and (d) ICP-D listed in Table II. 19


detailed in Table II, with measured roughness indicated. For the Cl2/BCl3 processes, the surface roughness increased with longer etch times. Introducing Ar to the Cl2/BCl3 does not result in additional surface roughness. The Cl2/CH4/H2 process had comparable roughness to the Cl2/BCl3 process for a given etch time. The roughness of all etched samples are deemed to be within the range of device quality etching.

(a)

(b)

(d)

Ra = 0.284nm

(c)

Ra = 0.428nm

Ra = 0.516nm

(e)

Ra = 0.580nm

Ra = 0.417nm

Figure 4. 5x5μm AFM scans of (a) unetched (control) sample and samples blanket etched using the ICP etch conditions of (b) ICP-A, (c) ICP-B, (d) ICP-C and (e) ICP-D listed in Table II.

An etch process for the realisation of vertical In0.53Ga0.47As fins with a high aspect ratio was also explored using the Cl2/CH4/H2 chemistry. A large matrix of etch experiments was carried out with variations in RF platen power (0-250W), ICP coil power (100-2000W), chamber pressure (1-10mTorr), temperature (0-60°C) and gas flow rates. This led to the realisation of a highly vertical 10nm In0.53Ga0.47As fin with 16:1 aspect ratio as shown in Fig. 5(a), perhaps the highest aspect ratio, smallest critical dimension fins that been demonstrated to date in In0.53Ga0.47As. The details of this fin etch process are Cl2/CH4/H2 : 6/10/15sccm, coil/platen powers of 1000/75W, 2mTorr, 198V, 60°C, 45s. AFM was also used to analyse the etched surface as shown in Fig. 5(b). The measured roughness of 0.456nm is indicative of device quality etching.

20


9.7nm

(b)

(a)

Figure 5. (a) SEM of a vertical 10nm In0.53Ga0.47As fin with a high aspect ratio of 16:1 realised using a Cl2/CH4/H2 etch process and (b) 8x8μm and 2x2μm (inset) AFM scans of the etched In0.53Ga0.47As surface. Sidewall Damage Assessment A wide variety of a techniques such as x-ray photoelectron spectroscopy, secondary ion mass spectroscopy, Auger electron microscopy, photoluminescence, Hall measurements, Schottky diode measurements, conductivity measurements of quantum wires, etc. (14,16-19,21-25,30-33) have been used to yield structural, chemical and electrical information relating to etch-induced damage. Our concern here is the extent of electrical damage to the dielectric/sidewall interface. In MOS technology, the electrical properties at the dielectric/semiconductor interface are routinely studied from capacitancevoltage (C-V) characteristics derived from MOSCAPs (6-8). On the basis of this, the impact of the etch processes on the electrical properties of the sidewall MOS interface is assessed from MOSCAP measurements in this work. Here, the aim is to correlate the electrical damage to the ICP based fin etch processes detailed in Table II. As a first step, samples of (100) oriented In0.53Ga0.47As, 1μm thick, ndoped 2x1016 cm-3 grown on an n+ substrate by molecular beam epitaxy (MBE) are subjected to the etch processes. These samples are not patterned, they are simply blanket etched using the fin etch conditions. Although this does not fully mimic the processes that FinFET sidewalls will experience, it will give an initial indication of the likely impact of the etch conditions on the In0.53Ga0.47As surface, via the electrical characteristics of MOSCAPs which are subsequently formed on the etched surface using the process flow shown in Fig. 6. The samples are treated in 10% (NH4)2S for 20min at room temperature immediately prior to atomic layer deposition (ALD) of 8nm-thick (nominal) Al2O3 film.

Figure 6. Process flow for fabrication of MOSCAP on blanket etched InGaAs.

21


The gate electrode was defined via a shadow mask through which a Pt/Au contact was electron-beam (e-beam) evaporated. A backside contact was formed by blanket e-beam deposition of Ni/Ge/Au on the back of the samples. A MOSCAP was also fabricated on an unetched sample to serve as a control in the study. Shown in Fig. 7 are the room temperature multi-frequency (1kHz to 1MHz) C-V characteristics of the unetched (control) sample and samples subject to the ICP etch processes listed in Table II. The key electrical metrics derived from the C-V data of Fig. 7,

Figure 7. Multi-frequency, room temperature C-V characteristics of Au/Pt/Al2O3/nIn0.53Ga0.47As MOSCAPs with the InGaAs sample (a) unetched (control) and etched for the ICP conditions of (b) ICP-A , (c) ICP-B, (d) ICP-C and (e) ICP-D listed in Table II.

22


specifically the frequency dispersion in accumulation (ΔCacc), stretch-out of the C-V curve (dC/dV), frequency dispersion in depletion (ΔmV) and hysteresis at 1MHz are summarised in Table III. The definitions used for the extraction of these metrics can be found in Ref. 34. Percentages, displayed in the table, are used to compare and quantify the difference in metrics between an etched sample and a control sample. It is also worth pointing out that a decrease in dC/dV is taken to mean an increase in the stretch-out.

TABLE III. Summary of metrics derived from the C-V responses of an unetched (control) sample and samples etched under a variety of chlorine-based chemistries for the ICP conditions given in Table II. MOSCAP Sample ΔCacc dC/dV x 10-7 ΔmV Hysteresis (F/cm2.V) (%/dec) (mV) (mV) Control 2.17 9.15 100.7 126.0 ICP-A 2.28 (+5.1%) 8.38 (-8.4%) 105.2 (+4.5%) 117.4 (-6.8%) ICP-B 2.29 (+5.5%) 8.27 (-9.6%) 70.7 (-29.8%) 84.8 (-32.7%) ICP-C 2.33 (+7.4%) 8.27 (-9.6%) 139.2 (+38.2%) 105.8 (-16.0%) ICP-D 2.48 (+14.3%) 5.31 (-42.0%) 169.1 (+67.9%) 190.3 (+51.0%)

Samples ICP-A, ICP-B and ICP-C, etched in Cl2/BCl3 based chemistries, presented with a 5-7.5% increase in ΔCacc and a 8-10% increase in stretch-out. While ΔmV of samples ICP-A and ICP-C are increased from that of the control sample, ICP-B in fact shows a reduction. The hysteresis of all samples etched in a Cl2/BCl3 based process is smaller than that of the control sample. In contrast, the metrics of sample ICP-D subject to the Cl2/CH4/H2 etch process, which produced the best fin profile among all the etch recipes, are found to be significantly degraded. It is notable that amongst the etched samples, ICPD demonstrates the largest degradation across all metrics. In the depletion region, the C-V responses are comparable between the control sample and samples etched in Cl2/BCl3 chemistry, including Ar (Figs. 7(a)-(d)). It is observed that the C-V responses go through a peak in the gate bias range of 0V to -1.5V. Such a peak response is a characteristic signature of interface defects (7,8,35). While peak responses are also observed in the C-V curves of the sample etched in the Cl2/CH4/H2 chemistry, the peaks are noticeably broader and higher in magnitude (Fig. 7(e)) which suggests an increase in interface defect density (Dit) (35). The deterioration of the interface properties of the sample etched in Cl2/CH4/H2 is also noted from the significant peak on the 1MHz response. A similar feature is not present in the C-V response of the control sample or the other etched samples. Equivalent parallel conductance (Gp/ω) can be used to provide an indication of the relative differences in defect densities between the etched samples and the control sample since there is direct correlation between Gp/ω and Dit (35). In Fig. 8, plots of Gp/ω as a function of gate bias at a constant frequency of 1MHz and 100kHz are shown. The peak magnitudes of Gp/ω is increased by a factor of 1.5-2 for samples etched in Cl2/BCl3 based chemistries in comparison to the control sample. On the other hand, the conductance peak of the sample etched in Cl2/CH4/H2 is a factor of 6.5-8.5 greater than the control sample.

23


Figure 8. Gp/ω versus Vg of Au/Pt/Al2O3/n-In0.53Ga0.47As MOSCAPs, with the InGaAs sample unetched (control) and etched using the ICP processes listed in Table II, at a constant frequency of (a) 1MHz and (b) 100kHz.

Based on the aforementioned analysis it is clear the Cl2/CH4/H2 etch process induces substantial damage to the In0.53Ga0.47As surface, despite the fact the surface roughness obtained with this process is smaller than that of the Cl2/BCl3 based etch processes. It is possible that methane and hydrogen present in the chemistry could be causing polymers and/or carbon based contaminants to be deposited on the In0.53Ga0.47As surface, resulting in the quality of the interface to be degraded. To elucidate such effects, TEM analysis was undertaken. Shown in Fig. 9 are the cross-sectional TEM micrographs obtained from each of the etched samples and the control sample following high-k dielectric and metal gate deposition. These images confirm the thickness of the Al2O3, and correlate well with the roughness measurements on each sample. From the TEM images, it is clear there is a sharp transition from the In0.53Ga0.47As to the Al2O3 film with no obvious interlayer. Particularly, for the Cl2/CH4/H2, there is no evidence of polymer deposition or the presence of carbon on the In0.53Ga0.47As surface, to impact the electrical performance of the MOSCAPs. The damage, therefore, is likely arising from the physical nature of the Cl2/CH4/H2 etch process. The high anisotropy required for the realisation of near vertical fins with this etch process is primarily provided by ion sputtering. The enhanced ion bombardment, however, also induces more damage (18,21). The degree of damage is directly proportional to the ion energy and inversely proportional to the ion mass (18). Looking back at Table II, the platen power used with the Cl2/CH4/H2 etch process is noticeably higher compared to all the other etch processes. The etch-induced damage can therefore be minimised by lowering the platen power, which in turn reduces the ion energy.

24


10 nm

10 nm

Figure 9. Cross-sectional TEM of In0.53Ga0.47As samples subject to (a) no etching and blanket etched using the ICP conditions of (b) ICP-A, (c) ICP-B, (d) ICP-C and (e) ICP-D listed in Table II, prior to high-k and metal gate deposition.

Mitigation of Etch-induced Sidewall Damage Dry Etch Process Optimization As previously shown, the realisation of fins with near-90° sidewall verticality based on a Cl2/CH4/H2 etch process comes at the cost of significant etch-induced damage. It was highlighted that the high platen power of 75W used in the process is likely responsible for this. In an effort to minimise the damage an ICP etch process based around a Cl2/CH4/H2/O2 chemistry is explored. The addition of O2 to the etch chemistry allows for the platen power to be lowered, which should help with reducing the etch-induced damage without compromising the fin sidewall profile. Fins were etched in (100) oriented In0.53Ga0.47As(30nm)/In0.52Al0.48As samples using the HSQ etch mask shown in Fig. 1, to obtain fin heights in the range of 40-50nm. Two fin etch recipes were investigated, with the only difference being the platen temperature. The process details are Cl2/CH4/H2/O2 : 6/10/15/0.5sccm, coil/platen powers of 200/25W, 2mTorr, 113V, 5min. Shown in Fig. 10 are the SEM micrographs of fins etched using the aforementioned process conditions at temperatures of 60°C and 120°C. Highly vertical fin profiles are realised with both etch recipes. The fins etched at the higher

25


temperature though show a more vertical sidewall profile, which closely resembles that of the fins etched in the Cl2/CH4/H2 chemistry (Fig. 3(d)).

designed Wfin = 100nm

111 8nm

42 3nm 45 8nm

Figure 10. SEM of fins etched in In0.53Ga0.47As(30nm)/In0.52Al0.48As using a Cl2/CH4/H2/O2 chemistry at temperatures of (a) 60°C and (b) 120°C for the process conditions of Cl2/CH4/H2/O2 : 6/10/15/0.5sccm, coil/platen powers : 200/25W, 2mT, 113V, 5min.

To assess the damage associated with the Cl2/CH4/H2/O2 etch processes, MOSCAPs were fabricated on samples of (100) oriented In0.53Ga0.47As, 1μm thick, n-doped 4x1017 cm-3 using the process flow illustrated in Fig. 6. A MOSCAP fabricated on an unetched sample served as a control in the study. In Figs. 11(a)-(c) the room temperature multifrequency (1kHz to 1MHz) C-V characteristics of the control sample and samples etched at the temperatures of 60°C and 120°C, denoted as A and B, are displayed. Etch-induced damage is observed from the peak responses being broader and of higher magnitude in the etched samples. It is further noted the fin etch process performed at the lower temperature of 60°C gives rise to more damage as the peaks are observed to be broader and larger in magnitude compared to sample A. From the plot of Gp/ω versus Vg (Fig. 11(d)), conductance peaks of samples A and B are found to be 4.5x and 2.75x larger in relation to the control sample as opposed to the larger factor of 8.5 reported earlier for the Cl2/CH4/H2 chemistry (Fig. 8(b)). Table IV summarises the electrical metrics of the control and etched samples determined from their respective C-V characteristics. Frequency dispersion in accumulation and depletion along with stretch-out are observed to be less degraded for sample B. While both the etched samples demonstrate a reduction in hysteresis, a larger improvement is noted for sample B. These observations in conjunction with the aforementioned Gp/ω analysis suggest the higher temperature etch process renders less damage to the sidewall. Moreover, in contrast to the Cl2/CH4/H2 etch process there is a marked improvement in the metrics of samples subject to the Cl2/CH4/H2/O2 etch process

26


with respect to the control sample. This indicates the lower platen power arising from the addition of O2 to the Cl2/CH4/H2 chemistry results in a substantial reduction of etchinduced damage.

Figure 11. Multi-frequency, room temperature C-V characteristics of Au/Pt/Al2O3/nIn0.53Ga0.47As MOSCAPs with the InGaAs sample (a) unetched (control) and etched in Cl2/CH4/H2/O2 chemistry at the temperatures of (b) 60°C and (c) 120°C, and (d) the resulting Gp/ω versus Vg at a constant frequency of 100kHz.

TABLE IV. Summary of metrics derived from the C-V responses of an unetched (control) sample and samples A and B etched in a Cl2/CH4/H2/O2 chemistry at temperatures of 60°C and 120°C. Sample ΔCacc dC/dV x 10-7 ΔmV Hysteresis (F/cm2.V) (%/dec) (mV) (mV) Control 2.18 2.21 200.2 450 A 2.59 (+19.0%) 1.95 (-11.8%) 208.3 (+4.0%) 383 (-14.9%) B 2.44 (+10.6%) 2.14 (-3.2%) 206.7 (+3.2%) 351 (-22.0%)

27


The Cl2/CH4/H2/O2 etch chemistry was also explored for nanowire etching on samples of (100) oriented In0.53Ga0.47As, using HSQ as an etch mask. As shown in Fig. 12 HSQ, limited to a thickness of 40nm, was patterned using high-resolution electron beam lithography to produce an array of nano pillars, each with a diameter of 33nm.

33.4 nm

37.8 nm

Figure 12. SEM of a HSQ etch mask comprised of nano pillars, each with a diameter of 33nm, for nanowire pattern transfer.

The etch processes investigated for nanowire realisation are detailed in Table V. Except for the flow rate of H2 and O2, all other process parameters were kept identical between the etch recipes. From Fig. 13, it is observed that highly vertical nanowires are realised with all three etch conditions, with sidewall-to-substrate angles in the range of 80-82° and nanowire heights in the range of 45-50nm. A trend of improving sidewall verticality with increases in H2 and O2 flow rate is noted, albeit the improvements are only marginal.

TABLE V. Summary of ICP etch conditions, based around a Cl2/CH4/H2/O2 chemistry, investigated for nanowire etching. Sample Etch Flow rate Coil/Platen Pressure Bias Temperature Duration Chemistry (sccm) Power (mTorr) (V) (C) (min) (W) NW-A Cl2/CH4/H2/O2 6/10/15/0.5 250/50 2 113 120 2.5 NW-B Cl2/CH4/H2/O2 6/10/22/0.5 250/50 2 113 120 2.5 NW-C Cl2/CH4/H2/O2 6/10/22/1 250/50 2 113 120 2.5

25 nm

22 nm

18 nm 10 nm

20 nm

20 nm 45 nm

50 nm

32 nm

42 nm

(a)

45 nm

35 nm

(b)

(c)

Figure 13. SEM of nanowires etched in In0.53Ga0.47As using a Cl2/CH4/H2/O2 chemistry, for the ICP process conditions of (a) NW-A, (b) NW-B and (c) NW-C listed in Table V. 28


Post-etch Sidewall Passivation Schemes Hydrogenation. The preparation of clean, well-ordered, stoichiometric and atomically smooth surfaces are of importance in semiconductor processing. Atomic hydrogen has been demonstrated to be an effective surface preparation technique due to its ability to remove carbon-containing contaminants and native oxides (36-38). The lower temperatures required of atomic hydrogen cleaning alleviates the problems of group V desorption and surface roughening typically associated with high temperature thermal cleaning of substrates prior to epitaxial growth (36-38). A notable obstacle in III-V MOS technology is the presence of a large density of defects at the dielectric/semiconductor interface. This can result in the Fermi level to be pinned, thereby limiting logic performance. Native oxides present on III-V surfaces have been proposed as one cause of Fermi level pinning (39). The reduction and/or removal of these oxides by means of atomic hydrogen cleaning have been shown to unpin the Fermi level (40,41) and reduce interface defect density (42). Another key feature of atomic hydrogen is its ability to passivate native defects within the semiconductor (23,30,43). This attribute has also been exploited in GaN and GaAs to recover damage arising from dry etch processing through the passivation of etch-induced defects (44,45). This motivates an investigation of atomic hydrogen as a postetch treatment for the alleviation of etch-induced damage in In0.53Ga0.47As. Atomic hydrogen is often introduced into semiconductors through controlled methods such as direct implantation (43), exposure to hydrogen plasmas (36,38,42-44) and from thermal cracking of molecular hydrogen (36-38,40,41). The first two methods, though, carry the risk of physical and electronic damage to the near surface regions of the semiconductor due to the presence of energetic ions (36,43). Here, we employ a photonassisted hydrogenation process (46) developed by Amethyst Research Incorporated to investigate mitigation of damage induced by the fin etch process. This process involves the irradiation of samples with an ultraviolet (UV) light source in a hydrogen ambient. The extent of hydrogen incorporation is controlled and optimized by temperature, exposure time and pressure. To investigate the effects of hydrogenation, four MOSCAPs were fabricated on samples of (100) oriented In0.53Ga0.47As, 1μm thick, n-doped 4x1017 cm-3 using the process flow of Fig. 6. For a controlled study, one sample did not see any etch process prior to MOSCAP fabrication. The remaining three samples were subject to a fin etch process. The process details are Cl2/CH4/H2 : 6/10/15sccm, coil/platen powers of 500/75W, 2mTorr, 182V, 60°C, 60s. A MOSCAP was directly fabricated on one of the etched samples. The remaining two samples underwent hydrogenation at different stages of the process flow for MOSCAP fabrication shown in Fig. 6. One sample underwent hydrogenation after the etch (post-etch hydrogenation) while the other was hydrogenated after Al2O3 deposition (post ALD high-k hydrogenation). Hydrogenation was carried out at a temperature of 325°C for 30min, with the pressure set at 1mbar. Multi-frequency (100Hz to 1MHz) C-V characteristics acquired at room temperature from the four samples are shown in Fig. 14. The electrical metrics extracted from the C-V curves of each sample are also detailed in Table VI. Although the post-etch hydrogenated sample shows an improvement across all metrics from the etched sample, the obtained

29


enhancement is marginal. In contrast, a significant reduction in stretch-out and depletion dispersion is obtained for the post high-k hydrogenated sample. These results suggest that hydrogenation done post high-k is more effective in alleviating etch-induced damage. The large conductance peak associated with the etched samples at a constant frequency of 1MHz shown in Fig. 15 is reduced substantially in magnitude after post-etch hydrogenation. A larger reduction in the peak value is obtained by hydrogenating the etched sample post high-k as opposed to post-etch.

Figure 14. Multi-frequency, room temperature C-V characteristics of Au/Pt/Al2O3/nIn0.53Ga0.47As MOSCAPs with the InGaAs sample (a) unetched (control), (b) only etched, etched and subjected to the treatments of (c) post-etch hydrogenation and (d) post ALD high-k hydrogenation.

TABLE VI. Summary of metrics derived from the C-V responses of samples investigated in the hydrogenation experiment. Sample ΔCacc dC/dV x 10-7 ΔmV (%/dec) (F/cm2.V) (mV) Control 2.84 2.49 322 Fin etch 3.82 (+34.5%) 1.63 (-34.5%) 605 (+87.9%) Post-etch hydrogenation 3.72 (+31.0%) 1.81 (-27.3%) 595 (+84.8%) Post ALD high-k hydrogenation 3.68 (+29.6%) 2.31 (-7.2%) 334 (+3.7%)

30


Figure 15. Gp/ω versus Vg of Au/Pt/Al2O3/n-In0.53Ga0.47As MOSCAPs investigated in the hydrogenation experiment, at a constant frequency of 1MHz.

Digital Etch In standard wet etching, semiconductors are immersed into a solution comprising an oxidising agent and an etching agent. Etching proceeds through the simultaneous process of surface oxidation and oxide etching. As a result, the depth of material etched is dictated by the length of time the semiconductor is exposed to the etchant. Digital etch, on the other hand, separates the two processes of oxidation and oxide removal. Etching is then achieved through the sequential application of the oxidant and etchant to ensure the chemical reactions associated with each process are independent of each other. (47, 48) Due to the self-limiting nature of the oxidation process, the depth of material removed is only dependent on the number of etch cycles and not on the etch time (48). The main benefit of digital etch compared to standard wet etching is the fact that etching can be performed in a controlled manner. This property of digital etch can be exploited in two ways, the first being for the removal of dry etch damaged semiconductor layers (27). Digital etch also offers a route for ultimate fin/nanowire scaling (49). In this work, we assess the impact of a digital etch clean for the mitigation of damage induced by fin etch processing. This is investigated on a sample of (100) oriented In0.53Ga0.47As, 1μm thick, n-doped 4x1017 cm-3 blanket etched using the 120°C, Cl2/CH4/H2/O2 etch process. The details of the etch are Cl2/CH4/H2/O2 : 6/10/15/0.5sccm, coil/platen powers of 200/25W, 2mTorr, 113V, 120°C, 5min. The etched surface is then subjected to three cycles of the digital etch clean. Each cycle is a two-step process comprising a self-limiting O2 plasma oxidation in a RIE tool followed by a 10s rinse in diluted H2SO4 for oxide removal. Plasma oxidation was carried out under the conditions of 50sccm, 50mTorr, 52V, 22°C, 3s. We estimate that one cleaning cycle etches 1nm of the In0.53Ga0.47As material. The process flow of Fig. 6 is adopted for the realisation of MOSCAPs on this sample. The C-V data acquired on the cleaned sample is shown in Fig. 16(a). To elucidate the impact of the digital etch clean, a comparison in C-V characteristics is drawn between the cleaned sample, a control sample (Fig. 11(a)) and a sample blanket etched under the same fin etch conditions (Fig. 11(c)). From this comparison, it is evident that the C-V characteristics of the cleaned sample is significantly improved, with all electrical metrics

31


showing improvements, over the etched sample. Additionally, the conductance peak of the etched sample is reduced by a factor of three in value after being subjected to the digital etch clean. This highlights the benefit of the digital etch clean for mitigating damage induced by fin etch processes. It is also noteworthy that the C-V data between the control sample and the cleaned sample is comparable. This is an important observation as it suggests the etch-induced damage has been completely recovered via the digital etch clean, resulting in the restoration of the Al2O3/In0.53Ga0.47As interface to its original state prior to etching. This also implies the damage induced by 120°C, Cl2/CH4/H2/O2 etch process only extends to the near surface region, up to a depth of about 3nm from the surface based on the etch rate (1nm/cycle) and the number of cleaning cycles used.

Figure 16. (a) Multi-frequency, room temperature C-V characteristics of a Au/Pt/Al2O3/nIn0.53Ga0.47As MOSCAP with the InGaAs sample subjected to the 120°C, Cl2/CH4/H2/O2 based fin etch process followed by the digital etch clean and (b) Gp/ω versus Vg of Au/Pt/Al2O3/n-In0.53Ga0.47As MOSCAPs with the InGaAs sample subjected to no etch (control), the fin etch process only and the fin etch process followed by the digital etch clean, at a constant frequency of 100kHz.

Mitigation of fin etch damage by means of the digital etch clean was also examined on etched (110) oriented In0.53Ga0.47As. For this investigation, 200nm thick n-type (110) In0.53Ga0.47As layer doped at 4x1017 cm-3 was grown by molecular beam epitaxy (MBE) on (110) n+-InP substrate. Of the three samples fabricated from (110) In0.53Ga0.47As for electrical evaluation, one served as control (unetched) while the others were blanket etched. The digital etch clean was then carried out on one of the etched samples. The conditions of the fin etch process, used for blanket etching, and the digital etch clean are identical to that used in the earlier study reporting on the effectiveness of digital etch clean on etched (100) In0.53Ga0.47As. The fabrication of MOSCAPs was based on the process flow of Fig. 6. The room temperature CV data of the unetched sample (control), the sample subjected to the fin etch process (etched), and for the sample subjected to the fin etch process followed by the digital etch clean (cleaned) are compared in Fig. 17. It is clear that etched sample has significantly degraded C-V response, evidenced by a stretch-out in the characteristics and the fact that the 100kHz and 1MHz capacitance does not reach the theoretical minimum capacitance of 2.5x10-7 F/cm2. In contrast, the cleaned sample appears to have regained many of the characteristics of the control sample, and indeed the

32


peak in depletion around -1V, evident in both the 10kHz and 100kHz data, is suppressed in the cleaned sample. This implies recovery of damage in etched (110) In0.53Ga0.47As, similar to the finding noted for post-etch cleaned (100) In0.53Ga0.47As.

Figure 17. Multi-frequency, room temperature C-V characteristics of a Au/Pt/Al2O3/n(110) In0.53Ga0.47As MOSCAP with the InGaAs sample (a) unetched (control), (b) subject to the fin etch process (etched) and (c) subjected to the fin etch process followed by the digital etch clean (cleaned).

Conclusion The introduction of III-V channels into CMOS, currently aimed at the 7nm technology node, would require top-down patterning of III-V fins. The realisation of fins with a vertical profile and a high quality sidewall MOS interface, however, is a challenging prospect. Reason being, highly anisotropic etching required of vertical fin profiles is more damaging to the sidewall. To tackle the conflict between anisotropy and damage, inherent to dry etch processing, we adopted a two-tier approach to realise vertical In0.53Ga0.47As fins with minimum etch damage. In the first tier, we focussed on developing dry etch processes capable of producing high resolution fins with vertical sidewalls and clean etch surfaces. Fin etching was investigated for a variety of chlorine-based chemistries using either a RIE or an ICP process. A fin profile within 3˚ of vertical was obtained with the ICP process based around a Cl2/CH4/H2 chemistry. Vertical 10nm fins with 16:1 aspect ratio, perhaps the highest aspect ratio, smallest critical dimension fins to date in In0.53Ga0.47As, was also achieved. The process, however, severely degraded the electrical characteristics of MOSCAPs formed on a (100) In0.53Ga0.47As surface subjected to the etch which indicated substantial etch-induced damage. The aim in the second tier was then to mitigate the damage. The modification of the Cl2/CH4/H2 chemistry to include O2 resulted in the substantial reduction of etch-induced damage, due to the lowering of the platen power, without compromising on the fin profile. Two post-etch sidewall passivation schemes were also examined for damage mitigation. The first was a photon-assisted hydrogenation process, applied post-etch or post high-k. The electrical performance of MOSCAPs formed on a (100) In0.53Ga0.47As surface subjected to the Cl2/CH4/H2 etch indicated a larger reduction in etch damage for hydrogenation done post high-k. In the second approach, a digital etch clean, comprising of a multi-cycle O2 plasma oxidation then oxide removal in H2SO4, was investigated as a post-etch treatment. The electrical characteristics of MOSCAPs formed on (100) In0.53Ga0.47As and (110) In0.53Ga0.47As surfaces subjected to the Cl2/CH4/H2/O2 etch revealed a complete recovery of etch damage. The demonstration of high resolution (10 nm), near-vertical (~87°) In0.53Ga0.47As fins and the ability to realise

33


damage-free sidewalls are of significance for the realisation of high-performance III-V FinFETs.

Acknowledgments The authors acknowledge support from the Semiconductor Research Corporation (Task ID 2188.002) and technical support from the James Watt Nanofabrication Centre (JWNC) University of Glasgow.

References 1. 2. 3. 4. 5.

J. A. del Alamo, Nature, 479, 317 (2011). H. Iwai, Microelectron. Eng., 86, 1520 (2009). H. Riel, L. -E. Wernersson, M. Hong, J. A. del Alamo, MRS Bulletin, 39, 668 (2014). I. Ferain, C. A. Colinge, J. -P. Colinge, Nature, 479, 310 (2011). C. C. Wu, D. W. Lin, A. Keshavarzi, C. H. Huang, C. T. Chan, C. H. Tseng, C. L. Chen, C. Y. Hsieh, K. Y. Wong, M. L. Cheng, T. H. Li, Y. C. Lin, L. Y. Yang, C. P. Lin, C. S. Hou, H. C. Lin, J. L. Yang, K. F. Yu, M. J. Chen, T. H. Hsieh, Y. C. Peng, C. H. Chou, C. J. Lee, C. W. Huang, C. Y. Lu, F. K. Yang, H. K. Chen, L. W. Weng, P. C. Yen, S. H. Wang, S. W. Chang, S.W. Chuang, T. C. Gan, T. L. Wu, T. Y. Lee, W. S. Huang, Y. J. Huang, Y. W. Tseng, C. M. Wu, E. Ou-Yang, K. Y. Hsu, L. T. Lin, S. B. Wang, T. M. Kwok, C. C. Su, C. H. Tsai, M. J. Huang, H. M. Lin, A. S. Chang, S. H. Liao, L. S. Chen, J. H. Chen, P. S. Lim, X. F. Yu, S. Y. Ku, Y. B. Lee, P. C. Hsieh, P. W. Wang, Y. H. Chiu, S. S. Lin, H. J. Tao, M. Cao, Y. J. Mii, IEEE IEDM Tech. Dig., 2711 (2010). 6. S. Oktyabrsky, M. Yakimov, V. Tokranov, R. Kambhampati, H,. Bakhru, S. Koveshnikov, W. Tsai, F. Zhu, J. Lee, International Journal of High Speed Electronics and Systems, 18, 761 (2008). 7. P. K. Hurley, E. O'Connor, V. Djara, S. Monaghan, I. M. Povey, R. D. Long, B. Sheehan, J. Lin, P. C. McIntyre, B. Brennan, R. M. Wallace, M. E. Pemble, K. Cherkaoui, IEEE Trans. Device Mater. Rel., 13, 429 (2013). 8. V. Chobpattana, E. Mikheev, J. Y. Zhang, T. E. Mates, S. Stemmer, J. Appl. Phys., 116, 124104 (2014). 9. R. Oxland, S. W. Chang, X. Li, S. W. Wang, G. Radhakrishnan, W. Priyantha, M. J. H. van Dal, C. H. Hsieh, G. Vellianitis, G. Doornbos, K. Bhuwalka, B. Duriez, I. Thayne, R. Droopad, M. Passlack, C. H. Diaz, Y. C. Sun, IEEE Elec. Dev. Lett., 33, 501 (2012). 10. R. J. W. Hill, C. Park, J. Barnett, J. Price, J. Huang, N. Goel, W. -Y. Loh, J. Oh, C. E. Smith, P. Kirsch, P. Majhi, R. Jammy, IEEE IEDM Tech. Dig., 621 (2010). 11. S. Lee, V. Chobpattana, C. -Y. Huang, B. J. Thibeault, W. Mitchell, S. Stemmer, A. C. Gossard, M. J. W. Rodwell, VLSI Technology Tech. Dig., 54 (2014). 12. C. Y. Huang, S. Lee, V. Chobpattana, S. Stemmer, A. C. Gossard, B. Thibeault, W. Mitchell, M. Rodwell, IEEE IEDM Tech. Dig., 586 (2014). 13. S. W. Chang, X. Li, R. Oxland, S. W. Wang, C. H. Wang, R. Contreras-Guerrero, K. K. Bhuwalka, G. Doornbos, T. Vasen, M. C. Holland, G. Vellianitis, M. J. H. van Dal, B. Duriez, M. Edirisooriya, J. S. Rojas-Ramirez, P. Ramvall, S. Thoms,

34


U. Peralagu, C. H. Hsieh, Y. S. Chang, K. M. Yin, E. Lind, L. -E. Wernersson, R. Droopad, I. Thayne, M. Passlack, C. H. Diaz, IEEE IEDM Tech. Dig., 417 (2013). 14. S. J. Pearton, U. K. Chakrabarti, W. S. Hobson and A. P. Perley, J. Electrochern. Soc., 137, 3188 (1990). 15. J. W. Lee, E. S. Lambers, C. R. Abernathy, S. J. Pearton, R. J. Shul, F. Ren, W. S. Hobson, C. Constantine, Mater. Sci. Semicond. Process., 1, 65 (1998). 16. T Maeda, J. W. Lee, R. J. Shul, J. Han, J. Hong, E. S. Lambers, S. J. Pearton, C. R. Abernathy, W. S. Hobson, Appl. Surf. Sci., 143, 174 (1999). 17. T Maeda, J. W. Lee, R. J. Shul, J. Han, J. Hong, E. S. Lambers, S. J. Pearton, C. R. Abernathy, W. S. Hobson, Appl. Surf. Sci., 143, 183 (1999). 18. S. J. Pearton, F. Ren, T. R. Fullowan, A. Katz, W. S. Hobson, U. K. Chakrabarti, C. R. Abernathy, Mater. Chem. Phys, 32, 215 (1992). 19. C. D. Wilkinson and M. Rahman, Philos Trans A Math Phys Eng Sci., 362, 125 (2004). 20. F. Karouta, J. Phys. D: Appl. Phys., 47, 233501 (2014). 21. S. J. Fonash, J. Electrochem. Soc., 137, 3885 (1990). 22. G. Franz, J. Vac. Sci. Technol. A, 19, 762 (2001). 23. T. R. Hayes, W. C. Dautremont-Smith, H. J. Luftman, J. W. Lee, Appl. Phys. Lett., 55, 56 (1989). 24. R. van Roijen, M. B. M. Kemp, C. W. Bulle-Lieuwma, L. J. van Ijzerdoorn, T. L. Thijssen, J. Appl. Phys., 70, 3983 (1991). 25. S. J. Pearton, U. K. Chakrabarti, F. A. Baiochi, Appl. Phys. Lett., 55,1633 (1989). 26. A. Dixit, T. B. Hook, J. B. Johnson, E. J. Nowak and K. V. Murali, in Physics of Semiconductor Devices, V. K. Jain and A. Verma, Editors, p. 5, Springer-Verlag, New York (2014). 27. X. Zhao, J. A. del Alamo, IEEE Elec. Dev. Lett., 35, 521 (2014). 28. M. Volatier, D. Duchesne, R. Morandotti, R. Arès, V. Aimez, Nanotechnology, 21, 134014 (2010). 29. L. Gatilova, S. Bouchoule, S. Guilet, P. Chabert, J. Vac. Sci. Technol. A, 27, 262 (2009). 30. L. Goubert, R. L. Van Meirhaeghe, P. Clauws, F. Cardon, P. Van Daele, J. Appl. Phys., 82, 1696 (1997). 31. H. C. Neitzert, R. Fang, M. Kunst, N. Layadi, J. Vac. Sci. Technol. B, 18, 2803 (2000). 32. T. R. Hayes, U. K. Chakrabarti, F. A. Baiocchi, A. B. Emerson, H. S. Luftman, W. C. Dautremon-Smith, J. Appl. Phys., 68, 785 (1990). 33. A. R. Long, M. Rahman, I. K. MacDonald, M. Kinsler, S. P. Beaumont, C. D. W. Wilkinson, C. R. Stanley, Semicond. Sci. Technol., 8, 39 (1993). 34. U. Peralagu, I. M. Povey, P. Carolan, J. Lin, R. Contreras-Guerrero, R. Droopad, P. K. Hurley and I. G. Thayne, Appl. Phys. Lett., 105, 162907 (2014). 35. E. O’Connor, B. Brennan, V. Djara, K. Cherkaoui, S. Monaghan, S. B. Newcomb, R. Contreras, M. Milojevic, G. Hughes, M. E. Pemble, R. M. Wallace, and P. K. Hurley, J. of Appl. Phys., 109, 024101 (2011). 36. G. R. Bell, N. S. Kaijaks, R. J. Dixon, C. F. McConville, Surf. Sci., 401, 125 (1998). 37. A. Khatiri, J. M. Ripalda, T. J. Krzyzewski, G. R. Bell, C. F. McConville, T. S. Jones, Surf. Sci., 548, L1 (2004). 38. T. Kikawa, I. Ochiai, S. Takatani, Surf. Sci., 316, 238 (1994). 39. H. Hasegawa, M. Akazawa, A. Domanowska, B. Adamowicz, Appl. Surf. Sci., 256, 5698 (2010).

35


40. W. Melitz, J. Shen, T. Kent, A. C. Kummel and R. Droopad, J. Appl. Phys., 110, 013713 (2011). 41. J. Szuber, Vacuum, 55, 209 (2000). 42. A. D. Carter, W. J. Mitchell, B. J. Thibeault, J. J. M. Law, M. J. W. Rodwell, Appl. Phys. Express, 4, 091102 (2011). 43. S. J. Pearton, J. W. Corbett, T. S. Shi, Appl. Phys. A, 43, 153 (1987). 44. B. -S. Yoo, S. -J. Park, K. -H. Park, J. Vac. Sci. Technol. A, 13, 931 (1995). 45. S. Chen, Y. Lu, R. Kometani, K. Ishikawa, H. Kondo, Y. Tokuda, M. Sekine, M. Hori, AIP Advances, 2, 022149 (2012). 46. H1. T. D. Golding and R. P. Hellmer 2008, Photon-assisted hydrogenation process, US Patent 0268658. 47. X. Cao, I. Thayne, Microelectron. Eng., 67, 333 (2003). 48. G. C. DeSalvo, C. A. Bozada, J. L. Ebel, D. C. Look, J. P. Barrette, C. L. A. Cerny, R. W. Dettmer, J. K. Gillespie, C. K. Havasy, T. J. Jenkins, K. Nakano, C. I. Pettiford, T. K. Quach, J. S. Sewell, G. David Via, J. Electrochem. Soc., 143, 3652 (1996). 49. J. Lin, X. Zhao, D. A. Antoniadis, J. A. del Alamo, IEEE Elec. Dev. Lett., 35, 440 (2014).

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MOS Interface Control Technologies for Advanced III-V/ Ge Devices S. Takagi1, 2, C. Y. Chang1, 2, M. Yokoyama1, 2, K. Nishi1, 2, R. Zhang1, 3, M. Ke1, 2, J. H. Han1, 2, and M. Takenaka1, 2 1

The University of Tokyo, 2JST-CREST 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 JAPAN 3 Zhejiang University, Hangzhou 310027, CHINA

Critical issues for high quality Ge/III-V MOS gate stacks have been reviewed and discussed. For Ge gate stacks, a plasma post oxidation method can realize high quality ultrathin EOT Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stacks. We have evaluated limiting factors of electron and hole mobility in Ge MOSFETs. The Ge MOS channel mobility in a high Ns region is significantly degraded by surface roughness scattering as well as trapping of free carriers into interface states inside the Ge bands. It is shown that reduction in surface roughness through low temperature PPO and reduction in Dit inside the bands due to atomic Deuterium annealing can improve the effective mobility in the high Ns region. For InGaAs gate stacks, ALD La2O3 gate stacks yield lower Dit than the Al2O3 ones. For GaSb gate stacks, high ALD temperature or annealing temperature increases Dit at Al2O3/GaSb interfaces. InAs passivation for GaSb surfaces can effectively significantly improve the MOS interface properties and the thermal stability of the Al2O3/GaSb interfaces. Introduction High-mobility-channel CMOS on the Si platform is strongly expected to be one of the promising devices for high-performance and low-power logic large-scale integrated circuits (LSIs) in the future technology nodes [1, 2]. There are a variety of CMOS structures using III-V/Ge channels, which have been regarded as a promising CMOS structure under sub 10 nm regime [3, 4]. The typical CMOS structures are schematically shown in Fig. 1. CMOS structures for near-future applications could be integrated with strained-Si devices, although the performance improvement might be limited. Ge CMOS is plausible in terms of the simplicity of the process/material integration, because the CMOS is composed of a single material. III-V CMOS is another possible CMOS structure, there are still many choices of materials for CMOS, because III-V materials suitable for n-MOSFETs and p-MOSFETs are different in most cases. One of the ultimate CMOS structures is the co-integration of an As-based III-V n-MOSFET and a Ge p-MOSFET [1]. As a result, realistic CMOS structures using high mobility materials are still strongly dependent on future progress in the device/process/integration technologies of III-V/Ge MOS devices, the amount of the performance enhancement and the yield/cost.

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nMOS

pMOS

s-Si

Ge

nMOS

pMOS

nMOS

Ge

Ge BOX Si substrate

BOX Si substrate

nMOS

III-V

Ge BOX Si substrate

Ge CMOS

s-Si/Ge CMOS pMOS

nMOS

III-V

s-Si BOX Si substrate

pMOS

III-V/Ge hybrid CMOS pMOS

III-V

III-V BOX Si substrate

III-V/s-Si CMOS

III-V CMOS (eg. InAs/GaSb)

Performance Process Simplicity

Fig. 1. Several CMOS structures using Ge/III-V channels. Here, one of the most critical issues for these Ge/III-V MOSFETs is formation of superior gate stacks satisfying the requirements of thin equivalent oxide thickness (EOT) and excellent MOS interface quality enabling high channel mobility and low S factor. As a result, MOS interface control engineering is of paramount importance. In this presentation, we focus on viable III-V/Ge gate stack technologies by using ALD high-k films for realizing these requirements. The impact of the MOS interface properties on the MOS channel mobility is emphasized here. Mobility limiting factors originating in Ge MOS gate stacks ALD Al2O3 on Ge

O2

Al2O3

ALD Al2O3

O2

GeOx

Ge

HfO2

O2

Ge ECR oxygen plasma

Al2O3

O2

O2

HfO2

O2

Al2O3 GeOx

Ge

Ge

ALD GeOx formation Al2O3/HfO2 by post plasma Ruion Zhang, Ge et al. 4A-1 oxidation

Fig. 2. Proposed Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stack formation process by oxidation using ECR oxygen plasma through a thin Al2O3 and a thin HfO2/Al2O3 layer, respectively, by ALD. It has been revealed that Ge oxide interfacial layers (IL) can provide superior MOS interfaces with lower interface state density (Dit) among the various Ge MOS interfaces. Recently, we have presented ultrathin EOT Al2O3/GeOx/Ge [5-8] and HfO2/Al2O3/GeOx/Ge gate stacks [9, 10], fabricated by a plasma post oxidation (PPO)

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method, which is shown in Fig. 2. The advantages of the ECR plasma post oxidation through ALD Al2O3 are (1) precise control of ultrathin GeOx IL formation by employing thin Al2O3 as an oxygen barrier and diffusion control layer (2) low temperature process of plasma process to protect the superior properties of GeOx/Ge interface (3) protection of MOS interfaces during processing by Al2O3 films. 2

15

W/L=30/5 um 1

10

0

10

-1

10

-2

10

-3

Vd=+/-50 mV Vd=+/-500 mV

(100)/ EOT=0.76 nm

10

Step=-0.2 or 0.2 V

5

0

-1.0

Vg-Vth=0~-1 or 1 V

10

5

(b)

(a)

-4

10 -1.5

-Id (µA/µm)

10

15

EOT=0.76 nm

W/L=30 µm/5 µm

Id (µA/µm)

-Id (µA/µm)

10

-0.5

0.0

0.5

1.0

1.5

-1.0

-0.5

0.0

0.5

1.0

0

Vd (V)

Vg (V)

Fig. 3. (a) Id-Vg and (b) Id-Vd characteristics of the Ge p- and n-MOSFETs with HfO2 (2.2 nm)/Al2O3 (0.2 nm)/GeOx (0.35 nm)/Ge gate stacks.

(a)

Direct extraction of roughness from TEM

Interface position (nm)

It has been found that the reduction in Dit by one order of the magnitude is obtained after the plasma post oxidation compared with that of the direct Al2O3/Ge MOS interface. The minimum Dit lower than 1011 cm-2eV-1 has been observed without any hydrogen annealing. Fig. 3 (a) and (b) show the Id-Vg and Id-Vd characteristics, respectively, of nand p-MOSFETs with the HfO2 (2.2 nm)/Al2O3 (0.2 nm)/GeOx (0.35 nm)/Ge gate stacks under an EOT of 0.76 nm. The normal operation of n- and p-MOS devices can be confirmed from the Id-Vg characteristics. These Ge p- and n-MOSFETs show the on/off current ratios of ~104 and ~103, and the S factors of 85 and 80 mV/dec, respectively. The peak mobility of HfO2/Al2O3/GeOx/Ge p- and n-MOSFETs with EOT of 0.76 nm amounted to 546 cm2/Vs and 690 cm2/Vs, respectively. 1

(b)

0 o

300 C oxidation

-1 1 0 -1 0

RT oxidation 20

40

60

80

100

Position (nm)

Fig. 4. Cross-sectional TEM images of the GeOx/Ge interfaces formed by 300 °C and RT post plasma oxidation and the spatial variation of the interface roughness extracted from TEM data.

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On the other hand, one of the critical problems in Ge MOSFETs is the effective mobility reduction in high Ns region, which is important in current drive under the realistic device operation. However, the physical origin has not been clarified yet in spite of the importance. Since this mobility in high Ns region has almost no temperature dependence, possible origins are (1) increased surface roughness scattering rate (2) inversion-carrier trapping into defects and decrease in apparent mobility. Thus, we have experimentally studied the mobility from the above two viewpoints.

2

Hall mobility (cm/Vs)

We have found that plasma oxidation temperature strongly affects the GeOx/Ge interface roughness [11, 12]. Fig. 4 shows the cross-sectional TEM images of the Al2O3/GeOx/Ge structures fabricated at the PPO temperature of 300 oC and room temperature (RT). In order to make the interface roughness more visible, the variation of the MOS interface position has been extracted directly from the TEM images [13]. Larger roughness is observed at the GeOx/Ge interface grown at 300 oC, while a reduction of the GeOx/Ge interface roughness is observed for the one grown at RT. It has been found that the effective mobility of Ge p- and n-MOSFETs with RT oxidation is higher by 20% and 25%, respectively, at Ns of 1013 cm-2, than those with 300 oC oxidation, which is attributable to the reduction of GeOx/Ge interface roughness by RT PPO. Normal interface Flat interface

Open: Total µ Hall Line: Calculated µsr

10 3

10

Electron

Hole

∆ real/∆ TEM =3.0

2

4

5

6

N s (10

12

7

-2

cm )

Fig. 5. Theoretically calculated roughness mobility and total Hall mobility measured at 120 K of Ge p- and n-MOSFETs with 300 °C and RT oxidized GeOx (1.2 nm)/Ge interfaces. In order to quantitatively further examine the impact of reduced interface roughness by lowering the PPO temperature, the theoretical roughness-limited-mobility (µsr) of Ge MOSFETs are calculated using the real GeOx/Ge interface roughness extracted from the TEM data, shown in Fig. 4, and compared with the experimental Hall mobility at 120 K, which is free from any carrier trapping effect discussed later [11, 12]. Fig. 5 shows the Theoretically calculated roughness mobility and total Hall mobility measured at 120 K of Ge p- and n-MOSFETs with GeOx (1.2 nm)/Ge interfaces oxidized at 300 °C (normal interface) and RT (flat interface). Here, µsr was directly determined by the extracted roughness without any parameter fitting [13]. It is found in Fig. 5 that the total Hall mobility for both hole and electron are in a good agreement with the calculated µsr in high Ns region and that the enhancement of mobility with decreasing the oxidation temperature is also well represented. This result is one of the direct evidences that the reduction of GeOx/Ge interface roughness leads to the increase in the mobility in high Ns region.

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Another mobility degradation mechanism can be a trapping effect of carriers into interface states inside the conduction and valence bands. Actually, we have revealed through Hall mobility measurements that the effective mobility of InGaAs n-MOSFETs is degraded by a large amount of Dit inside the conduction bands [14-16]. Split C-V, used for evaluating the effective mobility, includes both free carrier and trapped carrier responses, indicating that the estimated Ns values becomes higher than the real on and, thus, the estimated effective mobility is lower than the real one. On the other hand, Hall measurements allow us to directly evaluate free carrier concentration. Thus, we have also employed this technique to Ge n- and p-MOSFETs to estimate the influence of Dit inside the Ge bands on the effective mobility [11, 17].

Electron mobility (cm /Vs)

1200

400 300 200 0.5 nm GeO x

0.25 nm GeOx

100

Open: Hall Line: Split C-V

(100) Ge pFETs

0

0.1

1 12

Open: Hall Line: Split C-V

(100) Ge nFETs

2

1.2 nm GeOx

2

Hole mobility (cm /Vs)

500

900 1.2 nm GeOx 600

300

0 0.1

10 -2

0.25 nm GeOx 0.5 nm GeOx 1

10 12

Ns (10 cm )

-2

Ns (10 cm )

Fig. 6. Comparison mobility evaluated by split C-V and Hall measurement for (a) holes and (b) electrons in (100) Ge p- and n-MOSFETs with different GeOx/Ge MOS interface thicknesses. Fig. 6(a) and (b) shows the comparison between the Hall and the effective mobility for (100) Ge p- and n-MOSFETs, respectively, on an assumption of a fixed Hall factor, γ = 1. Here, the MOS interface qualities were intentionally varied by changing the GeOx/Ge interface thicknesses [8, 18]. It is found that much higher Hall mobility than the effective mobility is observed for both holes and electrons. The larger effective mobility degradation with reducing GeOx thickness is found for Ge n-MOSFETs, which can be explained by the fact that the Dit increase near the conduction band is much higher in the thinner GeOx IL than that near the valence band [8, 18, 19]. Recently, we have found that this trapping effect of carriers into interface states inside the conduction and valence bands can be mitigated by atomic deuterium (D) annealing [22]. Fig. 7 shows the effective and Hall electron mobility in Al2O3/GeOx/Ge nMOSFETs after with N2 and atomic D post deposition annealing (PDA) at 400 °C in comparison with the effective mobility reported previously [19-21]. It is found that the electron effective mobility in the high-Ns region is enhanced after the atomic D PDA. Since we have confirmed that the Hall mobility does not change with and without PDA, this increase in the mobility after PDA is attributed to the reduction in Dit inside the conduction band, which decreases the amount of trapping of inversion-layer electrons resulting in the increase of Ns at a given Vg value.

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, ,

(a)

N2 Aotmic D

2

Electron mobility (cm /Vs)

1000

800

Hall

600

Split CV ~25% C. H. Lee VLSI, 2013.

400

C. H. Lee IEDM, 2010.

D. Kuzum TED, 2011.

1

2

4

6

Ns (1012 cm-2)

8 10

Fig. 7. Mobility of Ge n-MOSFETs with N2 and atomic deuterium PDA in comparison with previous reports [19-21]. Reduction in slow states in Ge MOS gate stacks One of the remaining critical issues for the Ge MOS gate stacks is the existence of a large amount of slow traps and the resulting poor BTI (bias-temperature instability) characteristics [7, 23, 24], attributable to any defects in gate insulators including Ge oxides, Al2O3 and/or HfO2. Thus, the reduction in the amount of slow traps responsible for BTI and the significant improvement in the reliability lifetime are quite important. It has been recently reported that Y-doped GeOx interface layers fabricated by sputtering can provide the MOS interface properties with small hysteresis and low Dit [25-27]. These results suggest that appropriate doping of Y atoms into Ge oxides and Al2O3 near Ge interfaces can reduce the slow trap density and improve the BTI reliability. Thus, we are currently studying the impact of ALD Y2O3 and AlYO3 gate stacks on the slow trap density [28].

2 1.5 1

2.5 -2

-2

C (μf/cm )

2.5

3

1.5nmAl2O3/GeOx/p-Ge CET 1.87nm C (μf/cm )

3

1kHz

0.5

1.5nmAlYO3/GeOx/p-Ge CET 1.65nm

2 1.5 1

1kHz

0.5

(b) 1MHz 0 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Vg (V)

(a) 1MHz 0 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Vg (V)

Fig. 8. C-V curves of 1.5-nm-thick (a) Al2O3/Ge and (b) AlYO3/Ge MOS capacitors with plasma post oxidation. The measurement frequency was varied from 1 k, 10 k, 100 k to 1 M Hz.

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After the pre-cleaning of (100) Ge wafers, Y2O3 and AlYO3 layer were deposited at 300 °C by ALD using (CpMe)3Y and/or Al(CH2)3 as the precursors and water. For ALD AlYO3, Al(CH2)3 and (CpMe)3Y were supplied alternatively, defined here as one cycle, to form the AlYO3 layer. Subsequently, PPO using ECR plasma of Ar and O2 with 650 W. PDA for 30 min at 400 oC in N2 ambient was performed, followed by Au gate electrode and Al back contact formation by thermal evaporation. We have found that Y2O3/Ge gate stacks with and without PPO have large hysteresis and thus have no improvement in the slow trap density. Thus, we focus on the properties of AlYO3/Ge gate stacks. Fig. 8 shows the C-V curves of 1.5-nm-thick (a) Al2O3/Ge and (b) AlYO3/Ge MOS capacitors with plasma post oxidation. The measurement frequency was varied from 1 k, 10 k, 100 k to 1 MHz. We have observed that the AlYO3/Ge interface after PPO, which can be represented as AlYO3/GeOx/Ge, can provide Dit lower than AlYO3/Ge without PPO and comparable to the conventional Al2O3/Ge with PPO (Al2O3/GeOx/Ge). It is found in Fig. 8 that AlYO3/GeOx/Ge has smaller hysteresis and a resulting smaller amount of slow traps than Al2O3/GeOx/Ge. In order to estimate the density of slow traps, the effective slow trap areal density, ∆Nfix, was evaluated from the amount of hysteresis measured with changing the minimum voltage with holding constant the maximum voltage as a function of the effective electric field across gate insulators (Eox=(Vg-VFB)/ CET (capacitance equivalent thickness)), according to [24]. Fig. 9 shows ∆Nfix of the 1.5-nm-thick AlYO3/GeOx/Ge and 1.5-nm-thick Al2O3/GeOx/Ge interfaces for both n- and p-Ge substrates. It is found that ∆Nfix of the AlYO3/GeOx/p-Ge interface is significantly lower than that of Al2O3/GeOx/p-Ge interface, while the reduction in ∆Nfix for n-Ge is small for the AlYO3/GeOx/Ge interface. These results mean that AlYO3-based gate stack can effectively improve the amount of slow traps in the valence band against the conventional Al2O3/GeOx/Ge interfaces. It is also confirmed that the slow trap density near the conduction band edge is much higher than that that near the valence band edge. Thus, further refinements and improvements on the Ge gate stacks are still strongly needed to reduce the slow trap density near the conduction band edge.

13

10

n-Ge 1.5nmAl O

1.5nmAlYO3

3

-2

△N (cm )

2

12

fix

10

p-Ge 1.5nmAl2O3

1.5nmAlYO3

1.5nmAl2O3 or AlYO3/GeOx/Ge PPO 6 7 8 10 10 10 Eox(V/cm)

11

10

Fig. 9. Relationship between Eox and ∆Nfix of 1.5-nm-thick AlYO3/GeOx/p-Ge and n-Ge MOS capacitors and 1.5-nm-thick Al2O3/GeOx/n-Ge and p-Ge MOS capacitors.

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Improvement of interface defects at InGaAs MOS interface Since the MOS interface control and EOT scaling are more difficult issues for III-V semiconductors than for Ge, III-V gate stack technologies for high-quality MOS interfaces are quite important. Actually, one of the most important recent findings in the III-V MOS interface control has been the effectiveness of ALD Al2O3 films as a gate insulator for III-V materials such as GaAs and InGaAs in terms of the reduction in Dit [29-33]. As thin EOT InGaAs gate stacks, the insertion of 0.2-nm-thick ultrathin Al2O3 inter-layer for HfO2/InGaAs interfaces has been found to effectively improve the interface properties [34]. As a result, HfO2(2nm)/Al2O3(0.2nm)/InGaAs MOS gate stacks with CET of 1.08 nm and gate leakage current of 2.4×10-2 A/cm2 have been realized. However, the minimum Dit values at InGaAs MOS interfaces with Al2O3 IL are typically still around lower half of 1012 cm-2eV-1 order. A recent study has revealed that La2O3/InGaAs MOS interfaces can provide a lower Dit than Al2O3/InGaAs [35], which can provide a new MOS interface engineering scheme. Thus, we are also studying the MOS interface properties and control of ALD La2O3/InGaAs [36]. 12

0.5

TiN/W/La2O3/InGaAs (CET~1.8nm) [35]

-2

-1

La2O3 5.2nm La2O3 2.9nm (CET 1.8nm) La2O3 8.2nm Au/La2O3/InGaAs PMA 300oC

11

10

(a)

0

Au/La2O3/InGaAs 0.4 PMA 300oC

Hysteresis at VFB (V)

Dit (cm eV )

10

0.05 0.1 Energy from midgap (eV)

0.15

0.3 0.2 0.1 0 0

(b)

2 4 6 8 10 La2O3 Thickness (nm)

Fig. 10. (a) Energy distributions of Dit of 8.2-, 5.2- and 2.9-nm-thick La2O3/InGaAs MOS capacitors evaluated by conductance method. (b) hysteresis at VFB as a function of La2O3 thickness.

(0.4 nm) Al2O3: 3.5 nm

1 kHz 10 kHz 100 kHz 1 MHz

10

13

La2O3 physical thickness (nm) 0 1 2 3 Al2O3 (3.5nm)/InGaAs

Dit (cm-2eV-1)

C

(µF/cm2)

Au/Al2O3/La2O3/InGaAs La2O3 = 10 cycles

10

12

10

11

0 0.5 1 1.5 2 (b) (a) -2 -1.5 -1 -0.5 (b) Vg (V)

Al2O3 (3.5nm)/La2O3/InGaAs La2O3 = 5 ~ 40cy La2O3 (2.9nm)/InGaAs E - Ei = 0.1 eV 0

10 20 30 40 La2O3 cycle number

50

Fig. 11. (a) C-V curves of Al2O3 (3.5 nm)/La2O3 (0.4 nm (10 cycles))/InGaAs gate stacks. (b) La2O3 ALD cycle number dependence of Dit of Al2O3 (3.5 nm)/La2O3/InGaAs at the surface energy of 0.1 eV from midgap (E - Ei).

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We fabricated MOS capacitors on Si-doped n-In0.53Ga0.37As (ND ~ 5×1015 cm-3) grown on (001) InP. (NH4)Sx pretreatment was performed. La2O3 films were deposited by ALD. The precursors for La2O3 were La(iPrCp)3 and H2O, and the deposition temperature was 150 oC. The ALD mode deposition occurred with a rate of 0.1 nm/cycle and incubation of around 7 cycles. Au and Al were deposited by thermal evaporation as gate metal and the back contact, respectively. Post metallization annealing (PMA) in N2 at 300 oC for 1 min was performed for all MOS capacitors. Fig. 10(a) shows the energy distributions of Dit as a parameter of the La2O3 thickness. It is found that quite low Dit of ~ 3×1011 cm-2·eV-1, which is lower than that in the TiN/W/La2O3/InGaAs gate stacks reported in [35], can be obtained, almost independent of the La2O3 thickness, even less than 3 nm. However, the hysteresis of the C-V curves becomes larger with an increase in the La2O3 thickness, shown in Fig. 10(b), meaning that a high density of slow traps is included in La2O3. As a result, further optimization of La2O3-based gate stacks is needed to satisfy the requirements of thin CET, low gate current, small hysteresis and low Dit. In order to study the possibility of improving these electrical parameters, interface properties of Al2O3/La2O3/InGaAs MOS capacitors were examined with changing the La2O3 ALD cycle numbers. Fig. 11(a) shows the C-V curves of Al2O3 (3.5 nm)/La2O3 (0.4 nm (10 cycles))/InGaAs gate stacks. It is found that the hysteresis is reduced with reducing the thickness of La2O3. Fig. 11(b) shows Dit of Al2O3 (3.5 nm)/La2O3/InGaAs at the surface energy of 0.1 eV from midgap as a parameter of the La2O3 ALD cycle number, changing from 0, 5, 10, 15 to 40 cycles. Since the present deposition condition has incubation of around 7 cycles, the 5 cycle ALD means a sort of surface passivation. The 10, 15 and 40 cycle ALD produces 0.4-, 0.6- and 2.9-nm-thick La2O3, respectively. Also, 0 cycle La2O3 ALD means the Al2O3 (3.5 nm)/InGaAs gate stack. It is found that Al2O3 ALD strongly affects the MOS interface properties and increases Dit even for 2.9nm-thick La2O3 IL, suggesting any reaction of TMA and the La2O3 films. However, the Dit value of of Al2O3 (3.5 nm)/La2O3 (0.4 nm)/InGaAs is still lower than that of Al2O3/InGaAs. As a result, the combination of Al2O3 and La2O3 with an appropriate thickness can improve Dit with maintain a similar level of slow trap density, indicating that La2O3 IL can work as a promising high k IL for InGaAs gate stacks. Improvement of interface defects at GaSb MOS interface To realize III-V CMOS, the realization of high-performance III-V p-MOSFETs is a key, in contrast to the Ge CMOS. Thus, much attention has been paid to GaSb-based pMOSFETs, because of their higher hole mobility. As a result, there have recently been many reports on GaSb [37-44], InGaSb [40, 45-47] and InSb [48, 49] p-MOSFETs. Some of them have exhibited fairly good hole effective mobility. However, there are still many technological issues such as the high density of interface defects and poor thermal stability of MOS interfaces. Thus, the establishment of MOS gate stack technologies of GaSb and related III-V materials is indispensable in III-V CMOS. It has been reported for GaSb gate stacks that Al2O3/GaSb MOS interfaces have much higher Dit than Al2O3/InGaAs MOS interfaces, suggesting that the effect of the TMA cleaning effect can be limited. We have found that the ALD deposition temperature has a strong impact on the GaSb MOS Interface properties [50]. Fig. 12 shows the Al2O3/GaSb MOS interface properties with changing the ALD Al2O3 deposition temperature from 150, 200, 250 to 300 oC. It is found that the increase in the ALD temperature makes it difficult

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to obtain the larger capacitance modulation in the C-V curves. The similar dependence has also been obtained for annealing temperature, suggesting that the process temperature itself can degrade the Al2O3/GaSb MOS interface properties. As a result, ALD temperature of as low as 150 oC is needed for better MOS interfaces. However, even at this low ALD temperature, the C-V curves look insufficient, indicating there are still many interface states existing at the interfaces.

TALD = 150 ºC 1

o

ALD 150 C

200 ºC

250 ºC

300 ºC

o

o

ALD 250 C

ALD 200 C

o

ALD 300 C

2

C (μ μ F/cm )

0.8 0.6 1 kHz 10 kHz 0.4 100 kHz 1 MHz 0.2 dAl2O3 ~ 5 nm Vacc -> Vinv Vinv -> Vacc 0 -1 -0.5 0 0.5 V (V) G

1 kHz 10 kHz 100 kHz 1 MHz T ~ 150 K d ~ 5 nm Al2O3



d

d

Al2O3

~ 5 nm

Vacc -> Vinv Vinv -> Vacc 1-1 -0.5 0 0.5 V (V)

1 -1 -0.5 0 0.5 V (V)

1 -1 -0.5

G

G

Al2O3

~ 5 nm

Vacc -> Vinv Vinv -> Vacc

Vacc -> Vinv Vinv -> Vacc

0 0.5 V (V)

1

G

Fig. 12. ALD temperature dependence on the Al2O3/GaSb MOS interface properties. The frequency dispersion of the C-V curves of Al2O3/GaSb MOSCAPs with ALD Al2O3 deposited at 150, 200, 250 and 300 oC measured at room temperature. The red, blue, green, and black curves correspond to the measurements with the frequency of 1 kHz, 10 kHz, 100 kHz, and 1MHz, respectively. The solid and broken curves correspond to the measurements by sweeping the voltage from Vacc to Vinv and from Vinv to Vacc, respectively.

InAs 0 nm

InAs 0.5 nm

InAs 1.5 nm

InAs 3 nm

1

2

C (μ μ F/cm )

0.8 0.6 1 kHz 10 kHz kHz 0.4 100 1 MHz w/o InAs 0.2 Vacc -> Vinv Vinv -> Vacc 0 -2 -1 0 1 V (V)

1 kHz 10 kHz 100 kHz 1 MHz InAs 0.5 nm Vacc -> Vinv Vinv -> Vacc 0 1 2 -2 -1 V (V)

1 kHz 10 kHz 100 kHz 1 MHz InAs 1.5 nm Vacc -> Vinv Vinv -> Vacc 2 -2 -1 0 1 V (V)

1 kHz 10 kHz 100 kHz 1 MHz InAs 3 nm Vacc -> Vinv Vinv -> Vacc 0 1 2 -2 -1 V (V)

2

Fig. 13. Multi-frequency C-V curves of Al2O3/InAs/p-GaSb MOS capacitors with the InAs thickness of 0, 0.5, 1.5, and 3 nm, measured with f of 1 kHz, 10 kHz, 100 kHz, and 1 MHz at room temperature. The red, blue, green, and black colored curves are corresponding to the C-V curves measured with f of 1 kHz, 10 kHz, 100 kHz, and 1 MHz, respectively. The solid and broken curves correspond to the measurements by sweeping the voltage from Vacc to Vinv and from Vinv to Vacc, respectively. It has recently been reported that the GaSb MOS structures passivated with InAs layers can realize the good C-V curves in n-type GaSb MOS capacitors (MOSCAPs) even by an

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ex-situ Al2O3 ALD process [51]. This result suggests that the InAs capping layers can suppress the GaSb surface oxidation between the surface pre-cleaning and the ALD process, which is expected to provide better MOS interface properties at Al2O3/GaSb MOS capacitors. Thus, we have systematically studied the effects of the InAs capping layers on the Al2O3/p-GaSb MOS interface properties with changing the InAs thickness. The unintentionally-doped InAs layers with the thickness of 0.5, 1.0, 1.5, 2.0, 2.5, 3, and 5 nm were grown on p-type (100) GaSb wafers with carrier concentration (NA) of ~1×1017 cm-3 by MOCVD after thermal cleaning of GaSb surfaces at 570 ºC under trimethyl antimony gas flow. After that, 5-nm-thick ALD Al2O3 layers were deposited on the InAs/GaSb wafers at 150 ºC, after the pre-cleaning using an (NH4)2Sx solution. Fig. 13 shows the InAs thickness dependence of the room-temperature C-V curves of the Al2O3/InAs/p-GaSb MOSCAPs with the InAs thickness of 0, 0.5, 1.5 and 3 nm. The C-V curves are found to improve with an increase in the InAs thickness up to 1.5 nm, demonstrating the effectiveness of the InAs passivation on the MOS interface properties. On the other hand, the strong capacitance response in the inversion region is observed in the C-V curves with the InAs thickness of 3 nm, which are similar to those of MOS capacitors on n-type semiconductors. Since InAs/GaSb has the broken gap heterostructure, electrons can be supplied to the InAs conduction band form the GaSb valence band under positive gate bias. In addition, the inversion capacitance of the InAs/p-GaSb MOS capacitors becomes higher than the accumulation capacitance, because of the thickness of InAs. As a result, the C-V curves with thick InAs look similar to the ones on n-type substrates. 15

10

Al2O3/InAs/p-GaSb o T = 150 C

14

10

it

-2

-1

D (cm eV )

ALD

13

10

w/o InAs InAs 0.5 nm Terman method InAs 1.0 nm T = 100 K InAs 1.5 nm E ~ -0.4 eV InAs 2.0 nm V 12 10 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 E - E (eV) i

Fig. 14. Energy distributions of Dit of Al2O3/InAs/p-GaSb MOS capacitors with the InAs thickness of 0, 0.5, 1.0, 1.5, and 2.0 nm, estimated by the Terman method using the 1 MHz C-V curves measured at 100 K. The black, orange, green, red, and blue curves are corresponding to the MOS interfaces with 0-, 0.5-, 1.0-, 1.5- and 2.0 nm-thick InAs, respectively. In order to quantitatively examine the MOS interface quality, the energy distributions of Dit were evaluated from the 1 MHz C-V curves of the Al2O3/InAs/p-GaSb MOS capacitors measured at 100 K by using the Terman method. Fig. 14 shows the relationship between Dit and the surface energy from the midgap energy as a parameter of

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the InAs thickness of 0, 0.5, 1.0, 1.5, and 2.0 nm. The GaSb MOS capacitors without any InAs layers exhibit the strong pinning behaviors around 0.3 eV lower the midgap, because of the large Dit values of ~1013 - 1014 cm-2eV-1 or higher. On the other hand, the Al2O3/1.5-nm-thick InAs/p-GaSb MOS capacitors shows the lowest minimum Dit value of ~6.6×1012 cm-2eV-1 at -0.24 eV, which is reduced by ~50% from that of ~1.4×1013 cm2 eV-1 at E-Ei of -0.33 eV in the Al2O3/p-GaSb MOSCAPs. As a result, we can conclude that the 1.5-nm-thick InAs layer can yield the best interface properties among the present Al2O3/InAs/p-GaSb MOS capacitors. Conclusions In this paper, several critical issues for realizing superior Ge/III-V MOS gate stack properties have been reviewed and discussed. For Ge gate stacks, we present the properties of the thin EOT Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stacks, fabricated by the PPO method. We have evaluated limiting factors of electron and hole mobility in Ge n- and p-MOSFETs. It has been found in a high Ns region that the Ge MOS channel mobility is significantly degraded by surface roughness scattering as well as trapping of free electrons and holes into interface states inside the conduction and valence bands. The mobility in the high Ns region can be improved by reduction in surface roughness through low temperature PPO. Also, atomic Deuterium annealing can reduce Dit inside the bands, resulting in higher effective mobility. For InGaAs gate stacks, ALD La2O3 gate stacks have been found to yield lower Dit than the Al2O3 ones, indicating that La2O3 can be a promising high k material for InGaAs gate stacks. For GaSb gate stacks, Al2O3/GaSb MOS interfaces have much higher Dit than Al2O3/InGaAs MOS interfaces. ALD temperature or annealing temperature higher than 200 ºC is observed to increase Dit at Al2O3/GaSb interfaces. It has been shown that InAs passivation for GaSb surfaces can effectively improve the Al2O3/GaSb MOS interface properties and the thermal stability. The 1.5-nm-thick InAs has been found to be the optimum thickness in terms of Dit. Acknowledgments This work was partly supported by a Grant-in-Aid for Scientific Research (No. 23246058) from MEXT, the Development Program for Innovative Energy Efficiency Technology from NEDO and JST-CREST. The authors would like to thank Drs. M. Hata, T. Osada, O. Ichikawa, and H. Yamada in Sumitomo Chemical Corporation and Drs. H. Yokoyama and T. Akeyoshi in NTT for their collaborations. References 1. S. Takagi, T. Tezuka, T. Irisawa, S. Nakaharai, T. Numata, K. Usuda, N. Sugiyama, M. Shichijo, R. Nakane and, S. Sugahara, Solid-State Electron., 51, 526 (2007). 2. S. Takagi, T. Irisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka, and N. Sugiyama, IEEE Trans. Electron Devices, 55, 21, (2008). 3. S. Takagi, R. Zhang, S.-H. Kim, N. Taoka, M. Yokoyama, J.-K. Suh, R. Suzuki, Y.

48


Asakura, C. Zota and M. Takenaka, Tech. Dig. IEEE Int. Electron Device Meeting, 505 (2012). 4. S. Takagi, R. Zhang, J. Suh, S.-H. Kim, M. Yokoyama, K. Nishi and M. Takenaka, Jpn. J. Appl. Phys., 54, 06FA01 (2015). 5. R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka, and S. Takagi, Appl. Phys. Lett., 98, 112902 (2011). 6. R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka, and S. Takagi, IEEE Symp. on VLSI Technol., 56 (2011). 7. R. Zhang, N. Taoka, P. Huang, M. Takenaka, and S. Takagi, Tech. Dig. IEEE Int. Electron Device Meeting, 642 (2011). 8. R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka, and S. Takagi, IEEE Trans. Electron Devices, 59, 335 (2012). 9. R. Zhang, P. C. Huang, N. Taoka, M. Takenaka, and S. Takagi, IEEE Symp. on VLSI Technol., 161 (2012). 10. R. Zhang, P.-C. Huang, J.-C. Lin, N. Taoka, M. Takenaka, and S. Takagi, IEEE Trans. Electron Devices, 60, 927 (2013). 11. R. Zhang, P.-C. Huang, J.-C. Lin, M. Takenaka, and S. Takagi, Tech. Dig. IEEE Int. Electron Device Meeting, 371 (2012). 12. R. Zhang, J.-C. Lin, X. Yu, M. Takenaka, and S. Takagi, IEEE Trans. Electron Devices, 61, 416 (2014). 13. Y. Zhao, H. Matsumoto, T. Sato, S. Koyama, M. Takenaka, and S. Takagi, IEEE Trans. Electron Devices, 57, 2057 (2010). 14. N. Taoka, M. Yokoyama, S. H. Kim, R. Suzuki, R. Iida, S. Lee, T. Hoshii, W. Jevasuwan, T. Maeda, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi, Tech. Dig. IEEE Int. Electron Device Meeting, 610 (2011). 15. N. Taoka, M. Yokoyama, S.-H. Kim, R. Suzuki, S.-H. Lee, R. Iida, T. Hoshii, W Jevasuwan, T. Maeda, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi, Appl. Phys. Lett., 103, 143509 (2013). 16. N. Taoka, M. Yokoyama, S.-H. Kim, R. Suzuki, S.-H. Lee, R. Iida, T. Hoshii, W. Jevasuwan, T. Maeda, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi, IEEE Trans. Device Mater. Reliab., 13, 456 (2013). 17. R. Zhang, X. Yu, M. Takenaka, and S. Takagi, IEEE Trans. Electron Devices, 61, 2316 (2014). 18. D. Kuzum, T. Krishnamohan, A. J. Pethe, A. K. Okyay, Y. Oshima, Y. Sun, J. P. McVittie, P. A. Pianetta, P. C. McIntyre and K. C. Saraswat, IEEE Electron Device Lett., 29, 328 (2008). 19. C. H. Lee, T. Nishimura, T. Tabata, S. K. Wang, K. Nagashio, K. Kita1 and A. Toriumi, Tech. Dig. IEEE Int. Electron Device Meeting, 416 (2010). 20. D. Kuzum, T. Krishnamohan, A. Nainani, Y. Sun, P. A. Pianetta, H.-S. Philip Wong and K. C. Saraswat, IEEE Trans. Electron Devices, 58, 59(2011). 21. C. H. Lee, C. Lu, T. Tabata, T. Nishimura, K. Nagashio and A. Toriumi, IEEE Symp. on VLSI Technol., T28 (2013). 22. R. Zhang, J.-C. Lin, X. Yu, M. Takenaka, and S. Takagi, IEEE Symp. on VLSI Technol., T26 (2013). 23. J. Franco, B. Kaczer, Ph. Roussel, J. Mitard, S, Sioncke, L. Witters, H. Mertens, T. Grasser, and G. Groeseneken, Tech. Dig. IEEE Int. Electron Device Meeting, 397 (2013). 24. G. Groeseneken, J. Franco, M. Cho, B. Kaczer, M. Toledano-Luque, Ph. Roussel, T. Kauerauf, A. Alian, J. Mitard, H. Arimura, D. Lin, N. Waldron, S. Sioncke, L.

49


Witters, H. Mertens, L. Ragnarsson, M. Heyns, N. Collaert, A. Thean and A. Steegen, Tech. Dig. IEEE Int. Electron Device Meeting, 828 (2014). 25. C. H. Lee, C. Lu, T. Tabata, T. Nishimura, K. Nagashio, and A. Toriumi, IEEE Symp. on VLSI Technol., T28 (2013). 26. C. H. Lee, C. Lu, T. Tabata, W. Zhang, T. Nishimura, K. Nagashio, and A. Toriumi, Tech. Dig. IEEE Int. Electron Device Meeting, 40 (2013). 27. C. Lu, C. H. Lee, T. Nishimura and A. Toriumi, IEEE Symp. on VLSI Technol., T18 (2015). 28. M. Ke, X. Yu, R. Zhang, J. Kang, C. Chang, M. Takenaka and S. Takagi, Microelectron. Eng., 147, 244 (2015). 29. M. M. Frank, G. D. Wilk, D. Starodub, T. Gustafsson, E. Garfunkel, Y. J. Chabal, J. Grazul, and D. A. Muller, Appl. Phys. Lett., 86, 152904 (2005). 30. M. L. Huang, Y. C. Chang, C. H. Chang, Y. J. Lee, P. Chang, J. Kwo, T. B. Wu, and M. Hong, Appl. Phys. Lett., 87, 252104 (2005). 31. C.-H. Chang, Y.-K. Chiou, Y.-C. Chang, K.-Y. Lee, T.-D. Lin, T.-B. Wu, M. Hong, and J. Kwo, Appl. Phys. Lett., 89, 242911 (2006). 32. Y. Xuan, Y. Q. Wu, and P. D. Ye, IEEE Electron Device Lett., 29, 294 (2008). 33. R. Suzuki, N. Taoka, M. Yokoyama, S.-H. Kim, T. Hoshii, T. Maeda, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi, J. Appl. Phys., 112, 084103 (2012). 34. R. Suzuki, N. Taoka, S. Lee, S. H. Kim, T. Hoshii, M. Yokoyama, T. Yasuda, W. Jevasuwan, T. Maeda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi, Appl. Phys. Lett., 100, 132906 (2012). 35. D. H. Zadeh, H. Oomine, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, and H. Iwai, Tech. Dig. IEEE Int. Electron Device Meeting, 36 (2011). 36. C.-Y. Chang, M. Takenaka and S. Takagi, submitted to J. Appl. Phys. 37. A. Nainani, T. Irisawa, Z. Yuan, B. R. Bennett, J. B. Boos, Y. Nishi, and K. C. Saraswat, IEEE Trans. Electron Devices, 58, 3407 (2011). 38. M. Xu, R. Wang, and P. D. Ye, IEEE Electron Device Lett., 32, 883 (2011). 39. C．B. Zota, S.-H. Kim, M. Yokoyama, M. Takenaka and S. Takagi, Appl. Phys. Exp., 5, 071201 (2012). 40. Z. Yuan, A. Kumar, C.-Y. Chen, A. Nainani, B. R. Bennett, J. B. Boos, and K. C. Saraswat, IEEE Electron Device Lett., 34, 1367 (2013). 41. R. L. Chu, T. H. Chiang, W. J. Hsueh, K. H. Chen, K. Y. Lin, G. J. Brown, J. I. Chyi, J. Kwo, and M. Hong, Appl. Phys. Lett., 105, 182106 (2014). 42. M. Yokoyama, K. Nishi, S.-H. Kim, H. Yokoyama, M. Takenaka and S. Takagi, Appl. Phys. Lett., 104, 093509 (2014). 43. M. Yokoyama, H. Yokoyama, M. Takenaka, and S. Takagi, IEEE Symp. on VLSI Technol., 34 (2014). 44. M. Yokoyama, H. Yokoyama, M. Takenaka, and S. Takagi, Appl. Phys. Lett., 106, 073503 (2015). 45. K. Takei, M. Madsen, H. Fang, R. Kapadia, S. Chuang, H.-S. Kim, C.-H. Liu, E. Plis, J. Nah, S. Krishna, Y.-L. Chueh, J. Guo, and A. Javey, Nano Lett., 12, 2060 (2012). 46. A. Nainani, Z. Yuan, T. Krishnamohan, B. R. Bennett, J. B. Boos, M. Reason, M. G. Ancona, Y. Nishi, and K. C. Saraswat, J. Appl. Phys., 110, 014503 (2011). 47. Z. Yuan, A. Nainani, B. R. Bennett, J. B. Boos, M. G. Ancona, and K. C. Saraswat, Appl. Phys. Lett., 100, 143503 (2012).

50


48. S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. J. Phillips, D. Wallis, P. Wilding, and R. Chau, Tech. Dig. IEEE Int. Electron Device Meeting, 763 (2005). 49. T. Ashley, M. T. Emeny, D. G. Hayes, K. P. Hilton, R. Jefferies, J. O. Maclean, S. J. Smith, A. W-H. Tang, D. J. Wallis, and P. J. Webber, Tech. Dig. IEEE Int. Electron Device Meeting, 849 (2009). 50. M. Yokoyama, H. Yokoyama, M. Takenaka, and S. Takagi, Appl. Phys. Lett., 104, 262901 (2014). 51. A. Greene, S. Madisetti, P. Nagaiah, M. Yakimov, V. Tokranov, R. Moore, and S. Oktyabrsky, Solid State Electron., 78, 56 (2012). 52. M. Yokoyama, H. Yokoyama, M. Takenaka and S. Takagi, Appl. Phys. Lett., 106, 122902 (2015).

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Border Trap Density in Al2O3/InGaAs MOS: Dependence on Hydrogen Passivation and Bias Temperature Stress K. Tanga, R. Droopadb, and P. C. McIntyrea a

Department of Materials Science and Engineering, Stanford University, Stanford, California 94305, USA b Ingram School of Engineering, Texas State University, San Marcos, Texas, USA

We report on the role of hydrogen (forming gas) post-metal annealing to passivate border traps in Al2O3/In0.53Ga0.47As (100) gate stacks and of bias temperature stress treatments to generate/depassivate such traps. Experiments are carried out with Pd metal gates that efficiently dissociate molecular hydrogen during forming gas annealing, and they make use of InGaAs epitaxial layer substrates that are capped with arsenic after completion of their growth, to avoid unintentional oxide formation and disorder at the channel surface prior to atomic layer deposition of the Al2O3 gate dielectric. We find that forming gas anneal (FGA) greatly reduces both the interface trap density and border trap density measured in the gate stacks, but that the effectiveness of FGA for border trap passivation saturates for anneals with thermal budgets greater than 450°C/30 min. Both negative and positive bias temperature stress treatments are found to have no effect on the extracted border trap densities compared to nontreated capacitors.

Introduction In0.53Ga0.47As and atomic layer deposited Al2O3 are among the candidate channel and dielectric materials, respectively, for future high performance III-V n-channel metaloxide-semiconductor (MOS) devices [1]. InGaAs has low electron effective mass which promotes high performance operation of highly-scaled MOS devices [2]. Moreover, the ability to achieve large band offsets and a thermally stable interface [3] with Al2O3 makes it an interesting choice for an interlayer dielectric between an InGaAs channel and higher-k materials [4]. A longstanding problem for oxide/III-V structures has been the presence of interfacial charge traps that may cause Fermi level pinning during device operation [5, 6]. Apart from the well-known interface traps, electrically active defects in the oxide layer, called border traps, also affect the performance of MOS devices by trapping charges that tunnel into the oxide [7]. The electrical response of border traps can be distinguished from that of interface traps by 1) the presence of substantial frequency dispersion of the capacitance in accumulation, an energy range at which interface traps are not active [8]; 2) an often weak temperature dependence of this dispersion compared to the time constant for charging/discharging interface traps [9]; and 3) the fact that chemical treatments can selectively reduce interface trap dispersion while having no effect on the accumulation dispersion [10].

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The presence of a large and variable density of trapped charge in the dielectric layer of MOS field effect transistors (MOSFETs) produces threshold voltage instability and degradation of the on-state performance of such devices [11]. Therefore, the density of border traps in deposited MOS dielectric layers, particularly for channel materials that lack a stable and electrically resistive native oxide, is of great importance. Majority carriers in the semiconductor communicate with border traps in the oxide by tunnelingmediated trapping/detrapping (Figure 1). For the electrical characterization of border traps, Yuan et al. [12] recently developed a model that quantifies Nbt by analyzing the frequency-dependence of the MOS capacitance and conductance as function of gate bias in accumulation. Using their analytical approach, we have investigated experimental methods to alter Nbt in oxide/InGaAs gate stacks.

Figure 1. a) Schematic illustration of border traps (trap states produced by defects in an insulator layer) filling and emptying as a result of electron tunneling to and from conduction band states in an adjacent n-type semiconductor. b) Distributed impedance equivalent circuit model for the admittance response as a function of depth in the insulator, Y(x), of border traps in an MIS device [after reference 12]. In order to understand the nature of the border traps, it is helpful to prepare highk/InGaAs interfaces that are chemically abrupt. In this case, tunneling occurs between the n-InGaAs channel and traps in the deposited high-k layer, rather than defects in an illdefined, graded interface layer. In this paper, we describe samples prepared using an arsenic capping method to protect the InGaAs channel immediately prior to Al2O3 atomic layer deposition. As discussed in prior reports [10, 13, 14], this approach greatly suppresses formation of a native oxide/contaminant interlayer and produces a chemically abrupt high-k/InGaAs interface. Hydrogen annealing is found to effectively passivate border traps in ALD-Al2O3 [7]. This behavior is consistent with the results of ab initio simulations suggesting that the border traps in amorphous Al2O3 having energies near the conduction band edge of InGaAs are interacting Al dangling bonds, which are predicted to be passivated by bonding to hydrogen [15]. In this report, we examine the details of the forming gas (5% H2/95% N2) annealing (FGA) thermal budget and how it influences the border trap density in Al2O3.

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The reported reliability of Al2O3/InGaAs MOS devices with respect to bias temperature stability is poor [16-18]. Recently, it has also been reported that (low frequency) bias temperature instability is correlated with the border trap electrical response of these devices, measured at higher frequencies [17]. Finally, there is evidence [19] that border trap density can be enhanced by electrical bias stressing of high-k/InGaAs MOSFETs; however, the samples examined did not have surface treatments that would likely produce an abrupt interface. Therefore, in this work, we study the influence of both positive and negative bias temperature stability testing on the Al2O3 border trap density in MOS structures prepared using pre-ALD arsenic capping of the InGaAs channel. Forming Gas Anneal (FGA) Thermal Budget Effects on Defect Passivation Thermal desorption (decapping) of the protective As2 layer (nominally 80-100 nm thickness) on the n-In0.53Ga0.47As (100) channels was performed in situ in the ALD chamber just prior to the start of the ALD process. The InGaAs epilayers were grown by MBE onto lattice matched n-InP substrates. Decapping was performed at a constant chamber pressure of ~ 1×10-6 Torr and at a substrate temperature of 350°C. Under these desorption conditions, prior work [10, 20, 21] suggests that the InGaAs (100) surface should have an As-rich 2x4 reconstruction immediately after decapping. The substrates were cooled to 270°C in a few minutes, at which point the ALD process was begun. Atomic layer deposition of Al2O3 was performed using alternating cycles of trimethyl aluminum (TMA) and water vapor, at substrate temperature of 270°C. The ALD process began with a first pulse of TMA onto the arsenic-decapped InGaAs (100) surface. ALDAl2O3 deposition used a TMA precursor source temperature of 120°C and a water reservoir temperature of 100°C. A Fujikin flow control system (FCS) was used to dose these precursors into a load-locked, high vacuum (~ 1×10-7 Torr) base pressure ALD chamber. Nitrogen was used as the purge gas, and as a balance gas flow during precursor pulsing in the chamber to maintain a constant pressure of 180 mTorr during ALD. The purge duration between both TMA and H2O pulses was 60 s. The TMA pulse duration was 3 s and the H2O pulse duration was 4 s, corresponding to doses of 900 L and 1200 L, respectively. Palladium, ~ 50 nm in thickness and thermally evaporated through a shadow mask, was used a gate electrode to define circular MOS capacitors of either 100 µm or 200 µm diam. Post-metal FGA was performed on these capacitor structures in a quartz tube furnace at atmospheric pressure using 5% H2/95% N2 forming gas. Multi-frequency capacitance-voltage (C-V) curves were measured in the frequency range from 1 kHz to 1 MHz at room temperature in the dark, using a HP4284A LCR meter. The C-V data in Figure 2 illustrate the effects of FGA temperature on both the interface trap density (Dit) and the border trap density (Nbt) of these structures. The frequency dispersion observed in inversion for the n-InGaAs MOS capacitors arises from the charging of interface traps and can be related, quantitatively, to the Dit. The full conductance method [8] was used to determine the Dit energy distribution, and the estimated midgap Dit values are listed in Fig. 2. The border trap response gives rise in CV measurements to the capacitance dispersion observed in accumulation. Increasing FGA temperature up to 400°C decreases both Dit and Nbt significantly, indicating the increasing ability of atomic hydrogen to passivate dangling bonds at both the InGaAs interface and in the Al2O3 film. It is also noted that the flat band voltage shifts to less 55


positive values with increasing FGA temperature. This is consistent with the removal of negative near-interface fixed charge, as previously reported for ALD-Al2O3 films of similar thickness [22] on InGaAs (100).

Figure 2. Effect of post-metal FGA temperature on C-V characteristics of Pd/Al2O3/nInGaAs MOS capacitors with ALD-Al2O3 dielectric of ~ 3.3 nm ellipsometric thickness. Both the border trap (accumulation) and interface trap (inversion) response are suppressed by FGA at temperatures up to 400°C for 30 min anneal duration. Further increases in the FGA temperature or its duration cause a slight reduction in the Dit response relative to the 400°C/30 min FGA condition (Figure 3). Quantitative analysis of the capacitance- and conductance-voltage behavior of these MOS capacitors in accumulation using the distributed impedance equivalent circuit model [12] gives an estimate Nbt as a function of energy relative to the n-InGaAs conduction band edge. These values are summarized in Table I. It is evident that further increases in the FGA thermal budget do not reduce Nbt, suggesting that the effect of hydrogen passivation on defects in the Al2O3 layer saturates for anneals of greater than 30 min duration at 400°C. For the processing conditions used in this study, the saturation value of Nbt is estimated as ~ 1.0×1020 cm-3eV deep in accumulation at Vg = 2.0 V. In contrast, the full conductance method analysis of Dit suggests that it decreases by ~ 15% by increasing the FGA duration at 400°C to 60 min. Additional annealing data at FGA temperatures up to 500°C (not shown) show a similar trend, with mildly decreasing Dit and no change in Nbt at 500°C. We note that these quantitative results may be specific to the case of arsenic capping prior to ALD-Al2O3 deposition and to the use of an H2 dissociating gate electrode such as Pd.

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Figure 3. Increasing FGA temperature beyond 400°C causes a saturation of Nbt at a value of ~ 1.0×1020 cm-3eV under strong accumulation (Vg = 2.0 V). Data obtained from Pd/Al2O3/InGaAs MOS capacitors with ~ 3.3 nm ALD-Al2O3 thickness. Effect of bias temperature stability testing on border trap density Positive bias temperature stress has recently been reported by Jiao et al. [19] to generate traps in Al2O3/n-InGaAs gate stacks of both donor and acceptor character. The energy distributions of both types of traps are reported to extend into the range of energies above the conduction band edge of InGaAs, meaning that they can function as border traps (Fig. 1). Inspired by these results, we investigate the possibility of generating border traps by both positive and negative bias temperature stress treatments, using MOS structures that were prepared on initially As2-capped InGaAs channels to prepare chemically-abrupt ALD-Al2O3/n-InGaAs interfaces. In contrast to the experiments reported in reference 19, in which testing was performed on Ni/Au gated ALD-Al2O3/InGaAs MOSFETs, we employed Pd/4.3 nm Al2O3/InGaAs MOSCAPs after 400°C/30 min post-metal FGA. Both PBTI and NBTI testing was performed at a temperature of 100°C and under constant bias (either Vg = 1.5 V or Vg = 2 V) was applied for 30 min. In comparison, Jiao et al. applied positive gate bias Vg = 3.0 V for 500s at room temperature, across ALD-Al2O3 films of 8 nm physical thickness. Therefore, the electric field in the oxide was similar in both studies; however, the stress duration and temperature were higher for the work reported herein. Capacitance-voltage curves obtained before and after PBTI testing indicate +200 mV flat band voltage shift after bias temperature stress, but there is minimal change in the accumulation dispersion (Figure 4). Quantification of the Nbt using the distributed

57


impedance circuit model of Yuan et al. [12] shows essentially identical border trap density before and after electrical stress. This is not consistent with the data reported by Jiao et al. Instead, the most significant change in trap population observed in the C-V behavior of the Al2O3/InGaAs MOSCAPs after PBTI testing is a modest increase in interface trap density around midgap of InGaAs.

Figure 4. C-V profiles at 1 kHz and 1 MHz before and after positive bias stress at 100°C indicating ~ 200 mV positive shift in Vfb, and an increase in Dit in depletion. There is no detectable change in Nbt. Data obtained from a Pd/Al2O3/InGaAs MOS capacitor with ~ 4.3 nm ALD-Al2O3 thickness. Similar results were obtained after NBTI testing of identical MOSCAP samples. In this case, a much smaller, but still positive, Vfb shift was observed. No indication of Nbt generation was detected in analysis of the C-V data (Figure 5). Similar to the case of PBTI testing, however, a modest increase in interface trap density around midgap was extracted from the NBTI data using the full conductance method. Considering the differences between the observed bias temperature stress effects in this report, and those described previously by Jiao et al., it seems plausible that achieving a chemically abrupt Al2O3/semiconductor interface using an initially As2-capped InGaAs(100) surface produces a different population of near-interface defects during electrical stressing. In this interpretation, border traps in the ALD-Al2O3 layer are not formed under NBTI or PBTI conditions, although some interface state creation takes place. The situation arising from a graded and poorly-defined interface may include formation of border traps (corresponding to defects in the interlayer) under similar testing conditions.

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Figure 5. C-V profiles at 1 kHz and 1 MHz before and after negative bias stress at 100°C indicating ~ 70 mV positive shift in Vfb, and an increase in Dit in depletion. There is no detectable change in Nbt. Data obtained from a Pd/Al2O3/InGaAs MOS capacitor with ~ 4.3 nm ALD-Al2O3 thickness. Conclusions Border trap passivation and creation were investigated by applying (respectively) forming gas anneal and bias temperature stress treatments to Pd/ALD-Al2O3/n-InGaAs (100) MOS capacitors fabricated using methods that have been demonstrated to produce chemically-abrupt Al2O3/InGaAs interfaces. FGA was found to passivate both interface traps and Al2O3 border traps in these MOS structures with increasing effectiveness up to a thermal budget of 400°C/30 min. Longer duration/higher temperature FGA caused further modest reduction in Dit, but did not further reduce Nbt, indicating different chemical properties of the respective defects for hydrogen passivation. Both negative and positive bias temperature stress experiments did not result in Al2O3 border trap production; however, a modest increase in Dit near the midgap energy range of In0.53Ga0.47As was observed for both bias polarities. These results suggest that bias stress-induced border trap creation in high-k/III-V MOS devices is strongly related to interface abruptness of the details of oxide/semiconductor chemical bonding.

Acknowledgments We thank Mr. Masafumi Kitano for installation and characterization of the Fujikin FCS ALD precursor delivery system, and Prof. Andrew Kummel at UCSD for helpful discussions. This work was supported by the Semiconductor Research Corporation through the Non-Classical CMOS Research Center (Task ID 1437.008), the Stanford Initiative in Nanoscale Materials and Processes (INMP), and the US-Israel Binational Science Foundation. K.T. acknowledges financial support from a Stanford Graduate Fellowship.

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References 1. Q. Li, X. Zhou, C. W. Tang, and K. M. Lau, IEEE Electron Device Lett. 33, 1246 (2012). 2. J. A. del Alamo, Nature 479, 317 (2011). 3. G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 89, 5243 (2001). 4. L. Zhang, M. Gunji, S. Thombare, and P. C. McIntyre, IEEE Electron Device Lett. 34, 732, (2013). 5. W. Melitz, J. Shen, T. Kent, A. C. Kummel, and R. Droopad, J. Appl. Phys. 110, 013713 (2011). 6. E. O’Connor, S. Monaghan, K. Cherkaoui, I. M. Povey, and P. K. Hurley, Appl. Phys. Lett. 99, 212901 (2011). 7. E. J. Kim, L. Wang, P. M. Asbeck, K. C. Saraswat, and P. C. McIntyre, Appl. Phys. Lett. 96, 12903 (2010). 8. H. Chen, Y. Yuan, B. Yu, J. Ahn, P. C. Mcintyre, P. M. Asbeck, M. J. W. Rodwell, and Y. Taur, IEEE Trans. Electron Devices 59, 2383 (2012). 9. E. J. Kim, E. Chagarov, J. Cagnon, Y. Yuan, A. C. Kummel, P. M. Asbeck, S. Stemmer, K. C. Saraswat, and P. C. McIntyre, J. Appl. Phys. 106, 124508 (2009). 10. J. Ahn, T. Kent, E. Chagarov, K. Tang, A. C. Kummel, and P. C. McIntyre, Appl. Phys. Lett. 103, 071602 (2013). 11. D. Lin, A. Alian, S. Gupta, B. Yang, E. Bury, S. Sioncke, R. Degraeve, M. L. Toledano, R. Krom, P. Favia, H.Bender, M. Caymax, K. C. Saraswat, N. Collaert, and A. Thean, Tech. Dig. - Int. Electron Devices Meet. 2012, 28.3.1-28.3.4 12. Y. Yuan, B. Yu, J. Ahn, P. C. Mcintyre, P. M. Asbeck, M. J. W. Rodwell, and Y. Taur, IEEE Trans. Electron Devices 59, 2100 (2012). 13. B. Shin, J. B. Clemens, M. A. Kelly, A. C. Kummel, and P. C. McIntyre, Appl. Phys. Lett. 96, 252907 (2010). 14. J. Ahn and P. C. McIntyre, ECS Trans., 45, 183 (2012). 15. J. R. Weber, A. Janotti, and C. G. Van de Walle, Microelectronic Eng. 86, 1756 (2009). 16. E. Simoen, D.H-C. Lin, A. Alian, G. Brammertz, C. Merckling, J. Mitard, and C. Claeys, IEEE Trans. Dev. Mater. Reliability 13, 444-55 (2013). 17. A. Vais, K. Martens, J. Franco, D. Lin, A. Alian, P. Roussel, S. Sioncke, N. Collaert, A. Thean, M. Heyns, G. Groeseneken, and K. DeMeyer, Proceedings of the International Reliability Physics Symposium (IRPS), pp. 5A.7.1-5A.7.6 (2015). 18. F. Palumbo, I. Krylov, and M. Eizenberg, J. Appl. Phys. 117, 104103-1-8 (2015). 19. G. Jiao, C. Yao, Y. Xuan, D. Huang, P.D. Ye, and M.-F. Li, IEEE Trans. Electron Dev. 59, 1661-67 (2012). 20. W. Melitz, T. Kent, A. C. Kummel, R. Droopad, M. Holland, and I. Thayne, J. Chem. Phys. 136, 154706 (2012). 21. J. Shen, D. L. Winn, W. Melitz, J. B. Clemens, and A. C. Kummel, ECS Trans. 16, 463 (2008). 22. B. Shin, J.R. Weber, R.D. Long, P.K. Hurley, C.G. Van de Walle, and P.C. McIntyre, Appl. Phys. Lett. 96, 152908-1-3 (2010).

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Surface Passivation of High-k Dielectric Materials on Diamond Thin Films K.K. Kovi a,b, S. Majdi a, M. Gabrysch a, N. Suntornwipat a and J. Isberg a. a

Division of Electricity, Department of Engineering Sciences, Box 534, Angstrom Laboratory, Uppsala University, Uppsala, SE- 751 21, Sweden. b Center for Nanoscale Materials, Argonne National Laboratory, Argonne, IL – 60439, USA. Single-crystalline CVD diamond films have excellent electrical and material properties with potential in high power, high voltage and high frequency applications that are out of reach for conventional semiconductor materials. For realization of efficient devices (e.g. MOSFET), finding a suitable dielectric is essential to improve the reliability and electrical performance of devices. In the current study, we present results from surface passivation studies by high-k dielectric materials such as aluminum oxide and hafnium oxide deposited by ALD on intrinsic and boron doped diamond substrates. The hole transport properties in the intrinsic diamond films were evaluated and compared to unpassivated films using the lateral time-of-flight technique. The MOS capacitor structure, which forms the basic building block of the MOSFET is discussed.

Introduction Diamond is well known for its’ excellent properties like: high thermal conductivity (> five times to Cu), highest breakdown fields (10-20 MV/cm), high mobilities (4500 & 3800 cm2/Vs for electrons & holes, respectively) [1], high saturation velocity, wide band gap (5.47 eV), chemically inert, radiation hard and hardest of all the materials. These properties make diamond a unique semiconductor material for high voltage, high power and high temperature applications out of reach for conventional semiconductor materials. With recent progress in the growth of single-crystalline (SC) chemical vapor deposited (CVD) diamond, there has been a great attention towards diamond based electronic devices. By CVD process, it is also possible to dope with boron (p-type) and nitrogen & phosphorous (n-type) during the growth process by incorporating the dopants in the lattice. However, diamond still lacks shallow dopants and needs high activation energy. Nevertheless, the material properties of diamond are still attractive to pursue diamond based electronic devices. Several electronic devices based on SC-CVD diamond thin films have been realized, such as: Schottky diodes [2], P-I-N diodes [3], H-terminated FETs [4], MES-FETs [5], IR sensing devices [6], quantum [7] and valleytronic devices [8]. But, for efficient functionality and reproducibility, surface passivation is quite important. The surface passivation can improve the charge transport properties by reducing surface scattering effects, leakage currents etc. Our previous studies of passivation using SiO2 and Si3N4 have shown better transport properties in intrinsic diamond [9, 10]. Recently high-k dielectric materials have been getting greater attention due to the miniaturization of electronic devices. The current paper deals with surface passivation on intrinsic and

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boron doped SC- CVD diamond by using high-k dielectric materials such as: aluminum oxide (Al2O3) and hafnium oxide (HfO2). The electrical characterization on intrinsic diamond is done by lateral time-of-flight (L-ToF) technique [1, 11] and capacitance voltage (CV) measurements for MOS structures on boron doped diamond [12]. Experimental Sample preparation The SC-CVD diamond samples used in this study are grown by Element Six Ltd, using the microwave plasma CVD process. Prior to the process, the samples are boiled in a graphite etch, which consists of equal portions of nitric acid, sulphuric acid and perchloric acid at 180-200°C to clean any organic or metallic contaminants for 40 mins. For the ToF experiments, intrinsic diamond with thickness of 100 µm grown on type IIb HPHT diamond substrate is used. Ti/Al contacts of 10/250 nm thicknesses are deposited by sputtering after patterning with standard photolithography. The contacts cross-section can be seen in fig.1. The contacts have a dimension of 1.5 mm long and 0.5 mm width with a distance of 300 µm apart. Al2O3 and HfO2 measuring thicknesses of 20 nm are deposited between the contacts by using ALD. The sample is then wire-bonded on a ceramic holder for the measurements. For CV measurements, planar MOS structures are fabricated by using standard photolithography and sputtering to deposit metal contacts on boron doped diamond. The sample has a doping concentration of 3.1 x 1017 cm-3 as measured by SIMS. The sample geometries can be seen in Fig.1.

Figure 1. The geometry of the Lateral Time-of Flight contacts on intrinsic SC-CVD diamond with surface passivation of Al2O3 and HfO2 in between the contacts (left). Planar MOS structures on boron doped diamond (right).

Lateral Time-of Flight measurements A detailed description of the measurement set-up and the measurement process is reported in previous studies in [1, 10-11]. However, a brief description is given here for convenience: a quintupled Nd:YAG laser with a repetition frequency of 10 Hz producing short UV pulses (3 ns FWHM) of 213 nm wavelength is used as it has an energy higher than the bandgap of diamond (corresponding to 226 nm) to generate electron-hole pairs upon illumination. Applying a bias between the contacts and by laser illumination at one of the electrodes in the presence of a uniform electric field, the charge carriers traverse to the other electrode resulting in a current flow which is fed to a low noise amplifier and measured using a digital sampling oscilloscope. Several bias voltages from 4 to 150 V are applied. The bias is pulsed with 50 µs pulses to avoid undesirable charge accumulation.

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CV measurements Additionally, CV measurements are performed on the fabricated planar MOS structures. For this, an Agilent B1500 device analyzer is used. The measurements are performed at 1 MHz with an AC signal of 20 mV and applying a DC bias of -12 to 10 V to measure the differential capacitance in both the directions. Results & discussion The most important measurable quantity in the L-ToF is the transit time which is the time taken by the charge carriers to travel across the sample between the electrodes in the presence of an electric field. The full-width at half-maximum (FWHM) time of the obtained ToF curve gives the time of flight of charge carriers which is given by [11] (1) where is the applied electric field, d is the distance between electrodes, µ is the hole mobility, and is the saturation velocity which are obtained from plotting versus the inverse applied electric field as described in Ref. 13. The ToF curves obtained with Al2O3 and HfO2 surface passivation are compared with the measurements performed on the same sample without any passivation. Fig. 2 shows the ToF curves with two different biases of 16 and 90 Volts. The signal strength and the signal shape has improved considerably by surface passivation of the oxides. This is due to the reduction in charge trapping close to the surface. The illumination of the laser is strongly attenuated so as to enable measurement in the space-charge-free regime. A photo diode is used to monitor the illumination so that all the samples receive the same amount of illumination at the sample surface. Even though it appears from the curves that HfO2 passivation shows higher signal strength, but both the cases are still operated in the low field and space charge free regime. A more detailed analysis and calculations from the ToF curves shows the actual characteristics of charge transport.

Figure 2. The Lateral Time-of-Flight measurement curves (a). No surface passivation, (b) with Al2O3 as passivation layer in between the contacts and (c) with HfO2 as passivation layer. The hole mobility is calculated to study the charge transport properties using equation 1. The values of hole mobility obtained without any passivation is 1300 ± 20 cm2/Vs. With HfO2 and Al2O3 passivations, the calculated hole mobilities from the measurements are : 1400 ± 40 cm2/Vs and 1660 ± 15 cm2/Vs, respectively. The differences between the measured mobilities with and without passivation are substantial. With Al2O3, the

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mobility achieved is considered quite high. Al2O3 (8.4 eV) has a bandgap higher than that of HfO2. Also, the band gap of HfO2 (~5.6 eV) is close to the band gap of diamond (5.47 eV). This can be one of the reasons Al2O3 has better passivation properties on diamond. Furthermore, the CV measurement curves are plotted in Fig 3. A change in the flatband voltage is observed due to the presence of a high interface density in both the oxides. HfO2 shows a high positive oxide charge. Apart from that, a high frequency dispersion is also observed with HfO2 compared to Al2O3. Nevertheless, both oxides exhibit leakage through the oxide layer and a strong presence of interface states. Hence further studies are required to reduce the interface states and to explore different surface treatments for better surface passivation on diamond.

Figure 3. The CV measurement curves on planar MOS structures measured in both directions of the applied DC bias voltages for Al2O3 and HfO2. CV curves show signs of hysteresis and a high density of interface states. Conclusion It was shown that the selection of the dielectric material is of the utmost importance as surface passivation layers on diamond. The influence of the surface passivation layer on the charge transport near the interface was studied using the L-ToF technique, demonstrating the influence of surface passivation layers on the charge transport in intrinsic diamond. The measured hole mobilities in intrinsic diamond varied with the chosen dielectric oxide for the passivation layer which was attributed to a reduction in interface scattering and a reduced charge trapping at the diamond/passivation interface. Further studies are required to identify a better surface passivation material although Al2O3 has shown better passivation properties than HfO2. Acknowledgments The authors would like to acknowledge Swedish research council (VR).

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References 1. J. Isberg, J. Hammersberg, E. Johansson, T. Wikstrom, D. J. Twitchen, A. J. Whitehead, S. E. Coe, and G. A. Scarsbrook, Science, 297, 1670 (2002). 2. S.J. Rashid, A. Tajani, L. Coulbeck, M. Brezeanu, A. Garraway, T. Butler, N.L. Rupesinghe, D.J. Twitchen, G.A.J. Amaratunga, F. Udrea, P. Taylor, M. Dixon and J. Isberg, Diamond. Relat. Mater., 15 (2–3), 317-323 (2006). 3. K. Oyama, S.G. Ri, H. Kato, M. Ogura, T. Makino, D. Takeuchi, N. Tokuda H. Okushi, and S. Yamasaki, Appl. Phys .Lett., 94, 152109, (2009). 4. S.A.O. Russell, S. Sharabi, A. Tallaire, and D.A.J. Moran, IEEE Electron Device Lett., 33 (10), 1471-1473, ( 2012) 5. H. Taniuchi, H. Umezawa, T. Arima, M. Tachiki and H. Kawarada, IEEE Electron Device Lett., 22, 390, (2001). 6. S. Majdi, M. Kolhadouz, M. Moeen, K.K. Kovi and J. Isberg, Appl. Phys .Lett.,(2014). 7. M.V.G. Dutt, L. Childress, L. Jiang, E.Togan, J. Maze J et.al. Science, 316, 1312,(2007). 8. J.Isberg, M. Gabrysch, J. Hammersberg, S. Majdi, K.K. Kovi and D.J. Twitchen. Nature Mater. 12 , 760–764, (2013). 9. K.K. Kovi, S. Majdi, M. Gabrysch, I. Friel, R. Balmer and J. Isberg, MRS proceedings, 1282, 47-52, (2011). 10. K.K. Kovi, S. Majdi, M. Gabrysch and J. Isberg, ECS Solid Stat. Lett 3 (5), (2014). 11. K.K. Kovi, S. Majdi, M. Gabrysch and J. Isberg, Appl. Phys. Lett., 105, (20), 202102 (2014). 12. K.K. Kovi, Ö. Vallin, S. Majdi and J. Isberg, IEEE Electr. Device Lett, 36 (6), 603 (2015). 13. J. Isberg, S. Majdi, M. Gabrysch, I. Friel, R.S. Balmer, Diam. Relat. Mater. 18 1163-1166 (2009).

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Chapter 2 Nano Technology


Defects and Dopants in Silicon and Germanium Nanowires M. Fanciullia,b, M. Bellib, S. Palearia, A. Lampertib, A. Molleb, M. Sironia, and A. Pizioa a

Department of Materials Science, University of Milano Bicocca, Milano 20125, Italy b MDM Laboratory, IMM-CNR, Via C. Olivetti 2, Agrate Brianza 20864, Italy

The current status of the investigation of defects in silicon and germanium nanowires and at the interface between the group IV semiconductor and its oxide in 1D nanostructures is reviewed and discussed. The paper concentrates on nanowires produced by metal assisted chemical etching for silicon and by the vapor-liquid-solid (VLS) growth method for germanium. For silicon nanowires the role of defects at the interface between the semiconductor and its oxide and of hydrogen in passivating donor atoms is addressed. The experimental data on germanium nanowires are scarce and we report here only evidence of dislocations. Introduction Several architectures for ultra-scaled devices targeting classical and quantum information processing, chemical sensing, and energy harvesting and production rely on silicon and germanium nanowires (SiNWs, GeNWs) [1-7]. Despite the efforts in the preparation and characterization of these nanostructures, some fundamental issues remain relatively unexplored. In particular the investigation of defects in 1D nanostructures at the interface between the semiconductor and its oxide or other semiconductors or oxides in core-shell structures represent an important challenge, as the NW diameter reduces and the surfaceto-volume ratio increases [8, 9]. NWs represent also an interesting system to investigate more fundamental issues such as, for example, Mott transition, spin relaxation mechanisms and scattering processes. In this paper we will review the current experimental data and understanding of the n-type doping of silicon and germanium nanowires produced by different methods. The main results concerning the investigation of defects in SiNWs produced by different methods are related to the observation of defects at the Si/SiO2 interface and in the SiO2 [10-15] and to donors [12, 13, 16]. In this paper the role of hydrogen and defects at the interface between the semiconductor and its oxide in the donor de-activation mechanisms will be discussed. Data on SiNWs with diameters larger than 20 nm will be reported therefore excluding discussion of dielectric mismatch and quantum confinement effects, while for GeNWs the investigated structures, with diameters in the range 20-80 nm may show electron quantum confinement effects. Experimental data on defects and dopants in GeNWs are scarce in the literature. The EPR signal observed by Luo et al. [17], and attributed to surface dangling bonds, is the only reported result. Dopants (B and P) in GeNWs have been observed by Raman spectroscopy [18]. For GeNWs the observation of defects at the Ge/GeOx interface, observed in bulk Ge[19], and the investigation of their role in the donor deactivation mechanisms is still a challenge. Experimental Methods

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Nanowires fabrication. SiNWs were prepared according to the procedure described by Zhang et al. [20]. Either highly resistive (ρ>5000 Ω cm) silicon (100) wafers or silicon (100) p-type wafers (ρ=812 Ω cm) with a 10 µm thick epilayer on top, n-type (phosphorus doped) with dopant concentration of ND=1×1017 cm-3 have been used. Samples having an area of 2×2 cm2 were cleaned with a piranha solution (H2SO4/H2O2 3:1 v/v) for 10 min at room temperature to entirely remove organics. Wafers were then rinsed with water, etched with a 4.8% HF aqueous solution for 3 min at room temperature, immediately placed into an Ag coating solution containing 4.6 M HF and 0.005 M AgNO3 for 1 min for electroless deposition of Ag nanoparticles, washed with water to remove the extra Ag+ ions and then immersed in the etchant solution composed of 4.8 M HF and H2O2 0.4 M for 4 min at room temperature. Samples were then washed with water, immersed in dilute HNO3 (1:1 v/v) to remove residual Ag nanoparticles, washed first with water, then with isopropyl alcohol, then they were left to dry in air. The samples were then finally cut to dimensions suitable for characterization (3×12 mm2). Further annealing steps, aiming at the investigation of the defects evolution, were performed in a rapid thermal annealing system or in a horizontal furnace, in N2 and at different temperatures in the range 60°C600 °C. After each annealing step the samples were left for 24 hours in air to maximize the Pb center signal as discussed later on. GeNWs (Nano-wire Tech Inc.) [21] were grown on Si(100) p-type (Boron) 10-100 Ω cm by the VLS method, using gold nanoparticles catalyst, inside a hot-wall CVD set-up, at a temperature of 300°C. TABLE I. Samples properties. Average diameters extracted from Scanning Electron Microscopy micrographs reflect the statistical data of an ensemble of some tens of nanowires. Additional structural information by TEM. Doping in SiNWs determined by Hall effect, in GeNWs nominal. Sample Average Diameter [nm] Doping (SEM) SiNWs-i 60±40 17 SiNWs-n 70±30 P, 10 cm-3 GeNWs-i 30±10 GeNWs-n 50±20 P, 2x1018 cm-3 GeNWs-cs 40±20 a-Si: B, 1019 cm-3 (external diameter) c-Ge: P, 2x1018 cm-3 a-Si shell 8±1 nm (TEM)

Characterization. The SiNWs have been characterized by a variety of methods to access their morphology, their chemical properties, and to address defects and dopants. Morphological characterization was performed with Scanning Electron Microscopy (SEM, Zeiss SUPRA 40), chemical properties were investigated with Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS, ION-TOF IV) and X-ray Photoelectron Spectroscopy (XPS, PHI 5600). ToF-SIMS mass spectra were acquired using a 25 keV Ga+ ion beam with few pA current over a 50 µm x 50 µm area for analysis and 1 keV Cs+ ion beam with nA current for raster sputtering over an area of 300 µm x 300 µm, in negative polarity and interlaced mode; secondary ions are collected in time-of-flight spectrometer granting a mass resolution of at least 7000 at the investigated masses. The analysis has been stopped after about 200 nm depth sputtering from the surface (calibrated from a SiO2 reference

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sample). XPS measurements were acquired using a monochromatic Al Kα X-ray source (1486.6 eV) with pass energy 5.85 eV over a mm2 area; the instrument resolution is 0.1 eV. XPS spectra were fitted using XPSPEAK4.1 software, considering Shirley background, doublets for Si 2p and Ge 3d peak with spin orbit splitting of 0.59 eV and 0.58 eV respectively, and pseudo-Voigt functions. Positions of the lines are calibrated on the C 1s line descending from adventitious carbon. The chemical environment at the surface of the NWs was investigated by Fourier Transform Infrared spectroscopy (FT-IR) using a Jasco FT/IR Michelson interferometer, in the wavenumber range 4000-400 cm-1 with 0.25 cm-1 resolution. Absorbance spectra were measured at room temperature, using a double stage rotary pump to evacuate the sample chamber. Dual beam measurement mode was operated by acquiring a reference spectrum without the sample (I0) as reference, then calculating sample absorbance (A) according to A=log(I0/I). Electron Paramagnetic Resonance spectroscopy (EPR) has been carried out in an X band (9.4 GHz) spectrometer equipped with a high Q-factor cylindrical cavity (Bruker EF4122sHQ). A frequency counter was used to monitor the microwave frequency. The gfactors and absolute spectral intensities were determined using the reference signal of a standard Bruker marker characterized by g factor g=1.97984(1) [22]. The samples were tied onto a quartz rod with teflon® tape and inserted into a flow-cryostat capable of operating at temperatures in the range 4 K – 300 K. Experimental results and discussion Silicon Nanowires. In Fig. 1 the morphology of the SiNWs produced by MACE is shown in a representative SEM micrograph. These images show vertically aligned porous NWs with diameters in the range 25-200 nm and an average diameter of ~ 60 nm. The nanowires height, 11.3 µm in the example of Fig. 1, can be tuned by adjusting the etch time and the concentrations of etching solution components. Morphological parameters were essentially unaffected by the thermal treatments in the adopted conditions. ToF-SIMS mass spectra at nominal mass m=31 amu and m=32 amu are shown in Fig. 2a and Fig. 2b respectively. At mass m=31 amu (Fig. 2a) we can distinguish the presence of at least 4 contributions from different ions and, in particular, from lower to higher mass 31P, 30SiH, 29SiH2 and 28SiH3 [23, 24]. The intensity of SiH-related masses denotes the high contribution from Si-H bonds in the as-prepared nanowires. The peak related with P can be hardly seen as a shoulder in the tail of the 30SiH contribution, not fully de-convoluted from the 30SiH mass contribution. It is worth noticing that the chosen measurement setup is capable of granting full peak separation (i.e. mass resolution) between P and 30SiH on flat P-doped wafer. Here the observed overlapping underlines the high contribution from SiH-related ions. Looking at mass m=32 amu we have a further confirmation of SiH ion abundance, as can be seen from the clear detection of contributions from 30SiH2, 29SiH3 and 28SiH4 ions [23, 24]. Further, here we observe a contribution from sulfur and oxygen (seen as molecular O2 ion). To further elucidate the chemistry of as-prepared NWs, with a particular attention to the surface and sub-surface regions, we performed XPS measurements across the Si 2p spectral region. From the fitting we could resolve the major contribution originating from Si0 chemical state and the presence of minor contribution from SiO and SiO2 oxide states. The presence of the sub-oxidation contribution is probably due to the short exposure in air while transferring the sample from the clean room to the (ex-situ) XPS analysis chamber. Further, the fitting is well

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matched only when also considering a contribution at 99.6 eV associated with SiH bond [25, 26]. FT-IR data reported in Fig. 2d for the as-prepared SiNWs revealed the prevalence of Si-H bonds evidenced by the Si-Hx peaks (2087, 2110, 2141 cm-1) and the limited contribution of OySi-Hx shoulders (2196, 2250, 2273 cm-1) [27, 28]. Almost no oxidation at the surface of nanowires can be inferred from the absence of the typical infrared absorption bands of the SixOy vibrational modes in the region 1065 - 1176 cm-1 (not shown).

Figure 1. SEM micrograph cross section view of typical intrinsic SiNWs produced by MACE, showing vertically aligned wires and a flat etch profile. The nanowires are 11.3 µm tall, and display diameters in the range 25 – 200 nm, with an approximate average diameter of 60 nm. Inset: detail at high magnification showing the porosity at the surface of some relatively large nanowires.

Figure 2. a), b) ToF-SIMS mass spectra for as-fabricated phosphorus-doped SiNWs at nominal mass m=31 amu and m=32 amu. Note the strong contribution from SiH-related ions. c) XPS spectrum across Si 2p region: contributions from Si0 and SiH are well evident. d) FT-IR absorbance spectra recorded in dual beam mode: Si-Hx peaks (2196, 2250, 2273 cm-1, indicated by the blue lines) prevail over the OySiHx (2196, 2250, 2273 cm-1, red lines). Signals of the SiOx vibrational mode are absent in the spectral region 1065 - 1173 cm-1 (not shown). Resolution is reduced to 2 cm-1 to suppress the thin film interference pattern due to internal reflections in the substrate.

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Electron paramagnetic resonance of the as prepared intrinsic SiNWs does not show any resonance, while the n-type SiNWs show the hyperfine splitted resonance of the substitutional P [29]. Upon annealing and exposure to air the signals of the well-known Pb center [30-32] appears in both samples, while the P doublet first increases and, when the Pb signal appears, starts to decrease as reported in Fig. 3. Upon annealing of doped SiNWs in N2 in the temperature range 60-300°C, EPR reveals the increase of the P0 resonance. This result is attributed to the dissociation of PH complexes formed during the MACE process (PH)0 → P++ H-

[1]

The dissociation, observed upon isothermal annealing, is consistent with the first-order rate law kinetics observed in porous silicon

(

I(t) =I0 1 − e− kt k =k 0e − E a /k B T

)

[2] [3]

with values of the constants k0=6x1013 s-1; Ea=1.2 eV reported in literature [33-35] (see Fig. 3d). Donor passivation by hydrogen has been extensively studied for P-doped bulk (nanoporous) Si [33-36]. First-principles pseudopotential-density functional calculations revealed that H is located on the extension of a P-Si bond on the Si side, with the Si-H pair relaxing away from P leaving the P atom threefold coordinated [37, 38]. The electronic level scheme of acceptors and donors in silicon nanowires produced by the VLS method has been recently investigated by Sato and coworkers using deep level transient spectroscopy and photon-induced current transient spectroscopy [39]. For n-type SiNWs they reported four levels in the gap. In particular the E2 (with 0.25 eV activation energy) was not assigned to any specific defect, while the E2B (with 0.26 eV activation energy) was associated with the E-center (P-V complex). We did not observe, by EPR signals, which could be attributed to the P-V complex. This result is not conclusive and additional work is necessary to clarify it. However, we tentatively suggest that the E2 level is related to complexes involving H. ToF-SIMS, XPS and FT-IR investigation of intrinsic or doped SiNWs annealed at temperatures higher than 300°C show: i) a decrease of the SiHx signals; ii) an increase of the SiOx signals. These results indicate hydrogen release from the SiNWs and a progressive oxidation. The latter strongly depends on the air exposure time after the annealing steps. Immediately after each annealing step EPR shows a very weak signal related to the presence of dangling bonds at the interface (Pb centers) between the SiNW and the growing SiOx layer. The Pb signal increases as function of exposure to air at room temperature with a time constant of the order of 9 hours as shown in Fig. 3c. The EPR spectrum is not affected by long settling time in inert environment, the Pb signal begins to increase only after exposure to air, as we verified in one case by leaving the sample at room temperature for 18 h in N2. It is possible to indirectly investigate the dissociation kinetics of the Si-H bonds by recording the increase of the maximum Pb signal observed by EPR after each annealing step followed by 28 h exposure to air at room temperature. As a first-order approximation, the trend can be interpreted as an exponential recovery:

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(

I =I∞ 1 − e(t − t 0 )/τ

)

[4]

with maximum intensity I∞ dependent on annealing temperature (T) and time (t). Such a functional form is consistent with second order dissociation kinetics: 1 I∞ = [5] 1 + Ckt k = ν 0 e − E a /k B T

[6]

with ν0 = 120 cm2s (fixed) and Ea = 2.39±0.02 eV. The activation energy is an intermediate value between those found for the dissociation of the SiH and SiH2 centers as reported in Fig. 3e for crystalline silicon flat surface [40]. However such a model is only indicative as a simplified approximation and a thorough investigation is necessary to address the details of the dissociation kinetics. For example, the same intensity trend may be obtained by considering a distribution of activation energies and/or of the preexponential factor. Nevertheless, the steep slope of the Pb intensity upon isochronal annealing allows to exclude any first order process as the origin of Pb signal increase. In such a case a smoother slope is expected, even in the absence of a distribution of the relevant parameters. It is interesting to note that XPS and FT-IR show the oxidation of silicon well before the occurrence in the EPR spectrum of the Pb-related signals. The silicon oxide should go through small re-arrangements not visible with XPS or FT-IR leading eventually to the interfacial defects formation. The average diameter of the SiNWs is larger than the value below which quantum confinement and dielectric mismatch effects should be observed. However, the SiNWs system allows a detailed and controlled investigation, using EPR, of the depletion region formation due to interface defects, since the Pb center concentration can be modified by annealing followed by exposure to air. Fig. 3f reports the intensity of the P and Pb signals after an initial annealing step followed by exposure to air. The intensities of the P and of the Pb, determined against the marker, have been measured at 15 K and at RT respectively to avoid saturation effects. As expected an increase of the Pb centers results in a decrease of the P signal.

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Figure 3. a) EPR spectrum (RT, H||[111]) after air exposure (t>20 h): the fit (individual components depicted as shifted below the experimental data) evidences two Pb peaks, as expected by symmetry considerations when the magnetic field is oriented along one of the [111] directions of the Si crystal. b) EPR spectrum (15 K, H||[011]) after air exposure: the fit evidences two Pb peaks, as expected when the magnetic field is oriented along one of the [011] directions of the Si crystal, the isotropic doublet related to P0, the marker and other two peaks due to P clusters and to Si dangling bonds generated by the cut of the sample. c) Time evolution of the intensity of the EPR signals due to Pb centers following an annealing step at T = 365°C for 60'. After annealing, the sample was left at room temperature in N2 for 18 hours, then exposed to air. The EPR spectrum of the annealed sample did not reveal any signal and was not affected by the long exposure time to an inert atmosphere. The Pb signals begin to increase only after exposure to air. The maximum intensity is determined by the annealing temperature. d) Intensity of the P0 peaks upon isothermal annealing at T = 60°C. Data are consistent with the dissociation kinetics of PH complexes described by Eq. (2) [33-35]. e) Maximal Pb intensity after isochronal anneal (t = 1 h). In the figure the dissociation of SiH and SiH2 are reported for comparison. f) Intensity of the Pb and P0 centers as function of exposure to air after an annealing step.

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Germanium Nanowires. In Fig. 4a the morphology of the GeNWs produced by the VLS method is shown in a representative SEM micrograph. In the inset a detail showing the formation of clusters attributed, using EDX investigation (not shown), to Ge/GeO2. In the case of core shell structures, the thickness of the Si shell has been determined with TEM (not shown). The relevant structural properties are reported in Table I.

Figure 4. a) Plan-view SEM image of GeNWs. In the inset a detail of the Ge/GeO2 clusters; b) Ge 3d XPS of core-shell GeNWs; Ge 3d XPS of n-type GeNWs. The chemical environment of the Ge nanowires is elucidated by investigating the Ge 3d core level photoemission lines in Fig. 4b, 4c. From a qualitative comparison of the Ge 3d line of the n-doped Ge NW and and core-shell NW, we notice that in both samples the Ge 3d lines are split in two components. This reveals that Ge is partially oxidized, but the degree and the details of the oxidation are different in the two structures. To get through this difference, the XPS data were deconvoluted according to fit strategy reported in Ref. [41]. Positions of the lines are calibrated on the C 1s line descending from adventitious carbon. The outcome of the Ge 3d line deconvolutions is illustrated in Fig. 4b and 4c for the CS and Ge NW system, respectively. Both spectra in Fig. 4b and 4c can be fitted with a minimal number of three Voigt functions, denoted as Ge0, Ge2+, and Ge4+. These components are associated with elemental Ge bonding in the NW, and oxidized Ge in the GeO and GeO2 stoichiometry, respectively. Despite the qualitative similarity between the Ge 3d lines of the CS and Ge NW structures, some differences can be inferred by comparing the details of the two fits to the data. First, the width of the elemental component Ge0 is 0.72 eV and 0.92 eV in the CS and in the Ge NW system, respectively. This discrepancy can be attributed to a different degree of structural or morphological disorder in the two configurations. Second, the Ge2+ component in the CS system is comparatively broader and shifted to slightly higher binding energy. This can be due to the fact that the Ge2+ component in the CS system involves not only the GeO stoichiometry, but also other minor sub-stoichiometric species. In both configurations, the majority of the oxidized Ge bonding corresponds to a GeO2 stoichiometry.

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Electron spin resonance investigations of the different GeNWs structures did not reveal any signal which could be attributed to dangling bonds at the Ge/GeO2 interface [19 and references therein], to Si/SiO2 interfaces (for the CS structure), or to donors in Ge [42]. In intrinsic GeNWs we observed broad and isotropic resonances, as shown in Fig. 5. These lines appear after optical excitation and persist for hours in dark at low T. The signals are consistent with a powder distribution of paramagnetic centers related to dislocations, as reported in literature for bulk low doped dislocated Ge [43]. Work is in progress to search for additional paramagnetic defects and donors in GeNWs.

Figure 5. EPR of intrinsic GeNWs recorded at 4 K in dark, but after exposure to light. The spectrum has been fitted only in the high field region. The fit reveals at least three broad Lorentzian signals attributed to dislocations. The line below the spectrum is a subtracted baseline. Resonances at B < 400 mT are due to the Bruker marker and to other centers not related to the GeNWs. Conclusions SiNWs produced by the MACE method and GeNWs produced by the VLS technique have been investigated by electron spin resonance spectroscopy to investigate defects and dopants, and by complementary techniques (SEM, TEM, XPS, ToF-SIMS, FT-IR) to determine the morphological and chemical properties. The nanowires, in addition to their interest steaming from the different applications, represent also a model system in which several intriguing phenomena may be investigated. In SiNWs we have shown how H is terminating the nanowire surface preventing its oxidation and the passivating of donors. Upon thermal treatments and exposure to air the nanowires go through a series of chemical reactions leading to the dissociation of PH complexes, H desorption, oxidation, formation of defects at the interface between Si and SiO2 , the Pb centers, which leads to the formation of a depletion region deactivating some of the donors. Due to the average size of the investigated SiNWs, quantum confinement or dielectric mismatch effects have not been detected by EPR. GeNWs did not reveal any EPR signal attributable to donors or Ge/GeO2 interfacial defects. The EPR spectra of intrinsic GeNWs show, upon illumination at low T, broad resonances attributable to dislocations.

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Acknowledgments We thank Prof. S. Binetti at the University of Milano Bicocca for her assistance in the FT-IR measurements.

References 1.

P. Yang, R. Yan, and M. Fardy, Nano Lett. 10, 1529 (2010)

2.

Y. Huang, and K-N. Tu, Silicon and Silicide Nanowires: Applications, Fabrication, and Properties, CRC Press (2013)

3.

M. Hasan, M. F. Huq, and Z. H. Mahmood, SpringerPlus 2, 151 (2013)

4.

K-Q. Penga, X. Wanga, L. Lia, Y. Hua, and S-T. Leeb, Nano Today 8, 75 (2013)

5.

S.T. Picraux, S.A. Dayeh, P. Manandhar, D.E. Perea, and S.G. Choi, JOM 62, 35 (2010)

6.

L. Z. Pei, and Z. Y. Cai, Recent Patents on Nanotechnology 6, 44 (2012)

7.

N.K. Mahenderkar, Y-C. Liu, J.A. Koza, and J.A. Switzer, Nanotechnology 26, 195705 (2015)

8.

V. Schmidt, S. Senz, and U. Gösele, Appl. Phys. A. 86, 187 (2007)

9.

M. T. Björk, H. Schmid, J. Knoch, H. Riel, and W. Riess, Nature Nanotech. 4, 103 (2009)

10. A. Baumer, M. Stutzmann, M. S. Brandt, F. C.K. Au, and S. T. Lee, App. Phys. Lett. 85, 43 (2004) 11. R. P. Wang, Appl. Phys. Lett. 88, 142104 (2006) 12. M. Fanciulli, A. Vellei, C. Canevali, S. Baldovino, G. Pennelli, and M. Longo, Nanosci. Nanotechnol. Lett. 3, 568 (2011) 13. M. Fanciulli, A. Molle, S. Baldovino, and A. Vellei, Microelectronic Engineering 88, 1482 (2011) 14. M. Jivanescu, A. Stesmans, R. Kurstjens, and F. Dross, Appl. Phys. Lett. 100, 082110 (2012) 15. K. Yin, Y. Zhao, X. Wang, L. Liu, G. Xue, S-T. Lee, and M. Shao, App. Phys. Lett. 104, 033110 (2014) 16. N. Fukata, S. Ishida, S. Yokono, R. Takiguchi, J. Chen, T. Sekiguchi, and K. Murakami, Nano Lett. 11, 651 (2011) 17. L. Luo, X. Yang, F. Liang, J. Jie, C.Wu, Li Wang, Y. Yu, and Z. Zhu, J. Phys. Chem. C 115, 24293 (2011) 18. N. Fukata, K. Sato, M. Mitome, Y. Bando, T. Sekiguchi, M. Kirkham, J. Hong, Z.L. Wang, and R. L. Snyder, ACS Nano 4, 3807 (2010) 19. S. Paleari, S. Baldovino, A. Molle, and M. Fanciulli, Phys. Rev. Lett. 110, 206101 (2013)

78


20. M. Zhang, K. Peng, X. Fan, J. Jie, R. Zhang, S. Lee, and N. Wong, J. Phys. Chem. C 112, 4444 (2008) 21. www.nano-wirestech.com 22. Bruker EPR Chromium marker 23. G. Audi, and A. H. Wapstra, Nucl. Phys. A 565, 1 (1993) 24. G. Audi, and A. H. Wapstra, Nucl. Phys. A 595, 409 (1995) 25. A. Thøgersen, J.H. Selj, and E.S. Marstein, J. Electrochem. Soc. 159, D276 (2012) 26. M.Y. Bashouti, K. Sardashti, J. Ristein, and S. Christiansen, Nanoscale Research Letters 8, 41 (2013); M.Y. Bashouti, M. Pietsch, K. Sardashti, G. Brönstrup, S.W. Schmitt, S.K. Srivastava, J. Ristein, J. Arbiol, H. Haick, and S. Christiansen, Hybrid Silicon Nanowires: From Basic Research to Applied Nanotechnology, in «Nanowires: Recent Advances» edited by X. Peng, ISBN 978-953-51-0898-6, Published 19 December 2012 under CC BY 3.0 license, by INFOTECH, Chapter 9, pp.177-210. doi:10.5772/54383. 27. D. B. Mawhinney, J. A. Glass, and J. T. Yates, J. Phys. Chem. B 101, 1202 (1997). 28. X. H. Sun, S. D. Wang, N. B. Wong, D. D. D. Ma, S. T. Lee, and B. K. Teo, Inorg. Chem. 42, 2398 (2003) 29. G. Feher, Phys. Rev. 114, 1219 (1959) 30. P.J. Caplan, E.H. Pointdexter, B. Deal, and R.R. Razouk, J. Appl. Phys. 50, 5847 (1979) 31. A. Stesmans, and V. Afanasev, J. Appl. Phys. 83, 2449 (1998) 32. K. L. Brower, Semicond. Sci. Technol. 4, 970 (1989) 33. K. Bergman, M. Stavola, S. J. Pearton, and J. Lopata, Phys. Rev. B 37, 2770 (1988) 34. K. Murakami, H. Suhara, S. Fujita, and K. Masuda, Phys. Rev. B 44, 3409 (1991) 35. S.J. Pearton, and J. Lopata, App. Phys. Lett. 59, 2841 (1991) 36. K. Bergman, M. Stavola, S. J. Pearton, and T. Hayes, Phys. Rev. B 38, 9643 (1988) 37. K. J. Chang, and D. J. Chadi, Phys. Rev. Lett. 60, 1422 (1988) 38. P. J. H. Denteneer, C. G. Van de Walle, and S. T. Pantelides, Phys. Rev. B 41, 3885(R) (1990) 39. K. Sato, A. Castaldini, N. Fukata, and A. Cavallini, Nano Lett. 12, 3012 (2012) 40. P. Gupta, V. Colvin, and S. George, Phys. Rev. B 37, 8234 (1988) 41. A. Molle, S. Spiga, and M. Fanciulli, J. Chem. Phys. 129, 011104 (2008) 42. D. K. Wilson, Phys. Rev. 134, A265 (1963) 43. E.J. Pakulis, and C.D. Jeffries, Phys. Rev. Lett. 47, 1859 (1981)

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Topological States in Multi-Orbital Honeycomb Lattices of HgTe (CdTe) Quantum Dots W. Beugelinga, E. Kalesakib,c, C. Deleruec, Y.M. Niquetd, D. Vanmaekelberghe, C. Morais Smithf a

Max-Planck-Institut für Physik komplexer Systeme, Nöthnitzer Straße 38, 01187 Dresden, Germany b Physics and Materials Science Research Unit, University of Luxembourg, 162a avenue de la Faïencerie L-1511 Luxembourg, Luxembourg c IEMN – Département ISEN, UMR CNRS 8520, 59046 Lille, France d Université Grenoble Alpes & CEA, INAC-SP2M, L_Sim, 17 avenue des Martyrs, 38054 Grenoble, France e Debye Institute for Nanomaterials Science, University of Utrecht, 3584 CC Utrecht, The Netherlands f Institute for Theoretical Physics, Center for Extreme Matter and Emergent Phenomena, Utrecht University, Leuvenlaan 4, 3584 CE Utrecht, The Netherlands

We summarize recent theoretical works on artificial graphene realized by honeycomb lattices of semiconductor (CdSe, HgTe, CdTe) quantum dots forming a two-dimensional single-crystalline sheet. In the case of CdSe, we predict conduction bands with Dirac cones at two distinct energies and nontrivial flat bands. An analogous behavior is found in HgTe but, in addition, the strong spin-orbit coupling opens large topologically nontrivial gaps, leaving a flattened band detached from the others. We deduce that honeycomb lattices of HgTe quantum dots may constitute promising platforms for the observation of a fractional Chern insulator or a fractional quantum spin Hall phase. Similar predictions are made for CdTe but with smaller nontrivial gaps.

Introduction Two-dimensional (2D) semiconductor quantum wells are widely employed in (opto)electronic devices such as laser diodes or high electron mobility transistors. In addition, the 2D electron gases which can be formed in these structures exhibit very interesting physical properties like the quantum Hall effect (1). Recently, the interest for 2D materials has been considerably reinforced by the discovery of graphene (2,3) which motivated research on silicene (4) and other 2D layered materials. Graphene has a honeycomb lattice and therefore presents in its band structure Dirac cones at the K and K’ points of the Brillouin zone. On the basis of these discoveries, it was proposed to impose a honeycomb pattern on a conventional 2D semiconductor using lithography or electrostatic gating in order to obtain linear electronic dispersions close to the K points like in graphene (5-7). A new impetus to the field of artificial graphene recently came from the oriented attachment of nanocrystals which produces atomically-coherent semiconductor layers,

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equivalent to single-crystalline 2D superlattices (8-11). Square (8,11) and honeycomb (810) lattices of PbSe nanocrystals have been synthesized and their transformation into superlattices of CdSe nanocrystals by a Cd-for-Pb cation exchange has been demonstrated (8). Calculations that we have performed for square (12) and honeycomb (13,14) lattices of CdSe nanocrystals give band structures which strongly deviate from that of CdSe semiconductor quantum wells. In that case, the superimposed honeycomb geometry results in Dirac-type electronic bands (13,14). Atomically-coherent lattices of semiconductor quantum dots may also present an extremely interesting feature when combined with the honeycomb geometry, a strong Spin-Orbit Coupling (SOC) which may open nontrivial energy gaps. In that case, depending on the position of the Fermi level, the superlattices behave as topological insulators, i.e., materials with boundaries characterized by helical edge states in the gaps induced by the SOC (15,16). The edge states carry dissipationless currents, leading in 2D systems to the quantum spin Hall effect (QSHE), as initially predicted for graphene by Kane and Mele (17). Whereas in graphene the SOC is too small to give measurable effects (3), topological insulators with much larger gaps could be made from ordinary semiconductors on which a potential with hexagonal symmetry is superimposed (13,18,19). In this work, we show that honeycomb lattices of HgTe (CdTe) could be very promising platforms for the observation of interesting quantum phases that have been recently predicted on the basis of model Hamiltonians (20-26). We present atomistic tight-binding (TB) calculations of their conduction band (27). Such honeycomb lattices combine multi-orbital degrees of freedom and strong SOC, ingredients known to generate topologically non-trivial flat bands (20-22,28), opening the way to the realization of strongly correlated phases such as fractional QSHE or fractional Chern insulators (20-26). In the following, we summarize our main results previously obtained on honeycomb lattices of CdSe (10,13,14) and HgTe (27). We also present new results on lattices of CdTe. Methodology

Figure 1. Honeycomb lattice consisting of tangential spheres (diameter D equal to lattice spacing a) connected by horizontal cylinders (diameter d). The electronic structure of CdSe, HgTe and CdTe superlattices is calculated within the TB approximation. The TB Hamiltonian matrix is written in a basis of sp3d5s* atomic orbitals for each spin orientation. The TB parameters have been obtained by fitting to reference bulk band structures and are given by Ref. (12) for CdSe, Ref. (29) for HgTe, and Ref. (30) for CdTe. Since the systems that we have studied contain up to 105 atoms

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per unit cell, only near-gap eigenstates are calculated using an iterative numerical approach. We consider honeycomb lattices made of spherical nanocrystals of diameter D (Fig. 1). The spheres are tangential (center-to-center distance a=D). Between each pair of neighbors, we add a cylinder of atoms. The cylinder diameter d (0