Enhancement-Mode GaN Double-Channel MOS-HEMT with Low On-Resistance and Robust Gate Recess Jin Wei, Shenghou Liu, Baikui Li, Xi Tang, Yunyou Lu, Cheng Liu, Mengyuan Hua, Zhaofu Zhang, Gaofei Tang, and Kevin J. Chen Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong Phone: +852-23588969, Fax: +852-23581485, Email:
[email protected],
[email protected]
978-1-4673-9894-7/15/$31.00 ©2015 IEEE
Passivation
Conduction band energy
3.0 t1 = 2 nm t1 = 10 nm (a) 2.5 t1 = 6 nm 2.0 1.5 1.0 0.5 0.7 eV EF 0.0 -0.5 GaN/AlN/GaN AlGaN AlN -1.0 GaN -30
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Introduction GaN MOS-HEMT with partially or fully recessed gate has emerged as a promising candidate for high performance enhancement-mode (E-mode) power switching devices because the MOS-gate is compatible with the mainstream gate driver ICs [1-4]. Compared to partially recessed gate, fully recessed gate structure possesses some desired characteristics including more positive threshold voltage (Vth) and better process tolerance, but suffers from high MOS-channel resistance. This high channel resistance stems from low channel mobility caused by etching-induced damages and the inferior dielectric/GaN interface quality compared to that of the heterojunction-interface, even with significant improvement made by optimization of the recess process and interface engineering [5, 6]. Furthermore, the recess depth requires very tight control as over-etch (by a few nanometers) could easily interrupt the current flow between the 2DEG access regions and the MOS-channel due to large parasitic resistance at the gate-recess corners. Thus, new approaches are desired for obtaining low on-resistance E-mode MOS-HEMTs with robust gate recess control. In this work, an E-mode GaN double-channel MOS-HEMT (DC-MOS-HEMT) is proposed. The device features an upper MOS-channel and a lower heterojunction channel several nanometers apart. With the gate recess terminated at the upper channel, both channels are pinched off at zero gate bias, enabling E-mode operation, while the high electron mobility is maintained in the lower channel because of its separation from the etched GaN surface. The DC-MOS-HEMT delivers a positive threshold voltage, low on-resistance with high breakdown voltage, high saturation current, negligible dynamic Ron degradation, and a sharp subthreshold swing. The device performance shows enhanced insensitivity to the recess depth,
Fig. 1. Schematic structure of the DC-MOS-HEMT, featuring an upper MOS-channel and a lower heterojunction channel. The barrier consists GaN(cap)/AlGaN/AlN (3/17/1.5 nm). The AlN insertion layer (ISL) is 1.5 nm. t1 = 6 nm and t2 = 4.5 nm are adopted for the fabricated devices unless otherwise specified. An ultrathin PEALD AlN interfacial layer (IFL) and 18 nm Al2O3 are used as gate dielectric.
ns (×10 cm )
Abstract An enhancement-mode GaN double-channel MOS-HEMT (DC-MOS-HEMT) was fabricated on a double-channel heterostructure, which features a 1.5-nm AlN layer (AlN-ISL) inserted 6 nm below the conventional barrier/GaN hetero-interface, forming a lower channel at the interface between AlN-ISL and the underlying GaN. With the gate recess terminated at the upper GaN channel layer, a positive threshold voltage is obtained, while the lower channel retains its high 2DEG mobility as the heterojunction is preserved. The fabricated device delivers a small on-resistance, large current, high breakdown voltage, and sharp subthreshold swing. The large tolerance for gate recess depth is also confirmed by both simulation and experiment.
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Fig. 2. (a) Simulated band diagrams of the double-channel structure with passivation, i.e. in the access region of the device. (b) The influence of t1 on the balance of the two channels. While the total electron density stays the same when t1 is larger than 5 nm, a smaller t1 favors a higher 2DEG density in the lower channel.
thus exhibiting improved process tolerance. Double-channel heterostructure design The DC-MOS-HEMT, as shown in Fig. 1, features a 1.5-nm AlN insertion layer (AlN-ISL) several nanometers below the barrier(GaN-cap/AlGaN/AlN)/GaN interface. The simulated
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Fig. 3. Simulation of charge control in the two channels by gate bias. (a) Conduction bands at gate region with different VGS (t2 = 6 nm as example). With increasing VGS, the lower and upper channels are turned on sequentially. (b) The total 2DEG density. (c) and (d) show the electron densities of the lower channel and upper channel, respectively. The lower channel turns on at a lower VGS, and its electron density saturates when the upper channel turns on. The saturation density of the lower channel is determined by t2, and a smaller t2 favors a higher saturation 2DEG density in the lower channel.
conduction bands of this structure with passivation (i.e. in the access region) are plotted in Fig. 2(a). Because of the strong polarization field in the AlN-ISL, a lower channel is formed at the interface between AlN-ISL and the underlying GaN, in addition to the upper 2DEG channel at barrier/GaN interface. The thickness of the GaN upper channel layer (t1) determines the electron distribution between the upper and lower channel, as shown in Fig. 2(b). Due to the reverse electric field in GaN upper layer compared to AlN-ISL, a large t1 results in a lower 2DEG density in the lower channel and a higher 2DEG density in the upper channel. The total carrier density in the two channels remains relatively unchanged for t1 > 5 nm, since the net polarization charge introduced by AlN-ISL is zero. Fig. 3 shows conduction bands and electron densities in the recessed gate region, where the remaining GaN layer between the upper and lower channels has a thickness of t2. As the gate bias increases from 0 V, the lower channel is turned on first, followed by the upper channel. The lower channel is screened from the gate control when the upper channel is on, and therefore, the 2DEG in the lower channel saturates. A smaller t2 favors a tighter gate control of the lower channel. In this work, t1 = 6 nm was adopted, with which the lower channel delivers relatively high 2DEG density so the gate-controlled channels feature low resistances. Meanwhile, the 6-nm GaN upper channel layer provides a good tolerance for the gate recess. The experimental DC-HEMT wafer was grown by MOCVD on a 4-inch Si substrate, consisting of a barrier (3-nm GaN cap, 17-nm AlGaN, and 1.5-nm AlN), a 6-nm GaN upper channel layer, a 1.5-nm AlN insertion layer (ISL), and a 4-ȝm GaN buffer/transition layer. The as-grown wafer yields a carrier density of 8.6×1012 cm-2 and a channel mobility of 2080 cm2/(V·s) by Hall measurement. Fig. 4(a) shows the measured C-V characteristics of a fabricated circular
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Fig. 4. (a) Measured C-V curve of a circular SBD on the double-channel heterostructure, with the thickness of the upper channel layer t1 = 6 nm. The electron densities in the lower and upper channel are calculated by integrating C-V curve from -5 V to -1.3 V (corresponding to a depth of 27.5 nm), and from -1.3 V to 0 V, respectively. (b) Electron distribution of the heterostructure is extracted by differentiating 1/C2 again V. The two peaks of the electron are located at the AlN-ISL/GaN interface, and barrier/GaN interface.
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Fig. 5. (a) Surface morphology of the recessed gate region by AFM. The scanned area is 5×5 μm2 with an RMS roughness of 0.47 nm. (b) Trench profile along the recess window. The etching depth is ~23 nm, indicating removal of the entire barrier and ~ 1.5 nm GaN upper channel layer.
Schottky diode. The electron distribution in Fig. 4(b) was extracted by differentiating 1/C2 against V, showing two peaks at the barrier/GaN and AlN-ISL/GaN interfaces. The electron densities in the upper and lower channel were 2.8×1012 cm-2 and 5.9×1012 cm-2, respectively. Device fabrication and characteristics The fabrication process commenced with Ti/Al/Ni/Au Ohmic contacts formation. An AlN/SiNx (4/50 nm) stack was deposited as passivation layer [7]. Subsequently, planar isolation was accomplished by fluorine ion implantation [7]. After removing the passivation layer in the gate window by dry etching, the gate recess was performed by a hybrid dry-/digital-etching process featuring a low-power ICP etch, followed by 5 cycles of plasma-oxidation/HCl-dipping digital etching process to remove a thin surface layer that had been exposed to plasma during the dry etching [5]. The recessed region showed smooth morphology by AFM (Fig. 5(a)). The recessed depth was determined to be ~23 nm, indicating a complete recess of the barrier layer and removal of 1.5-nm GaN channel layer (Fig. 5(b)). An in situ remote plasma pretreatment was applied in PEALD chamber to remove the native oxide, followed by deposition of an ultrathin AlN and 18-nm Al2O3 as gate dielectrics [6, 8]. A subsequent post-deposition annealing at 500 ÛC in oxygen ambient was performed to improve the quality of gate dielectrics. Finally, Ni/Au metal gate was formed. Using the transfer length method (TLM), the Ohmic contact resistance of the DC-MOS-HEMT is measured to be 0.58 ȍ·mm, close to that (0.52 ȍ·mm) measured in a single-channel control sample.
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Fig. 9. Double-pulsed output characteristics with various VG/VD base measured on a device with LG/LGS/LGD = 2/2/15 ȝm. The device was hard switched with simultaneous high VG and VD at the transition time. Ron shows only 2% increase with a VD base of 60 V owing to the superior AlN/SiNx passivation and high quality MOS-interface.
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Fig. 6. I-V characteristics of a DC-MOS-HEMT with LG/LGS/LGD = 1.5/2/15 ȝm. (a) Transfer characteristics in linear scale and (b) in semi-log scale. The Vth is extracted to be 0.5 V from log scale at ID = 10 ȝA/mm, and to be 1.4 V from linear extrapolation. (c) The output curves with VGS from 0 to 10 V. The on-resistance is as small as 6.9 ȍ·mm at VGS = 10 V, while the maximum current is 836 mA/mm. (d) Off-state leakage/breakdown characterization with grounded substrate. A breakdown voltage of 705 V is determined at a drain current criterion of 1 ȝA/mm.
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Fig. 8. (a) I-V characteristics of the gate diode measured on a DC-MOS-HEMT. The forward gate breakdown occurs at 14.2 V. (b) Frequency-dependent C-V characteristics of a DC-MOS-diode, with frequency ranging from 1 kHz to 100 kHz. The first rise in the curves corresponds to the turn-on of the lower heterojunction channel, while the second rise is due to formation of the upper MOS-channel. The dispersion extracted at C = 100 nF/cm2 is 0.24 V between 1 kHz and 100 kHz. The small frequency dispersion and small G/Ȧ are both indicators of a high quality MOS interface.
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Fig. 7. Field-effect mobility extracted from a long-channel DC-MOS-HEMT with LG/WG = 44/100 ȝm, using ȝFE = LG·gm / (WG·C·VDS). C in the equation is the capacitance between gate and the lower channel. The peak field-effect mobility of the lower channel is as high as 1801 cm2/(V·s).
Fig. 6 shows the I-V characteristics of a DC-MOS-HEMT with LG/LGS/LGD = 1.5/2/15 ȝm. The threshold voltage is +0.5 V (@ IDS = 10 ȝA/mm) and +1.4 V from the linear extrapolation. A steep subthreshold swing of 72 mV/dec is obtained. The on/off drain current ratio is ~109, and the ratio of the on-state drain current to gate leakage current at VGS = 10 V is > 108. The device shows two obvious gm peaks with peak values of 170 mS/mm at VGS = 2.2 V and 103 mS/mm at VGS = 7.7 V, corresponding to the strongest gate modulation to the lower and upper channel. The on-resistance is 6.9 ȍ·mm (corresponding to a specific on-resistance of 1.48 mȍ·cm2, with 1.5 ȝm transfer length of each Ohmic contact taken into account for calculation of device area) at VGS = 10 V. For comparison, a single-channel normally-on GaN MIS-HEMT (without gate recess) with the same dimension exhibits an on-resistance of 6.7 ȍ·mm [9]. The maximum drain current is 836 mA/mm. The
off-state drain leakage is dominated by vertical drain-tosubstrate leakage current when the drain bias is larger than 400 V. The device exhibits a breakdown voltage of 705 V at a drain current criterion of 1 ȝA/mm. The low on-resistance is attributed to the presence of the lower channel that possesses high field-effect mobility, which is extracted from a long-gate DC-MOS-HEMT with WG/LG = 100/44 ȝm biased at VDS = 0.1 V, as shown in Fig. 7. The formula ȝFE = LG·gm/(WG·C·VDS) is used for calculation, where C is the capacitance between the gate electrode and the lower channel. A peak value is determined to be 1801 cm2/(V·s). The gate structure of the DC-MOS-HEMT is then investigated. I-V characteristics of a gate-diode are shown in Fig. 8(a), yielding a forward gate breakdown at 14.2 V. The gate leakage current is well-fitted with a Fowler-Nordheim model. The C-V characteristics (Fig. 8(b)) of a DC-MOS-diode exhibit two rising edges, corresponding to the formation of the lower heterojunction channel and the upper MOS-channel. The small frequency dispersion of the C-V curves indicates a high-quality MOS interface [10]. Double pulsed output characteristics of a DC-MOS-HEMT are shown in Fig. 9. At a drain base of 60 V, the dynamic Ron exhibits only 2% increase compared to the static Ron owing to the superior AlN/SiNx passivation [7] and high quality MOS-interface.
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TABLE I. COMPARISON OF DEVICES WITH TWO OVER RECESS DEPTHS Vth ǻVth Imax Ron (mA/mm) (V) (mV) (·mm) 6.9 836 0.50 50 A DC-MOS-HEMT with small over-etch (t2 = 4.5 nm) 8.0 669 0.35 66 An over-recessed DC-MOS-HEMT (t2 = 2 nm) * The peak mobility of the lower channel
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SS. (mV/dec) 72
1383
77
Acknowledgement This work was supported by Hong Kong Innovation and Technology Fund under ITS/192/94FP. References
Fig. 10. The influence of the remained upper channel layer thickness (t2) on Vth is studied with simulation. The inset shows the conduction bands at VGS = 0 V for different t2. The energy band of the upper channel layer is relatively flat before Vth. The simulated Vth shifts with t2 at a very small rate of 17.4 mV/nm.
Tolerance against gate recess The 6-nm GaN upper channel layer in the DC-MOS-HEMT results in robust control over the gate recess depth. From simulation, Vth is insensitive to the recessed depth as long as the etch stops in the upper GaN channel layer. As plotted in Fig. 12, Vth is reduced by a small value of 17.4 mV for every 1-nm over etch, because the conduction band of the upper channel is flat at the pinch-off condition as shown in the insert of Fig. 10. A largely over-etched DC-MOS-HEMT (described as the control device) (t2 = 2 nm) is compared with the standard device with small over-etch (t2 = 4.5 nm). Some key characteristics are listed in Table I. Vth of the control device is 0.35 V, which is close to that of standard device. The peak field-effect mobility of the lower channel is 1383 cm2/(V·s) for the control device. As a result, the on-resistance of the control device is 8.0 ȍ·mm, slight larger than the standard device. The degradation of mobility in the lower channel of the control device is originated from the closer separation between the lower channel and the MOS interface. Nevertheless, the control DC-MOS-HEMT still exhibits relatively high performance comparable to state-ofthe-art GaN single-channel E-mode transistors.
[1] W. Huang, Z. Li, T. P. Chow, Y. Niiyama, T. Nomura, and S. Yoshida, "Enhancement-mode GaN hybrid MOS-HEMTs with Ron,sp of 20 m-cm2," in Proc. ISPSD, Oralando, 2008, pp. 295-298. [2] T. Oka and T. Nozawa, "AlGaN/GaN recessed MIS-gate HFET with high-threshold-voltage normally-off operation for power electronics applications," IEEE Electron Device Lett., vol. 29, no. 7, pp. 668-670, Jul. 2008 [3] B. Lu, M. Sun and T. Palacios, "An etch-stop barrier structure for GaN high-electron-mobility transistors," IEEE Electron Device Lett., vol. 34, no. 3, pp. 369-371, Mar. 2013. [4] C. Liu, S. Yang, S. Liu, Z. Tang, H. Wang, Q. Jiang, and K. J. Chen, "Thermally stable enhancement-mode GaN metal-isolator-semiconductor high-electron-mobility transistor with partially recessed fluorine-implanted barrier," IEEE Electron Device Lett., vol. 36, no. 4, pp. 318-320, Apr. 2015. [5] Y. Wang, M. Wang, B. Xie, C. P. Wen, J. Wang, Y. Hao, W. Wu, K. J. Chen, and B. Shen, "High-performance normally-off Al2O3/GaN MOSFET using a wet etching-based gate recess technique," IEEE Electron Device Lett., vol. 34, no. 11, pp. 1370-1372, Nov. 2013 [6] S. Liu, S. Yang, Z. Tang, Q. Jiang, C. Liu, M. Wang, and K. J. Chen, "Al2O3/AlN/GaN MOS-channel-HEMTs with an AlN interfacial layer," IEEE Electron Device Lett., vol. 35, no. 7, pp. 723-725, Jul. 2014. [7] Z. Tang, S. Huang, Q. Jiang, S. Liu, C. Liu, and K. J. Chen, "High-voltage (600-V) low-leakage low-current-collapse AlGaN/GaN HEMTs with AlN/SiNx passivation," IEEE Electron Device Lett., vol. 34, no. 3, pp. 336-368, Mar. 2013. [8] S. Yang, Z. Tang, K. Wong, Y. Lin, C. Liu, Y. Lu, S. Huang, and K. J. Chen, "High-quality interface in Al2O3/GaN/AlGaN/GaN MIS structures with in situ pre-gate plasma nitridation," IEEE Electron Device Lett., vol. 34, no. 12, pp. 1497-1499, Dec. 2013. [9] M. Hua, C. Liu, S. Yang, S. Liu, K. Fu, Z. Dong, Y. Cai, B. Zhang, and K. J. Chen, "GaN-based metal-insulator-semiconductor high-electronmobility transistors Using low-pressure chemical vapor deposition SiNx as gate dielectric," IEEE Electron Device Lett., vol. 36, no. 5, pp. 448-450, May 2015. [10]S. Yang, Z. Tang, K. Wong, Y. Lin, Y. Lu, S. Huang, and K. J. Chen, "Mapping of interface traps in high-performance Al2O3/AlGaN/GaN MIS-heterostructures using frequency- and temperature-dependent C-V techniques," in Proc. IEDM, Washington, DC, 2013, pp. 152-155.
Conclusion Double-channel MOS-HEMT was fabricated on an optimized heterostructure, which features an upper MOS-channel and a lower heterojunction channel. With gate recess ending at the upper channel, the E-mode operation was obtained. Small on-resistance, large saturation current, high breakdown voltage, negligible dynamic Ron degradation, and sharp subthreshold swing are achieved simultaneously. The device performance shows a large tolerance for fabrication process.
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