1
A 0.3V FLOATING-GATE DIFFERENTIAL AMPLIFIER INPUT STAGE WITH TUNABLE GAIN Yngvar Berg1 , Snorre Aunet2 , Øivind Næss1 , Henning Gundersen1 and Mats Høvin1 1
Dept. of Informatics, University of Oslo, Gaustadalleen 23, P.O.Box 1080, Blindern, N-0316 Oslo, Norway. Fax: +47 22 85 24 01. Email:
[email protected] 2 Norwegian University of Science and Technology, Department of Physical Electronics, O.S. Bragstads pl 2, N-7034 Trondheim, Norway
ABSTRACT: In this paper we present a floating-Gate differential amplifier input stage with tunable gain. The input stage can be used in a differential ultra lowvoltage (ULV) floating gate (FG) transconductance amplifier. Measured data for the subcircuits operating at 0.8V, 0.5V and 0.3V are provided.
Ip
Ci Vin
Cr Ci
2. FGUVMOS TRANSISTORS For a multiple input FGUVMOS transistor each input has by design an effective coupling capacitance, Ci , to the floating-gate. The input signal (control gate) is attenuated with a factor ki = Ci /CT , where CT is the total load capacitance seen from the gate. ki is called the capacitive division factor for input i. The m-input floating-gate transistor currents are given by m Y 1 exp{ (Vi − Vdd /2)ki } In = Ids(nMOS) = Ibec nUt i=1 Ip = Ids(pMOS)
= Ibec
m Y i=1
exp{
1 (Vdd /2 − Vi )ki }, nUt
Vout
In
1. INTRODUCTION Lately, a number of floating-gate circuits have been proposed [1], [2], [3]. The ultra low-voltage UVprogrammable FG CMOS circuits (FGUVMOS) have been proposed for both analog and digital circuits [3], [4], [5]. The current levels or effective threshold voltages of all transistors are matched in a reversed biasing condition and applied UV-light [6]. We use UVactivated conductances [7] from the supply lines, Vdd and Vss , thus no additional programming circuitry is required. The proposed differential input stage can be expolited in amplifier design to improve linearity and to provide gain control. In section 2 the FGUVMOS transistor is shortly described. The ULV analog inverters are presented in section 3 with extensive measurements characterizing the inverters for supply voltages 0.8V , 0.5V and 0.3V and a wide range of current levels. The analog inverters were implemented in a standard digital double poly CMOS process, AMS 0.6µ, using transistor sizes 10/0.6µ, with inherent threshold voltages in the range of 0.7V to 0.9V . The differential input stage with tunable gain is presented in section 4.
Vin
Vout
Cr
(b)
(a) Ci
Ip Vm
V1
Ci Ci
Cr
Vout
Cr
V1
Vout
Vm In
Ci
(c)
(d)
Fig. 1. Floating gate analog inverters.
where Ibec is the programmed equilibrium current. Assuming a pMOS and an nMOS with common control gates and equal capacitive factors respectively we have that Ids(pMOS) =
(Ibec )2 Ids(nMOS)
0
≡ Ids(nMOS) .
3. FG ANALOG INVERTERS Assuming weak inversion, the currents Ip and In in figure 1 (a) can be expressed as ki Vdd ( 2 − Vin )} · Ip = Ibec exp{ nUt kr Vdd − Vout )} ( exp{ nUt 2 ki Vdd )} · (Vin − In = Ibec exp{ nUt 2 Vdd kr )} (Vout − exp{ nUt 2 We have that Ip = In , and hence Vout = {(A + 1)/2}Vdd − AVin , where A = ki /kr . If A = 1, that is ki = kr we get a pure analog inverter where Vout = ∗ . The transistor currents are equal to Vdd − Vin ≡ Vin the equilibrium point current and thus the frequency response of the analog inverter itself is only determined by Ibec .
2
0.8
Vb*
Vb Cb
0.7 0.6
Pi
Ipr
Ipi
Ci
0.5 Vout (V)
Cb
Vdd=0.8V
0.4
Cr
Vin
Cr
Ci
0.3
Vdd=0.5V
Ni
Iout
Vout
Vin
Vout Inr
Ini
Vb*
0.2 0.1 0
Cb
Vdd=0.3V
0
0.1
0.2
0.3
0.4 Vin (V)
0.5
0.6
0.7
0.8
-0.4
-0.6 Normalized gain
Fig. 4. Floating gate analog inverter with tunable gain. The capacitor values are Ci = 18.4f F , Cr = 6.0f F and Cb = 14.2f F . Vb∗ ≡ Vdd − Vb .
where A = ki /kr . With this circuit we can apply different gain values by using the capacitive division ratios, the gain will however be fixed after fabrication. For an additive inverter with gain equal to −1/m we have that kr = mki and hence m 1 X (Vi ). Vout = Vdd − m i=1
-0.5
-0.7 -0.8 Increasing Ibec -0.9
The analog inverter with tunable gain is shown in figure 4. The currents can be expressed as
-1 -1.1
0
0.1
0.2
0.3
0.4 0.5 Vin (V)
0.6
0.7
0.8
Fig. 3. Vdd = 0.8V. Measured analog inverter gain as a function input voltage.
The analog inverter in figure 1 (a) was implemented in the AMS 0.6µ CMOS process using transistor sizes 10/0.6µ (W/L) and capacitor values Ci = 18.4f F and Cr = 14.2f F . The analog inverter can be programmed to different supply voltages as shown in figure 2. The gain for a rail-to-rail input is shown in figure 3 for different current levels. The gain decreases when the output is getting close to the rails due to the linear region of the transistors. We can add more inputs to the basic analog inverter to provide a multiple input additive analog inverter. The currents Ip and In , shown figure 1 (c), can be expressed as ki mVdd X − ( (Vi ))} nUt 2 i=1 m
=
Ibec exp{
kr (Vdd /2 − Vout )} nUt m ki X mVdd )} Ibec exp{ ( (Vi ) − nUt i=1 2
· exp{ In
Vb
Vb*
Vb
Fig. 2. Measured analog inverter characteristics for supply voltages 0.8V , 0.5V and 0.3V .
Ip
Cb
=
· exp{
kr (Vout − Vdd /2)}. nUt
Ip = In yields: Vout
= (A
m X m 1 + )Vdd − A (Vi ), 2 2 i=1
Ipi
=
Ini
=
Ipr
=
Inr
=
ki (Vdd /2) − Vin } nUt ki Ib exp{ (Vin − Vdd /2)} nUt 0 kr Ib exp{ (Vdd /2) − Vout } nUt 0 kr Ib exp{ (Vout − Vdd /2)}, nUt Ib exp{
0
kb (Vb − Vdd /2)} and Ib = where Ib = Ibec exp{ nU t kb kb (Vb − Ibec exp{ nUt (Vdd /2) − Vb } = Ibec exp{ nU t −1 Vdd /2)} . Assuming that Vb >> Vdd /2 we can neglect Ipr and Inr and the circuit behaviour resembles a biased “digital” inverter, where the gain is limited by the Early effect and parasitic gate-drain overlap capacitance. On the other hand, when Vb
