A 100-mW 4 10 Gb/s Transceiver in 80-nm CMOS for ... - IEEE Xplore

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Christian Kromer, Member, IEEE, Gion Sialm, Christoph Berger, Thomas Morf, ... C. Berger, T. Morf, and M. L. Schmatz are with IBM Research, Zurich Re-.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

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A 100-mW 4 10 Gb/s Transceiver in 80-nm CMOS for High-Density Optical Interconnects Christian Kromer, Member, IEEE, Gion Sialm, Christoph Berger, Thomas Morf, Member, IEEE, Martin L. Schmatz, Member, IEEE, Frank Ellinger, Member, IEEE, Daniel Erni, Member, IEEE, Gian-Luca Bona, and Heinz Jäckel, Member, IEEE

Abstract—This paper describes a quad optical transceiver for low-power high-density short-distance optical data communication. Each channel transmits 10 Gb/s over a multimode (MM) fiber and features a link margin of 5.2 dB at a bit error rate (BER) of 10 12 . The transmit and receive amplifying circuits are implemented in an 80-nm digital CMOS process. Each driver consumes 2 mW from a 0.8-V supply, and each vertical cavity surface-emitting laser (VCSEL) requires 7 mA from a 2.4-V supply. The receiver excluding the output buffer consumes 6 mW from a 1.1-V supply per channel and achieves a transimpedance gain of 80.1 dB . The isolation to the neighboring channels is 30 dB including the bond wires and optical components. A detailed link budget analysis takes the relevant system impairments as losses and power penalties into account, derives the specifications for the electrical circuits, and accurately predicts the link performance. This work presents the highest serial data rate for CMOS transceiver arrays and the lowest power consumption per data rate reported to date.

TABLE I SEMICONDUCTOR AND TRANSCEIVER TECHNOLOGY ROADMAP



Index Terms—Backplane transceiver, CMOS analog integrated circuits, high-frequency CMOS circuits, high-speed link, optical fiber communication, optical interconnections, transceiver.

I. INTRODUCTION HE bandwidth requirements of processing and networking chips are not accelerating at the rate of Moore’s law [1]; however, they undoubtedly are increasing mainly because of the growth in computation power and Internet data traffic. Rent’s rule states that the bandwidth requirement of a module with pro, where cessing capability is proportional to [2]. Key trends in CMOS technology, chip complexity, and performance requirements for transceiver link systems are summarized in Table I [3]. The largest changes will face the minimum CMOS transistor gate length of ASICs, on-chip frequency, chip-to-board frequency, and the serial data rate of backplane transceivers. It is interesting to note that the

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Manuscript received April 1, 2005; revised July 16, 2005. This work was supported by the Swiss Federal Office for Professional Education and Technology under Contract/Grant KTI 4900.1. C. Kromer, G. Sialm, F. Ellinger, and H. Jäckel are with the Electronics Laboratory, Swiss Federal Institute of Technology (ETH) Zurich, 8092 Zurich, Switzerland (e-mail: [email protected]). C. Berger, T. Morf, and M. L. Schmatz are with IBM Research, Zurich Research Laboratory, 8803 Rüschlikon, Switzerland. D. Erni is with the Laboratory for Electromagnetic Fields and Microwave Electronics, Swiss Federal Institute of Technology (ETH) Zurich, 8092 Zurich, Switzerland. G.-L. Bona is with IBM Research, Almaden Research Center, San Jose, CA 95120 USA. Digital Object Identifier 10.1109/JSSC.2005.856575

maximum number of chip pads, the transceiver port count, the maximum power consumption, the minimum supply, and the threshold voltage approached their limits. The pad count is limited for mechanical reasons, because the chip pads require a certain physical size for the connections to the chip package by bond wires or solder balls. In the past CMOS technology generations, the threshold voltage could not be lowered at the same rate as the supply voltage. Consequently, the supply voltage is approaching the fundamental CMOS performance limit of about three times the transistor threshold voltage. The small increase in chip power consumption is not surprising since in large chip systems cooling is a significant problem and is attaining its limit. From the serial backplane data rate and the port count, the aggregate data rate can be derived. The maximum chip power consumption and the aggregate data rate yield the power consumption per data rate, a key figure of merit (FOM) for transceivers. In the near future, backplane transmW Gb/s are needed, assuming ceivers with an FOM that 10% of the chip power is consumed by the input-output (I-O) circuits. Electrical backplane transceiver arrays with FOMs in the range of 30–60 mW/(Gb/s) have been reported [4]–[7]. These large FOMs result from compensating the severe bandwidth-length limitation of the electrical transmission media by extensive digital signal processing (DSP). An efficient way to increase the bandwidth-length product of a short-distance link system is to use inexpensive optical technology. Such an optical link would consist of a low-cost multimode (MM) vertical cavity surface-emitting laser (VCSEL) on the transmitter side, an MM fiber (MMF) as transmission medium, and a photodiode (PD) on the receiver side (Fig. 1). An electrical driver (DRIVER) translates the digital data at the input of the transmitter into a current to modulate the VCSEL. The

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Fig. 1.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

Physical layer block diagram of an optical link.

TABLE II PERFORMANCE COMPARISON OF RECENTLY PUBLISHED OPTICAL TRANSCEIVER ARRAYS

VCSEL converts the modulated current into an optical signal, which is transmitted to the PD over an optical channel. The PD converts the optical power into a current, which is converted back to digital data at the output of the receiver by an electrical amplifier (AMP). To meet the aggregate Tb/s bandwidth demand (Table I) in future optical backplanes and chip-to-chip links, hundreds of parallel high-density channels are required. Therefore, all circuits need to be optimized for low power consumption, owing to limited system power budgets. A summary of recent state-of-the-art optical interconnect transceiver array publications is given in Table II. All designs, listed in Table II, contain transmit and receive amplifying circuits and do not include clock-and-data-recovery (CDR) or MMF equalization. FOMs in excess of 20 mW/(Gb/s) for any technology are reported, and the highest serial data rate for CMOS transceiver arrays was 2.7 Gb/s. In this work, a very low FOM of 2.5 mW/(Gb/s) and a serial data rate of 10 Gb/s are presented. The goal of the link design is to demonstrate the feasibility of a high-speed array implementation on a digital CMOS process with low power consumption, low crosstalk between neighboring channels, sufficient link margin, small chip area, and no external components except the VCSEL and PD arrays as well as bypass capacitors. The paper is organized as follows. In Section II, an optical link analysis is performed, which derives the fundamental performance limitations of a high-density MMF optical link. Transmit and receive circuits and their results are outlined in Section III. The transceiver measurements are shown in Section IV followed by the conclusion in Section V. II. OPTICAL LINK ANALYSIS In this section, we will analyze the components of a typical optical link (Fig. 1) and their impact on the link budget. It will be shown that it is essential to include transmitter nonidealities, interchannel crosstalk, and intersymbol interference (ISI)

as power penalties in addition to the obvious loss terms to accurately predict the link margin and derive the driver and receiver specifications. VCSELs have become the lasers of choice for optical interconnects owing to their low power consumption, high modulation bandwidth, high uniformity, and manufacturing advantages. Since they are surface emitting, high-volume production in two-dimensional arrays and wafer-level testing are amenable. The 10 Gb/s MM VCSELs used in this work emit 2.5 to 3 dBm average optical power at a direct DC current of 7 mA [15]. This DC current results from optimizing bandwidth and power consumption. Low required modulation currents of VCSELs allow small CMOS driver circuits to be used and therefore offer a significant advantage over edge-emitting lasers. However, the bit error rate (BER) of VCSELs is limited by a high relative intensity noise (RIN), a large nonlinearity, and signal peaking of more than 3 dB due to the electrooptical conversion. of 0.4–0.6 A/W at an A p-i-n PD achieves a responsivity optical wavelength of 850 nm and 0.9 A/W at 1550 nm [16]. The responsivity is defined as (1) where denotes the average optical power incident to the the average PD current. III/Vactive area of the PD and material-based PDs are preferred over silicon (Si) PDs due to the higher responsivity and larger bandwidth. For the optical channel, four prime candidates are discussed: single-mode fiber (SMF), MMF, plastic optical fiber (POF), and MM polymer waveguides in or on printed circuit boards (PCB). A performance comparison of the four different optical channels in terms of dispersion, insertion, and coupling losses as well as the numerical apertures (NA) at optical wavelengths of 850 and 1550 nm is given in Table III [17]–[19]. Besides simple attenuation of the transmitted signal, various dispersion phenomena affect the ability of the signal to recover because of optical pulse broadening, which leads to ISI [20]. SMFs feature the lowest attenuation and the largest bandwidthlength product. However, they suffer from a high coupling loss from MM VCSELs owing to their small NA and core size. MMF is the best choice in terms of VCSEL and PD coupling efficiency [17], but its performance is limited by intermodal dispersion, which is caused by the fact that the optical pulse splits into several paths (modes) in the fiber. The graded index MMFs with a core diameter of 62.5 m, used for the transceiver, feature approximately 500 modes. Even though dispersion can be compensated for in the optical domain, applying electrical equalization can be of lower cost and complexity as well as more compact. Decision feedback equalization (DFE) has been successfully applied for electrical communication systems and can also be used to extend the optical MMF bandwidth-length product of a link [20]. With a 500 MHz km MMF, a link distance of 50 m can be reached at 10 Gb/s without equalization. By using special high-bandwidth MMF (Table III), a distance extension of up to a factor of four can be achieved. In addition to this bandwidth-length limitation, the overall link performance also depends on the VCSEL nonidealities,

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TABLE III PERFORMANCE COMPARISON OF DIFFERENT OPTICAL CHANNELS

coupling and channel loss, channel crosstalk, ISI due to DC rejection, and receiver noise. In the system analysis, the relevant channel losses are considered as absolute power losses and the performance degrading effects as power penalties. For 50 m of the MMF used in this work, the coupling and channel losses, listed in Table III, amount to 4.3 dB and attenuate the 2.5 dBm average optical power of the VCSEL to 1.8 dBm incident to the active area of the PD. Nonidealities of the VCSEL are finite extinction ratio (ER), RIN, and timing jitter due to laser nonlinearity. For the subsequent calculations, it is assumed that the receiver is thermal-noise-limited as shown in the receiver calculations (Section III-C). The ER is the ratio of the upper and lower transmitted power levels for 2-pulse-amplitude modulation (2-PAM), nonreturn-to-zero (NRZ) signaling, and its power can be expressed as [21] penalty (2) where the for 2-PAM is 6 dB, according to the Optical Internetworking Forum (OIF) VSR-3 standard. The power penalty is [22]–[24]

TABLE IV OPTICAL LINK PERFORMANCE ANALYSIS FOR 2-PAM

the deviation from the crossing point, and the total number of jitter curves. Crosstalk between high-density transceiver channels can be a serious problem in link systems. The reduction in eye-closure due to electrical and optical crosstalk from adjacent channels is in the link accounted for as a crosstalk power penalty budget [24]: (7)

(3) dB/Hz [15], where the worst-case GHz denotes the effective bandwidth, and reprecorresponds to a BER sents the signal-to-noise ratio. . The expression for the VCSEL timing jitter power of penalty is approximated by [22]–[24] (4) where (5) and (6) Parameter denotes the data rate, the root mean square (rms) the mean crossing point in UI, unit interval (UI) jitter,

where denotes the crosstalk power loss of channel to is the total number of adjacent the channel considered and channels. It is assumed that all channels have equal signal power levels. In most cases, it is sufficient to consider the crosstalk contribution by the two closest adjacent channels. The optical components specify an adjacent channel isolation of 40 dB. of 20 dB and 30 dB of the two adjacent chanFor an is 0.1 and nels to the channel in the middle of an array, of the link budget, a 0.01 dB, respectively. For minimal dB , high channel isolation, preferably 30 dB is desired. The results from (2)–(7) are shown in Table IV. To reduce the VCSEL turn-on delay, the optical power is never switched off completely in the transmitter, resulting in an inherent DC offset in the receiver. This would lead to signal saturation at the supply rails. Therefore, a DC offset compensation network (DOC) is required. The high-pass filtering of the transmitted data leads to ISI, which increases the BER and degrades the performance. This can be expressed as an ISI power dependent on the high-pass cut-off frequency penalty to bit rate frequency ratio: . Here, , and denotes 1-bit duration. For pseudo-random bit sequence and , to maintain a BER (PRBS) of , the yields 0.1 dB [25], and by introducing

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Fig. 2. Block diagram of the complete 4 10 Gb/s high-density fiber-optic link system. The laser diodes are forward biased by a supply voltage VFB, typically 2.4 V. The p-i-n PDs need to be reverse biased by a supply voltage VRB, typically 2.4 V.

8B10B DC-free coding [26], the is further reduced , DC-free to 0.03 dB [25]. Consequently, for line coding is not required, simplifying the link scheme and reducing the power consumption. Thus, for a bit rate of 10 Gb/s, the cut-off frequency is required to be lower than 10 MHz. 5.1 dBm is needed In conclusion, a receiver sensitivity of for 10 Gb/s 2-PAM data transmission and a BER . A mandatory link margin of up to 5 dB [24] translates into a required receiver sensitivity of 10.1 dBm. III. TRANSCEIVER TOPOLOGY A. Transceiver Array Topology Four VCSEL drivers and four receivers in a 250- m pitch array configuration are implemented in IBM’s standard CU-08 10M CMOS process and with a nominal transistor gate length of 80 nm. They are connected to the optical devices and PCBs by bond wires (Fig. 2). As the bond pad space does not suffice to provide each driver or receiver with a separate supply, all drivers and all receivers share the same chip supply. This, however, can decrease the channel isolation by signal coupling through the supply. As a precaution, all circuits are differential for best common mode rejection, and the empty chip space is filled with bypass capacitors. Short bond wires are desired for a flat frequency response and minimal crosstalk. Each receiver is isolated by a 15- m-wide ring of high-resistive substrate to reduce parasitic substrate coupling to radio frequency (RF) signal paths further. B. Transmitter Circuits and Results The requirements for the driver electronics are as follows: to supply the VCSEL with 7 mA DC and a modulation current of 7.5 mA, while maintaining a large overall bandwidth of 6.5 GHz and reducing the timing jitter of the VCSEL, a low power consumption, a small chip area, and a low input capacitance. A low input capacitance is required to enable the core chip to drive this transmitter. The combination of a pre-driver and a

Fig. 3. Schematic of a transmit channel. Next to the transistor references, the gate width and length are indicated in parentheses.

main driver chosen meets these requirements (Fig. 3). The predriver isolates the large capacitance of 0.74 pF of the VCSEL. Peaking inductors with a series inductance of 0.8 nH and a series m m occupying two resistance of 25 on an area of levels of metals have been used to optimize power consumption and bandwidth. The main driver is a combination of a commonsource (CS) and a source-follower (SF) amplifier topology. The CS stage provides voltage gain and the SF transistor yields a low output impedance. The purpose of low-threshold-voltage (LVT) and high-threshold-voltage (HVT) transistors is explained in Section III-C. This main driver topology offers four advantages. First, an efficient differential-to-single-ended conversion is provided for single-ended optical channels. Second, the voltage gain of the main driver can be set to 1, compared with an SF solution with a voltage gain always 1. This is important because the VCSEL requires at least an output modulation voltage of 0.47

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Fig. 4. Simulated optical eye-diagram of the transmitter at the output of the VCSEL at 10 Gb/s with (a) a conventional CS output stage and (b) using the proposed CS-SF output driver.

Fig. 6. Photograph of the quad transmitter with the VCSEL array placed and bonded onto a PCB. TABLE V TYPICAL KEY PERFORMANCE PARAMETERS OF ONE TRANSMIT CHANNEL

Fig. 5. Optical eye-diagram at the output of the VCSEL after 6 dB of 1. The average optical power is 2.5 dBm attenuation at 10 Gb/s, PRBS 2 and the ER amounts to 6 dB. The dotted lines are measurements and the solid lines are simulations.

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for an optical of 6 dB and an average optical power of 2.5 dBm. Third, the power consumption is lower than that of a conventional CS topology with a 60- load resistance because provides the same output impedance at a three times SF lower current. The lower current requirement allows smaller devices to be used. Fourth, the driver compensates the asymmetric edges of the emitted optical VCSEL pulse and therefore reduces its timing jitter. The VCSEL produces a fast rising and a slowly falling signal pulse edge because of the electrooptical conversion. A pulse applied to the differential inputs of the pre-driver in Fig. 3 generates a fast rising edge at the node and is propagated to the circuit output . A steeply rising turns the VCSEL off rapidly, providing pre-emedge at phasis to the slow falling edge of the VCSEL and, as a consequence, producing also a fast falling optical signal edge. In Fig. 4(a), an eye-diagram simulation at 10 Gb/s of a transmitter with a conventional CS main driver stage is displayed and yields rise and fall times of 28 and 112 ps, respectively. Both rise and fall times are measured within a window of 20% to 80% of the signal amplitude in the eye-diagram. The same simulation is applied to the proposed driver in Fig. 3, and the resulting eye-diagram is shown in Fig. 4(b). Significantly lower rise and fall times of 30 and 38 ps, respectively, are achieved. Consequently, a reduced timing jitter by 20%–30%, compared with that of a driver without pre-emphasis, results. The measured and overlapped simulated optical

eye-diagram of the implemented transmitter at 10 Gb/s, PRBS , is shown in Fig. 5. In all transmitter simulations, a largesignal dynamic VCSEL model [27] is included. Simulation and measurement exhibit excellent agreement. One transmitter consumes 2 mW from a 0.8-V supply and 16.8 mW from a 2.4-V supply including the VCSEL. The micrograph of the fabricated quad transmitter is shown in Fig. 6. m m and the A single driver uses a chip area of m m. The channel pitch driver array chip occupies is 250 m, which is determined by the VCSEL array and is a typical value in high-density optical links to date. The key performance parameters of one transmit channel are summarized in Table V. C. Receiver Circuits and Results A detailed receiver block diagram is shown in Fig. 7. The transimpedance amplifier (TIA) converts into an amplified voltage. As explained in the link analysis, a DOC is required. It was added at the output of the TIA. For best suppression of injected noise and power supply variations and for a differential optical application, a replica TIA is implemented for each channel. Four limiting amplifiers (LAs) further amplify the signal to regenerate digital ones and zeros. A 50- output buffer has been included for compliance with the test and measurement equipment. Based on the link analysis, the electrical specifications for the receiver are derived in the subsequent section. The photo-

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Fig. 7.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

Block diagram of a receiver channel with the PD and bond wires.

receiver sensitivity that considers only bit errors due to device noise can be expressed as [24] (8) stands for the minimum optical power averaged where over time that is needed to achieve a given signal-to-noise-ratio for NRZ data. for a BER . denotes the effective receiver bandwidth the PD responsivity and over which the total input-referred receiver noise current specis integrated as tral density (9) consists of input-referred amplifier noise shot-noise:

, and PD (10)

where C is the electron charge. The noise sources in a broadband CMOS receiver consist of thermal channel and induced gate noise. The total differential transimpedance gain of the receiver in case of a single-ended optical channel is expressed as (11) where denotes the peak-to-peak differential output the peak-to-peak photo voltage of the receiver and current given by (12) The transimpedance gain is sufficient if a minimum optical input signal at a certain BER can be restored to digital levels. By inserting (12) into (11) and using (1), the minimum required transimpedance gain results: (13) The dominant pole of the receiver is formed by the large depletogether with the input capacition capacitance of the PD and the input resistance tance of the electrical receiver of the receiver. Thus, the maximum input resistance of the receiver is given by (14)

Fig. 8. Single-ended circuit schematic of the implemented TIA with DC-offset compensation.

For a required receiver sensitivity of 10 dBm (Section II), a , a total input peak-to-peak differential output voltage of 0.5 and capacitance of 330 fF, and 10 Gb/s signaling, yield 78 dB and 48 , respectively. A responsivity of 0.5 A/W and an dB are assumed. A lower input resistance comes at the cost of a lower transimpedance gain and a higher transimpedance gain consumes more power because more amplifier stages are required. The circuit blocks in Fig. 7 are shown and outlined with measurement results in more detail in the following paragraphs. Based on the specifications for the receiver, the requirements for a short-distance optical interconnect TIA at 10 Gb/s NRZ signaling are a high transimpedance gain, low input impedance, small area, and low power consumption (Table I), whereas minimum input-referred noise currents are less important owing to the high incident optical power (Table IV). The single-ended TIA implemented in [28] is chosen as a basis for this design (Fig. 8). The TIA topology is a modified regulated cascode, where the . In the conmodification is the insertion of pass transistor is directly ventional regulated cascode [28], circuit node are connected to and two gate-source voltages , which does not allow one to bias these required at node transistors at half the supply voltage, as no headroom would be left for the load admittance . The transistors of this shortchannel digital CMOS technology are optimized for high speed and low power consumption at half the supply voltage. In Fig. 8,

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Fig. 9. Schematic of the OTA used for the DC-offset compensation of the NRZ signal at the output of the TIA.

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according to electromigration rules. The measured inductance yielded a 30% lower value than the field-solver simulation predicted mainly because of the small geometry and large number of metal layers used. Each LA features a small-signal gain of 1.7, a bandwidth of 18 GHz at its own load, and draws a DC current of 0.7 mA from a 1.1-V supply. The 50- output buffer consists of two pre-drivers and one main driver (Fig. 11). The main driver is a combination of an SF and a CS similar to the main driver in Fig. 3, except that here the main driver is fully differential. The advantages of the main driver in Fig. 3 hold for the main driver in Fig. 11 too. The requirement of the main driver to drive a 50- load yields and ) with large widths, which cannot transistors ( be connected directly to the output of the LAs, as otherwise the receiver bandwidth would be reduced significantly. Thus, pre-drivers are inserted to step down the large input capacitance of the main driver. Both pre-drivers use peaking inductors to optimize bandwidth and power consumption. The first predriver is a conventional differential CS topology. The second pre-driver is divided in two parts with different common-mode require a levels; as in the main driver, the SF transistors higher common-mode voltage at the gate than the CS transistors : (15) (16)

Fig. 10. Schematic of a limiting amplifier.

only one drain-source saturation plus one gate-source voltage is required at node . This allows all transistors to be biased at close to half the supply voltage, resulting in a superior bandwidth-gain product. The single-ended TIA features a transimpedance gain of 61.1 dB , a bandwidth of 7 GHz, and draws a DC current of 1.3 mA from a 1.1-V supply. An operational transconductance amplifier (OTA) in conjuncis added to cancel tion with a compensation capacitor the DC offset of the signal path. The difference between the and the common-mode reference output voltage of the TIA adjusts the DC current source of the TIA voltage after a low-pass filter. The OTA is a two-stage folded cascode [29] with common-mode feedback (Fig. 9). The DOC high-pass filters the transmitted data, which leads to ISI, as mentioned in MHz. The the link analysis. For a bit rate of 10 Gb/s, of the DOC in Fig. 8 is equal to the unity-gain frequency of the open-loop transfer function. This, on a first order, depends in the OTA and . The on the transconductance of transconductance is strongly process dependent; consequently, , to achieve sufficient margin on process variations and was chosen to be 1 MHz by design. All limiting amplifiers have the same differential CS topology (Fig. 10). Peaking inductors are added to increase the bandwidth. The peaking inductors feature a measured series inductance and resistance of 1.35 nH and 106 , respectively. They m occupy four metal layers in series, consume an area of m only, and can handle a maximum DC current of 400 A,

denotes the gate-to-ground or common-mode voltage, the gate-source voltage, and the drain–source saturation . The difference between and is voltage of transistor and amounts to approximately 300 mV. In this equal to short-channel CMOS technology, the transistors were highly optimized for digital applications and therefore yield an optimal bandwidth power consumption ratio at input-output bias voltages in the range of 0.5 to 0.6 V, which corresponds to half and the supply voltage. Shifting the common mode of 300 mV apart would make it difficult to maintain a sufficient and voltage gain in the second pre-driver stage with in saturation for large signals. Therefore, HVT and keep LVT field-effect transistors (FETs) are introduced for and , respectively. This has several advantages. First, the of the HVT FETs extends the saturareduced tion region of the transistor for large signal operation. Second, also allows a reduction of the difference bethe smaller and . Consequently, a voltage gain 1 in the tween is achieved. Third, the LVT FETs amplifier stage with enable an output common mode of typically 400 mV, which helps to relax the constraint for large-signal operation further. The higher common mode in the yields low load resistances that are amplifier stage with and maintain well suited to drive the large SF transistors the required bandwidth of 10 GHz. Three sets of measurements were carried out to evaluate the performance of one receiver channel: high-frequency S-parameter and noise figure, and low-frequency power-gain measurements. From the set of S-parameters, the transimpedance gain and phase as well as the input and output impedance can be calculated and are displayed in conjunction with simulations in Figs. 12–15, respectively.

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Fig. 11.

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Schematic of the three-stage 50- output buffer for an AC-coupled load.

Fig. 14. Comparison of simulated versus measured single-ended input impedance of the designed receiver. Fig. 12. Simulated and measured electrical differential transimpedance gain of the designed receiver.

Fig. 15. Simulated and measured single-ended output impedance of the implemented buffer and receiver. Fig. 13. Simulated and measured transimpedance phase. The group delay amounts to 105 ps and the group delay ripple is smaller than 25 ps for frequencies up to 10 GHz.

The measurements of the receiver show a transimpedance gain of 80.1 dB, a bandwidth of 6.4 GHz, an input impedance of 42 , and a high-pass cut-off frequency of 800 kHz. In the simulations, extracted parasitic capacitances are included. Simulations and measurements show good agreement, considering the large number of amplifier stages in the receiver implemented. The low-frequency power-gain measurement is performed to test the DC-offset compensation of the receiver and is displayed in Fig. 16. To predict the noise properties of a receiver, accurate FET noise models are required. Often, the FET noise models provided by the foundry do not account for short channel effects properly. Therefore, an RF noise model needs to be generated,

e.g., the van der Ziel [30] model, shown in Fig. 17. The correand the induced gate thermal noise lation between the drain current spectral density is given by (17) The parameters , , and denote the drain, gate, and cross stands for the correlation noise coefficients, respectively. absolute temperature and for the Boltzmann constant. represents the gate-oxide capacitance and the drain-source conductance at zero drain bias of the transistor. The need for an accurate RF noise model is outlined using the example of the receiver noise figure in a 50- system in Fig. 18. A typical foundry provided noise model for the used digital CMOS process yields a simulated noise figure of 7.3 dB at 5 GHz, 5.4 dB off from measurements. For frequencies higher than 5 GHz, the mismatch is even larger.

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TABLE VI EXTRACTED NOISE COEFFICIENTS OF AN 80 nm NFET

Fig. 16. Measurement of the low-frequency power gain of the receiver designed. The DC is rejected by more than 60 dB. The high-pass 3 dB cut-off frequency is at 800 kHz.

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Fig. 17.

Van der Ziel noise model of a FET.

Fig. 19. Photograph of the quad receiver with the PD array placed and bonded onto a PCB. Fig. 18. Comparison of measured versus two sets of simulated noise figures of the receiver implemented. The dotted line presents a simulation with extracted van der Ziel FET noise models. The dashed line shows a simulation with foundry-provided FET noise models.

To generate the van der Ziel noise model, the noise coefficients need to be extracted. This was accomplished using the method described in [31]. The extracted noise coefficients for a high-performance NFET with a gate length of 80 nm, biased at half the supply voltage, are displayed in Table VI. Compared with a long-channel FET, the measured 80-nm FET yields higher values for and by a factor of 2 and 3.5, respectively. However, turns out to be smaller by a factor of 2.7 than the long-channel value. With these extracted noise coefficients, the measured and simulated receiver NF deviates by less than 1.5 dB up to 10 GHz (Fig. 18). From the measured NF, the rms input-referred noise current spectral density yields 32 pA Hz. Applying (8) results a theoretical receiver sensitivity of 13.5 dBm incident to the active area of the PD for a , and a PD responsivity bandwidth of 10 GHz, a BER of 0.5 A/W. Inserting the maximum optical power incident to the PD of 1.8 dBm (Table IV) into (1) and using (10) yields a maximum rms shot-noise current spectral density of 10.3 pA Hz. The input-referred rms amplifier noise current spectral density is by a factor of three larger than the maximum input-referred rms shot-noise current spectral density. It can therefore be stated that the receiver is thermal noise limited. The transimpedance and limiting amplifiers consume 6 mW, and the 50- output buffer draws 10 mW from a 1.1-V supply per channel. A micrograph of the PD and fabricated receiver array chips is shown in Fig. 19.

TABLE VII TYPICAL KEY PERFORMANCE PARAMETERS OF ONE RECEIVE CHANNEL

A receiver without buffer uses m m, and the quad m m. The channel CMOS receiver chip occupies pitch is 250 m. Typical key performance parameters of one receiver channel are summarized in Table VII. An excellent agreement between measurement and simulation is demonstrated. IV. TRANSCEIVER MEASUREMENTS For the performance evaluation of the complete transceiver, the optical measurement set-up displayed in Fig. 20 was installed. On the transmit side, the VCSEL launches an optical nm, which is collimated and focused onto an beam at MMF with a core diameter of 62.5 m by a lens and a microscope objective, respectively. On the receive side, the light beam from the MMF is first collimated and then focused onto the PD by two lenses. This setup allows , , and adjustments within m. The optical power was controlled by an optical attenuator, which was inserted between the two lenses on the receiver side.

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Fig. 21. Electrical eye-diagram at the output of the receiver at 10 Gb/s, PRBS 2 1, and after 5m of MMF.

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TABLE VIII TYPICAL KEY PERFORMANCE PARAMETERS OF THE QUAD TRANSCEIVER

Fig. 20. Block diagram of the optical measurement setup of one transceiver channel. All lenses have a diameter of 1 inch and are plano-convex (f denotes the focal length).

Transmit and receive chips were mounted on substrate PCBs for testability. Both PCBs have two metal layers: the top layer carries the chips and metal traces and the bottom layer consists of a solid ground plane. Both metal layers consist of 8- m copper (Cu), plated with 4–5 m of bond gold, which contains 4- m Ni and 1- m gold (Au). This results in a total metal thickness of 12 to 13 m. The substrate material is polyimide with a thickness of 1 mil (25.4 m) and a relative dielectric constant of approximately 3.0 at 10 GHz. For a single-ended trace with a characteristic impedance of 50 , the metal trace width yields 44 m. For differential traces with a differential characteristic impedance of 100 , the widths and separation are 40 and 55 m, respectively. This low substrate height was chosen to achieve thin microstrip traces and subsequently bring the microstrip traces close to the transmitter and receiver chips. Consequently, the bond wires can be kept short, which is critical for maintaining a flat frequency response and reducing crosstalk between neighboring channels. Three sets of measurements were performed: small-signal channel isolation, large-signal eye-diagram, and BER measurements. The measured crosstalk between neighboring transceiver channels including the bond wires and the optics is less than 30 dB, which is sufficient for 2-PAM signaling as seen in Section II. Clear open eyes at 10 Gb/s at the output of the transceiver are achieved and displayed in Fig. 21. In the transceiver configuration shown in Fig. 20, with 5m of MMF and a variable optical attenuator, optical receiver sensitivities of 10 and 7 dBm at 5 and 10 Gb/s, respectively, and a PD responsivity of are measured at a BER 0.5 A/W. This results in link budgets of 12.5 and 9.5 dB at 5 and 10 Gb/s, respectively, and at a VCSEL launch power of 2.5 dBm. Subtracting the maximum optical power incident to the PD of 1.8 dBm (Table IV) from the measured sensitivity yields a link margin of 5.2 dB at 10 Gb/s. The receiver sensitivity with an ideal transmitter can be calculated by adding the power penalties to the measured sensitivity. A power penalty of 3.3 dB is caused by the transmitter (Table IV). An ISI penalty of 2.2 dB needs to be added due to bandwidth-limited PCB traces and connectors, which cause a 40% vertical eye-closure (Fig. 21). The

total jitter at the output of the transceiver (Fig. 21) amounts to 0.08 UI, which translates to a penalty of 0.9 dB. A penalty of 0.3 dB has already been accounted for in the transmitter, resulting in an additional transmission and receiver jitter penalty of 0.6 dB. For 10 Gb/s, this results in a sensitivity of 13.1 dBm, which shows excellent agreement with the theoretical receiver sensitivity calculation of 13.5 dBm. The total power consumption of the quad transceiver amounts to 100 mW, including the VCSELs and excluding the 50- output buffers. This results in an FOM of 2.5 mW/(Gb/s), leaving a sufficient power consumption budget for a CDR and MMF equalizer. Typical key performance parameters of the quad transceiver are summarized in Table VIII. V. CONCLUSION Transceivers with a power consumption per data rate of less than 10 mW/(Gb/s) are needed to meet the terabit per second bandwidth requirement and limited system power consumption of future backplanes and chip-to-chip communication systems. This work has presented a transceiver array that features a power consumption per data rate that is one order of magnitude lower than the best results published to date. In addition, the authors have, for the first time, demonstrated a high serial data rate of 10 Gb/s in an 80-nm digital CMOS process. This serial data rate is by a factor of four higher than the highest rate published for CMOS transceiver arrays to date. In order to achieve this small power consumption and high data rate, efficient and accurate models for the optical components and the transistor noise are required. Based on these models, a detailed optical link analysis, which takes relevant system impairments into account, can be performed. The link analysis accurately predicts the achievable link margin and derives the specifications for transmit and

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receive circuits. Conventional analog circuits need to be enhanced to achieve low power consumption per data rate at a low supply voltage of 1.1 V. In summary, this work showed that inexpensive optical technology combined with CMOS offers a low-power extension of the limited link distance of 10 Gb/s electrical links with outstanding performance. ACKNOWLEDGMENT The authors gratefully acknowledge P. Dill from IBM Research, Rüschlikon, Switzerland, for designing the PCBs, M. Lanz from ETH Zurich, Switzerland, for bonding the chips, S. Hunziker of Avalon Photonics for supplying the VCSELs, Albis Electronics for supplying the PDs, B. Jagannathan from IBM, East Fishkill, NY, for helpful discussions, and the IBM foundry team in Burlington, VT, for manufacturing the CMOS chips. REFERENCES [1] G. Moore, “Cramming more components onto integrated circuits,” Electronics, vol. 38, no. 8, pp. 114–117, Apr. 19, 1965. [2] W. J. Dally and J. W. Poulton, Digital Systems Engineering. Cambridge, U.K.: Cambridge Univ. Press, 1998, pp. 19–20. [3] The International Technology Roadmap for Semiconductors (2004). http://www.itrs.org [Online] [4] K. K. Chang, J. Wei, C. Huang, S. Li, K. Donnelly, M. Horowitz, Y. Li, and S. Sidiropoulos, “A 0.4–4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs,” IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 747–754, May 2003. [5] H. Takauchi, H. Tamura, S. Matsubara, M. Kibune, Y. Doi, T. Chiba, H. Anbutsu, H. Yamaguchi, T. Mori, M. Takatsu, K. Gotoh, T. Sakai, and T. Yamamura, “A CMOS multi-channel 10 Gb/s transceiver,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, Feb. 2003, pp. 72–73. [6] H. Higashi, S. Masaki, M. Kibune, S. Matsubara, T. Chiba, Y. Doi, H. Yamaguchi, H. Takauchi, H. Ishida, K. Gotoh, and H. Tamura, “5–6.4 Gbps 12 channel transceiver with pre-emphasis and equalizer,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 18, 2004, pp. 130–133. [7] Y. Moon, Y. Park, N. Kim, G. Ahn, H. J. Shin, and D. Jeong, “A quad 0.6–3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link,” IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 795–803, May 2004. [8] F. E. Kiamilev and A. V. Krishnamoorthy, “A high-speed 32-channel CMOS VCSEL driver with built-in self-test and clock generation circuitry,” IEEE J. Sel. Topics Quantum Electron., vol. 5, no. 2, pp. 287–295, Mar./Apr. 1999. [9] V. M. Hietala, C. Chun, J. Laskar, K. D. Choquette, K. M. Geib, A. 8 photoreceiver A. Allerman, and J. J. Hindi, “Two-dimensional 8 array and VCSEL drivers for high-throughput optical data links,” IEEE J. Solid-State Circuits, vol. 36, no. 9, pp. 1297–1302, Sep. 2001. [10] M. B. Venditti, E. Laprise, J. Faucher, P.-O. Laprise, J. Eduardo, A. Lugo, and D. V. Plant, “Design and test of an optoelectronic-VLSI chip with 540-element receiver-transmitter arrays using differential optical signaling,” IEEE J. Sel. Topics Quantum Electron., vol. 9, no. 2, pp. 361–379, Mar./Apr. 2003. [11] J. Ahadian, M. Englekirk, M. Wong, T. Li, R. Hagan, R. Pommer, and C. Kuznia, “A quad 2.7 Gb/s parallel optical transceiver,” in Proc. IEEE Radio Frequency Integrated Circuits Symp., Fort Worth, TX, Jun. 2004, pp. 13–16. [12] J. Simon, L. Windover, S. Rosenau, K. Giboney, B. Law, G. Flower, L. Mirkarimi, A. Grot, C.-K. Lin, A. Tandon, G. Rankin, R. Gruhlke, and D. Dolfi, “Parallel optical interconnect at 10 Gb/s per channel,” in Proc. IEEE Electronic Components and Technology Conf., Las Vegas, NV, 2004, pp. 1016–1023. [13] P. Gui, F. E. Kiamilev, X. Q. Wang, X. L. Wang, M. J. McFadden, M. W. Haney, and C. Kuznia, “A 2-Gb/s 0.5-m CMOS parallel optical transceiver with fast power-on capability,” J. Lightwave Technol., vol. 22, no. 9, pp. 2135–2148, Sep. 2004.

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[14] D. M. Kuchta, Y. Kwark, C. Schuster, C. Baks, C. Haymes, J. Schaub, P. Pepeljugoski, L. Shan, R. John, D. Kucharski, D. Rogers, M. Ritter, J. Jewell, L. Graham, K. Schrödinger, A. Schild, and H.-M. Rein, “120Gb/s VCSEL-based parallel-optical interconnect and custom 120-Gb/s testing station,” J. Lightwave Technol., vol. 22, no. 9, pp. 2200–2212, Sep. 2004. [15] D. Vez, S. Eitel, S. G. Hunziker, G. Knight, M. Moser, R. Hoevel, H.-P. Gauggel, M. Brunner, A. Hold, and K. H. Gulden, “10 Gbit/s VCSEL’s for datacom: devices and applications,” Proc. SPIE, vol. 4942, p. 2943, 2002. [16] H. Kressel, Semiconductor Devices for Optical Communication. Berlin, Germany: Springer-Verlag, 1980. [17] E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J., vol. 8, no. 2, pp. 115–128, May 2004. [18] J. Moisel, J. Guttmann, H.-P. Huber, O. Krumpholz, and M. Rode, “Optical backplanes with integrated polymer waveguides,” Proc. SPIE, vol. 39, no. 3, pp. 673–679, Mar. 2000. [19] Plastic Optical Fiber Trade Organization (POFTO), “Present State-ofthe-Art of Plastic Optical Fiber (POF) Components and Systems,” Information Gatekeepers, Inc., Brighton, MA, 2004. [20] P. Kirkpatrick, W.-C. Fang, H. Johansen, B. Christensen, J. Hanberg, M. Lobel, T. Mader, S. Shang, C. Schulz, D. Sprock, and M. Verdiell, “10 Gb/s optical transceivers: Fundamentals and emerging technologies,” Intel Technol. J., vol. 8, no. 2, pp. 83–100, May 2004. [21] G. Keiser, Optical Fiber Communication. New York: McGraw-Hill, 1991. [22] J. T. Verdeyen, Laser Electronics, 3rd ed. Englewood Cliffs, NJ: Prentice-Hall, 1995. [23] A. Yariv, Optical Electronics in Modern Communication, 5th ed. New York: Oxford Univ. Press, 1997. [24] G. P. Agrawal, Fiber-Optic Communication Systems, 2nd ed. New York: Wiley, 1992. [25] S. Han and M.-S. Lee, “Burst-mode penalty of AC-coupled optical receivers optimized for 8B/10B line code,” IEEE Photon. Technol. Lett., vol. 16, no. 7, pp. 1724–1726, Jul. 2004. [26] A. X. Widmer and P. A. Franaszek, “A DC-balanced, partitioned-block, 8B/10B transmission code,” IBM J. Res. Develop., vol. 27, no. 5, pp. 440–451, Sep. 1983. [27] G. Sialm, D. Erni, D. Vez, G.-L. Bona, T. Morf, C. Kromer, F. Ellinger, and H. Jäckel, “Trade-offs of VCSEL modeling for the development of driver circuits in short distance optical links,” Opt. Eng., vol. 44, no. 10, pp. 105401-1–105401–15, Oct. 2005. [28] C. Kromer, G. Sialm, T. Morf, M. Schmatz, F. Ellinger, D. Erni, and H. Jäckel, “A low-power 20-GHz 52 dB transimpedance amplifier in 80-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 885–894, Jun. 2004. [29] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997. [30] A. V. D. Ziel, Noise in Solid State Devices and Circuits. New York: Wiley, 1986, ch. 5. [31] C.-H. Chen, M. J. Deen, Y. Cheng, and M. Matloubian, “Extraction of the induced gate noise, channel noise, and their correlation in submicron MOSFET’s from RF noise measurements,” IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2884–2892, Dec. 2001.

Christian Kromer (M’98) received the M.S. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, in 1996, where he is currently working toward the Ph.D. degree. He joined LSI Logic Corporation, Milpitas, CA, in 1997, where he was engaged in PCB design for a QPSK receiver system, IC design for an 8-PSK demodulator, and discrete RF circuit design. In 2001, he started the Ph.D. program at ETH in collaboration with the IBM Zurich Research Laboratory in Rüschlikon. His research interests are high-density optical interconnects and CMOS analog RF circuit design. Mr. Kromer has served as a reviewer for several IEEE journals, including the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, TRANSACTIONS ON CIRCUITS AND SYSTEMS, and MICROWAVE AND WIRELESS COMPONENTS LETTERS.

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Gion Sialm received the M.S. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, in 1995, where he is currently working toward the Ph.D. degree in collaboration with the IBM Zurich Research Laboratory in Rüschlikon. He was employed as IT Manager in a company with worldwide activities, where he built-up the information technology and telecommunication infrastructure. In 2000, he joined the IT Department of ETH, where he both headed and implemented highavailability projects for database and e-mail applications. His research interests include networking, optical interconnects, and CMOS analog RF circuit design.

Christoph Berger received the M.S. degree in physics from the University of Bern, Bern, Switzerland, and the Ph.D. degree from the Institute of Microtechnology, University of Neuchâtel, Neuchâtel, Switzerland, in 1998. From 1998 to 2000, he investigated board-level optical interconnects as a Postdoctoral Researcher with the University of California at San Diego, La Jolla. Since 2001, he has been with the IBM Zurich Research Laboratory, Rüschlikon, Switzerland, where he is part of a multidisciplinary team working on intrasystem parallel optical interconnects.

Thomas Morf (S’89–M’90) was born in Zürich, Switzerland, on April 4, 1961. He received the B.S. degree from Winterthur Polytechnic, Winterthur, Switzerland in 1987, the M.S. degree in electrical engineering from the University of California, Santa Barbara (UCSB), in 1991, and the Ph.D. degree from the Swiss Federal Institute of Technology (ETH), Zürich, Switzerland, in 1996. From 1989 to 1991, he worked as a Research Assistant at UCSB, performing research in the field of active microwave inductors and digital GaAs circuits. In 1991, he joined the ETH. His Ph.D. work was on circuit design and processing for high-speed optical links on GaAs using “epitaxial lift-off” techniques. In 1996, he joined the Electronics Laboratory also at the ETH, where he led a research group in the area of InP-HBT circuit design and technology. Since fall 1999, he has been with the IBM Zurich Research Laboratory in Rüschlikon, Switzerland. His current research interests include all aspects of electrical and optical high-speed high-density interconnects and high-speed and microwave circuit design.

Martin L. Schmatz (S’94–M’97) received the M.S. degree in electrical engineering and the Ph.D. degree from the Swiss Federal Institute of Technology (ETH), Zurich, in 1993 and 1998, respectively, for his work on low-power wireless receiver designs and on noise parameter measurement systems. In 1999, he joined the IBM Zurich Research Laboratory, Rüschlikon, Switzerland, where he established a research group focusing on high-speed and high-density CMOS serial-link systems. Since 2001, he has managed the I/O Link Technology group at IBM Research. He is also the IBM Manager responsible for the joint IBM-ETH Competence Center for Advanced Silicon Electronics (CASE), which allows researchers from ETH to access IBM’s most advanced SiGe and CMOS technologies.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 12, DECEMBER 2005

Frank Ellinger (S’97–M’02) was born in Friedrichshafen, Germany, on 1972. He received the Masters degree in electrical engineering from the University of Ulm, Germany, in 1996, and the M.B.A. and Ph.D. degrees in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zürich, Switzerland, in 2001. A habilitation (post-doctoral) thesis was successfully submitted to ETH in 2004. During his M.B.A. work in 2001, he was with the Wireless Marketing Division of Infineon, Munich, Germany. Since 2001, he has been the Head of the RFIC Design Group of the Electronics Laboratory at the ETH, and Project Leader of the IBM/ETH Center for Advanced Silicon Electronics at IBM Research Rüschlikon. His main interests are the design of radio frequency integrated circuits (RFICs) for high-speed wireless and optical communication. Since 2002, he has been a Lecturer at the ETH. In 2003, he was Program Chair of WOCSDICE. As first author, he published over 40 refereed papers, most of them IEEE journal contributions, and three patents. Dr. Ellinger received several awards for his works, e.g., the Rohde&Schwarz/Agilent/Gerotron EEEfCOM innovation award, the SEV Denzler Award, the ETH Medal, and the Young Ph.D. Award of the ETH (Bonus 29). He received the Venia Legendi (university teaching degree) in high-frequency circuit design from the ETH in 2005.

Daniel Erni (S’88–M’93) was born in Lugano, Switzerland, on 1961. He received the El.-Ing. HTL degree in electrical engineering from Interkantonales Technikum Rapperswil HTL in 1986, the Dipl. El.-Ing. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zürich, Switzerland, in 1990, and the Ph.D. degree in 1996 for the investigation of nonperiodic waveguide gratings and nonperiodic coupled cavity laser concepts. Since 1990, he has been working at the Laboratory for Electromagnetic Fields and Microwave Electronics, ETH, on nonlinear wave propagation, laser diode modeling [multisection distributed feedback (DFB) and distributed Bragg reflector (DBR) lasers, VCSELs], computational electromagnetics, and on the design of nonperiodic optical waveguide gratings, e.g., by means of evolutionary algorithms. His current research interests include highly multimode (MM) optical signal transmission in optical interconnects (i.e., in optical backplanes with extremely large waveguide cross sections) as well as alternative waveguiding concepts for dense integrated optical devices like, e.g., photonic crystal devices, couplers, and wavelength division multiplexing (WDM) filter structures. Dr. Erni has been awarded the 2000 Outstanding Journal Paper Award by the Applied Computational Electromagnetics Society for a contribution on the application of evolutionary optimization algorithms in computational optics in 2001. He is the head of the Communication Photonics Group at ETH Zurich. He is a Member of the Swiss Physical Society, the German Physical Society, and the Optical Society of America.

Gian-Luca Bona received the Ph.D. degree in physics from the Swiss Federal Institute of Technology (ETH), Zürich, Switzerland, in 1987, for his investigations on surface magnetic structures by short-pulsed laser excited photo emission. After postdoctoral work at the IBM Zurich Research Laboratory in the area of picosecond optical sampling of ultrafast GaAs-based devices, he became a Research Staff Member in 1988 and was involved in work on quantum-well semiconductor lasers, with emphasis on the design and characterization of high-power and short-wavelength GaAs-based lasers. In 1994, he initiated work on high refractive index contrast SiON/SiO waveguide technology that led to a series of reconfigurable planar lightwave circuits. His current research focuses on photonic activities ranging from single mode adaptive integrated optical filter functions to parallel optical backplane high-speed link applications as well as exploratory high density optical interconnects using novel photonic bandgap concepts. Since mid 2004, he manages the Science and Technology effort in the IBM Almaden Research Center, San Jose, CA.

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Heinz Jäckel (M’82) received the Ph.D. degree from the Department of Electrical Engineering, Swiss Federal Institute of Technology (ETH), Zürich, Switzerland, in 1979. In 1980, he joined IBM, where he held scientific and management positions for 13 years in the research laboratories of IBM in Rüschlikon, Switzerland, and Yorktown Heights, NY. During this time, he carried out research projects in the field of device and circuit design for superconducting Josephson Junction Computers, GaAs-MESFET logic and memory ICs, and optoelectronics. In 1988, he was instrumental in the establishment of the optoelectronic project at IBM, where he subsequently managed the “Optical Storage Devices” activities. He has been full Professor of Analog Electronics at the Electronics Laboratory of ETH Zurich since 1993. The research activities of his “High Speed Electronics and Photonics” group at ETH concentrate on the following topics: technology, design, and characterization of ultrafast transistors (mainly InP-based heterojunction bipolar transistors) and circuits for multi-10 gigabit electronics, IC design of RF circuits for mobile communication, and CMOS ASICs for sensory technology. In the area of lightwave communication the group pursues research on photonic devices and integrated optical circuits for data transmission, particularly InP-based all-optical devices for all-optical signal processing at terabit per second data rates.

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