This paper describes the design methodology and measured performances of a monolithic two- stage RF power amplifier realized in a 0.35pm.
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A 1.9GHZ LOW VOLTAGE CMOS POWER AMPLIFIER FOR MEDIUM POWER RF APPLICATIONS A. Giry, J-M. Fournier’ and M. Pons* STMicroelectronics,Rue Jean Monnet, 38926 Crolles, France *Laborstoired’Electromagnbtisme, MicroOndes et Optoelectronique, BP 257,38016 Grenoble, France *CNETFrance Telecom, BP 98,38243Meylan, France
dimensions combined with the trend towards smaller batteries for modem portable applications leads to make use of low power supply.
ABSTRACT This paper describes the design methodology and measured performances of a monolithic twostage RF power amplifier realized in a 0.35pm CMOS technology. Under 2.5V supply, good linearity is achieved and an output power of 23.5dBm with an associated PAE of 35% is obtained at 19GHz. The obtained performances give an insight ,into CMOS potentialities for medium power RF amplification.
This work proposes an integrated 2-stage RF CMOS power amplifier (PA) operating under low supply voltage and designed for medium power RF applications (250mW). A good trade-off between linearity and efficiency is obtained at 1.9GHz under 2.W. Table 1 allows to compare this work with other recent PA implemented in different technologies and operating around 2GHz.
INTRODUCTION Future WLAN applications (Bluetooth, HomeRadio,.,.) with small coverage radii will require integrated medium power amplifiers at the end of the transmit path. For low cost and highly integrated RF solutions including digital part CMOS seems a promising technology compared to other dedicated technologies (LDMOS, GaAs, Bipolar,...). Some recent works propose efficiency optimized architectures using switched-mode power amplifiers [1] or proper load terminations at the signal harmonics [2]. However, most of modern digital phase modulations with good spectral efficiency present a non-constant envelope and then require the design of RF circuits with high linearity to prevent signal degradation. Efficient but nonlinear power amplifiers are not suitable for such “linear” modulations. The use of linearizing circuits [3] allows to alleviate this issue but at the price of greatest complexity and additional consumption which can be critical in case of low or medium power amplifiers. Furthermore, the device
Table 1
CIRCUIT DESIGN Figure1 shows the schematic of the CMOS PA which is designed to operate from a single 2.W supply. A single-ended 2-stage common source amplifier is used with an integrated reactive matching network between the output stage and the driver stage. A simple design methodology has been adopted for simplicity of design flow in order to
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2000 IEEE Radio Frequency Integrated Circuits Symposium
reduce the design cycle time (no load-pull measurements). As a first step, power density of the 0 . 3 5 ~gate length MOS was estimated from its simulated static I-V curves and then exploited to determine the output transistor size (Ml). Under 2.5V and at ldF3 compression the power density is about 150mW/mm. To deliver 24dBm of output power in a 50i2 load a 1.6mm gate-width transistor is then used for the fmal stage. External RF chokes (27provide DC feed to transistors drains and the output stage is class AB biased (Idq-20%Imax) to get linear operation.
W L ratio of 500cun/0.35pn has been chosen. An integrated inter-stage pi-network provides optimum loading (20Q) at the driver output : inductor L1' (2.5nH) is made using thick ( 2 . 5 ~metal ) 4 level to reduce series resistance and optimize overall efficiency, C1' (4.7pF), C2' (2pF) are MIM capacitors. A reactive network using a bonding and two extemal components (Ll, C3) provides gain matching at the driver input. This architecture allows a 25dB gain at 2GHz with only two stages. To ensure stable operation distinct ground planes and resistive gate bias circuits were employed. Due to the low power supply and resulting low impedance levels, a good knowledge of parasitics and the use of a transistor model which is accurate in the whole bias range is necessary for optimized operation at high frequencies. For MOS simulation, the Philips MM9 model was used and extended to the RF domain by adding extemal resistances at the gate and substrate accesses. Figure 2 shows the "modified" MM9 model used MM9 ff core ))
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Figure 1: Circuit diagram of the CMOS power amplifier
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In order to maximize the power performances of the output transistor a first estimation of the optimum load was made through an analytical study of a simplified model of MOS transistor (quadratic current source model). A bandpass impedance transformation network including the MOS output capacitance and interconnection elements (output bonding, pad capacitance, board traces) is designed to transform the 50Q load into the SQ optimum load that must be presented across the transistor current source for efficiency optimization. In a first version of the PA two extemal capacitance (Cl,C2) have been used in the output network to allow possible tuning. The only one cell pi-network obtained provides narrowband filtering due to the large transformation ratio (50/8) but could be modified to broaden the bandwidth (with a limit given in [5]). Driver stage size is established afier simulation of the last stage power gain. To ensure that the driver stage does not enter saturation before the output stage, a slightly oversized transistor (M2) with a
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Figure 2: MM9 MOS model extended to RF domain
Values of gate and substrate resistances have been evaluated from the transistor layout and resistivity of gate and substrate materials. In order to minimize these resistances and the drain junction capacitance an interdigitated structure was adopted. The unit cell has a total gate periphery of 1OOp.mand is folded in 4 x 2 5 wide ~ gate fingers with substrate contacts on each side. Substrate, source and ground nodes are tied together on chip. Ground bond wires have a very large impact on power performances because they degenerate the transistor and modify
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the load “seen” by its intemal current source. In order to reduce the equivalent inductance of the ground path multibonding was used, giving a minimumestimated inductance of 0.3nH.
power and efficiency as a function of supply voltage is shown in Figure 4.
EXPERIMENTALRESULTS
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A first version of the CMOS PA was tested using chip on board assembly. An input retum loss C-lSdB and a 24.6dB power gain are obtained at 1.9GHz with only 2 stages. Figure 3 shows the measured and simulated output power and poweradded efficiency (PAE) for a one tone signal of 1.9GHz. Under 2.5V operation, the PA exhibits a maximum output power of 23.5dBm and an overall PAE of 35%. The associated drain efficiency of the output stage is 48%. I-m.-Pout
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Figure 4: Measured output power and PAE versus supply voltage
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To evaluate the linearity of the PA, an ACPR measurement was performed on a HP8563E spectrum analyzer with a 1.9GHz d4DQPSK modulated signal based on PDC standard. With this modulated signal, a 22dBm output power is obtained for an ACPR of -5OdBc at SOkHz-offset (Figure 5). An AM/PM phase shift measurement was also made and shows that the maximum phase shift is less than 8’ over the entire input power range.
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Simulations have been performed using HP ADS simulator. By taking into account parasitics associated with bond wires and PCB a good agreement is obtained between measurement and simulation. The equivalent inductances of bond wires and mutual inductances between bond wires were estimated from Grover’s formulas [6,7].
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The large signal frequency response of the PA was also measured and shows that more than 20dBm of output power and 25% of PAE are obtained between 1.8GHz and 2.1GHz. A plot of output
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Figure 5: Measured gain and ACPR@SOkHz-offset with a PDC modulated signal
A microphotograph of the CMOS PA is shown in Figure 6. The chip is fabricated in a 0.35p.m 4-layer-interconnect RF CMOS (high-resistivity subs&&) te&nology of STMicroelectron& and is 0.9x1.2mm2.
REFERENCES K.-C* Tsai and p* Gray, “A le9GHZ lW CMOS Class E Power Amplifier for Wireless Communications”, ESSIRC98, pp.76-79. [2] S.Weber and G. Donig, “An Integrated 2GHz 5OOmW Bipolar Amplifier”, RFIC-97, pp139-142. [3] K Yamamoto and al., “A GaAs RF Transceiver IC for 1.9GHz Digital Mobile Communication Systems”, ISSCC96, ~ ~ 3 4 0 - 3 4 1 . [4] X. Wang and al., “A Low Quiescent Cument, 40% Efficiency Three-Stage PHEMT Power Amplifier MMIC for PCS CDMA Application”, RFIC-99, pp121-124. [5] R. M. Fano, “Theoretical Limitations on the Broadband Matching of Arbitrary Impedances”, Journal of the Franklin Institute, Vol. 249, January 1960, pp57-83, and February 1960, pp139-155.
Figure 6: Die photo
CONCLUSIONS A monolithic RF power amplifier was successhlly realized in 0.35p.m CMOS technology. Under a low power supply of 2.5V an output power of 23.5dBm and an associated PAE of 35% were obtained at 1.9GHi. These performances demonstrate the CMOS potentialities for short range RF applications around 2GHz requiring linear medium power amplification.
ACKNOWLEDGMENT The authors wish to thank Y. Gam& for packaging, P. Geoffroy and S. Abbas for PCB design. They also thank D. Cartalade, D. Pache, I. Telliez, F. Lemaire, J-L. Leclercq, P. Gouagout and J. Bonfiglio for technical assistance and helpful discussions.
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[qH. Patterson, “Analysis of Ground Bond Wire Arrays for RFICs”, RFIC-97, pp237-240. [7] F. W. Grover, Inductance Calculation,New York, Dover Publications, 1962.
