A 2.4GHz WLAN Transceiver with Fully-integrated Highly-linear 1.8V 28.4dBm PA, 34dBm T/R Switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS Y. Tan, J. Duster, C-T. Fu, E. Alpman, A. Balankutty, C. Lee, A. Ravi, S. Pellerano, K. Chandrashekar, H. Kim, B. Carlton, S. Suzuki, M. Shafi, Y. Palaskas, H. Lakdawala Intel Corporation, Hillsboro, OR, USA
[email protected] Abstract A 2.4GHz WLAN transceiver is presented with a fully-integrated highly-linear 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC and 320MS/s ADC (high OSR for relaxed filtering), DPLL and fractional LOG, in 32nm CMOS. For 802.11g 54Mbps, without linearization the TX delivers 19.8dBm at 12.5% efficiency (PA 21.6dBm/19.7% PAE) for -25dB EVM and mask-compliant 22.8dBm/18.5%, while the RX achieves 4.8dB NF, -69dBm sensitivity, and -8dBm IIP3. Introduction Process and packaging constraints unfriendly to RF performance pose a challenge to integrate RF into scaled digital CMOS. This work presents a fully-integrated direct-conversion 2.4GHz WLAN transceiver (Fig.1) in 32nm CMOS, employing high over sampling ratio (OSR) DACs/ADCs to relax filtering, a highly linear 28.4dBm PA [1] co-designed with the LNA’s embedded 34dBm T/R switch [2], and a digital PLL (DPLL) [3] with an inductor-less fractional LO generation (LOG) [4], to achieve highest level of integration. Transceiver Implementation A. Receiver: Co-designed with LNA & PA, T/R switch achieves 34dBm P1dB and 1.3dB loss in TX mode, and 1.1dB loss in RX mode, while providing >32dB isolation and a ESD protection path to LNA through PA transformer secondary center tap ground. The RX LNA is AC-coupled to a 25% duty cycle passive current mode mixer followed by single pole baseband (BBF) and anti-aliasing (AAF) filters, feeding a high dynamic range 320 MS/s ΔΣ ADC. To enhance RX large signal compliance, the LNA and BBF adopt a 1.8 volt power supply; The inductively degenerated LNA uses a push-pull topology that exploits the equal strength of p and n transistors [5] and nested, coupled inductors for input and output matching to achieve low noise figure, high linearity, low power and broadband matching. Minimum length thin gate devices are chosen to maximize fT. To improve receiver dynamic range, 3 coarse gain steps are provided, reducing the current to the mixer in 6dB increments. For quadrature accuracy, the passive double balanced mixer includes a local frequency divider to generate I/Q signals from the 2x channel frequency. The mixer includes digital bias control to maximize gain and linearity, while compensating for process and temperature variations. The equal drive strength p and n transistors are leveraged by the CMOS mixer structure to extend the signal handling capability and minimize switch loss. Scaled 5 bit current-switched DACs are employed for IP2 & DC offset control. The BBF is composed of a high-speed (UGBW=2GHz), two-stage differential op-amp, feedback resistors, and a 978-1-4673-0849-6/12/$31.00 ©2012 IEEE
switchable MOM capacitor bank for programmable (10, 20MHz) baseband bandwidth. A compromise between the amplifier’s flicker noise corner and linearity was chosen to achieve a -74dBm sensitivity level (excluding LO phase noise) while producing a -8dBm IIP3 at the receiver’s maximum gain level. The AAF provides a single far out pole using a folded cascode op-amp with gain boosting for the first stage, a class AB output stage for low output impedance, high swing, and fine gain (-18 to 1dB) control. The RX’s simplified architecture is enabled by the 11-9 bit, 10-40MHz ΔΣ ADC using a digitized integrator (DI) MASH structure that achieves a 67dB SNDR featuring a simplified op-amp based integrator and flash multistage architecture, reconfigurable 2-0/2-2-0 MASH architecture with each modulator implemented as low swing 2nd order feed-forward structure with digital summing. The ADC compensates for finite op-amp gain and uses digitally calibrated source followers for reference buffers. B. Transmitter: The current steering DACs sample at 240MS/s, providing a high dynamic range and high OSR, and an integrated far-out pole to relax the following AAF to a single pole. The DACs employ a segmented 4-bit unary and 6-bit binary architecture for an optimal trade-off between linearity and complexity. The DAC driver has a folded-cascode topology for low-voltage operation, exploiting the process’ equal complementary drive capability to enhance the overall power efficiency. To overcome the limited output impedance of the current sources, boosted cascode transistors are used to enhance gain. The DACs consume 17.6mW, while delivering 410mVpp with 9.5 ENOB in-band and 62dB SFDR up to 120MHz. The active AAFs and out-of-band attenuation in RF section reduce the aliased images to
