A 28 GHz Hybrid PLL in 32 nm SOI CMOS - Semantic Scholar

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 4, APRIL 2014

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A 28 GHz Hybrid PLL in 32 nm SOI CMOS Mark Ferriss, Alexander Rylyakov, José A. Tierno, Member, IEEE, Herschel Ainspan, and Daniel J. Friedman, Member, IEEE

Abstract—A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. In addition to the analog proportional path, the PLL includes a set of digital proportional path controls, so that the two approaches can be experimentally compared. At 28 GHz the RMS jitter is 199 fs (1 MHz to 1 GHz), phase noise is –110 dBc/Hz at 10 MHz offset. The 14 × 160 µm2 32 nm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31 mA from a 1 V supply. Index Terms—DPLL, frequency synthesizers, hybrid PLL, phase locked loop, PLL.

I. INTRODUCTION

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IGH performance digital PLLs have been proposed as alternatives to the conventional charge pump based analog PLL architecture, offering significant advantages in area, manufacturability and programmability. However, several major challenges must be addressed if the full potential of the digital PLL is to be realized. Bang-bang PLLs (BB-PLL) have been demonstrated to be capable of good performance once they achieve phase lock [1]. It should be noted, however, that the hard non-linearity introduced by the 1-bit bang-bang PFD (BB-PFD) severely impacts locking dynamics and noise event response of BB-PLL [2], resulting in relatively slow frequency and phase acquisition times. The former is not problematic in applications where frequency acquisition time is not critical, for example, in wireline I/O communication applications. The slow phase acquisition time, however, in conjunction with the narrow linear range of the BB-PFD, significantly affects the robustness of the BB-PLL to external noise events. For example, if a large phase step is applied to BB-PLL input, the PLL’s recovery time can be extremely slow compared to that of an analog PLL and, furthermore, the locking dynamics can exhibit significant ringing. Unless completely decoupled from external noise events, BB-PLLs can perform poorly in large integrated

Manuscript received August 19, 2013; revised October 24, 2013; accepted December 16, 2013. Date of publication January 23, 2014; date of current version March 24, 2014. This paper was approved by Guest Editor Jeffrey Gealow. This work was supported in part by DARPA under AFRL contract # FA8650-09-C-7924. The views, opinions, and/or findings contained in this presentation are those of the author/presenter and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense. The authors are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10591 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2014.2299273

systems where significant amounts of noise may be present in form of undesirable deterministic tones or even random phase step events which may be coupled to the reference clock through the power supply or substrate. Another important consideration affecting practical applications of BB-PLLs is that the effective small signal gain through the phase detector is a function of noise [2], which complicates the selection of BB-PLL loop gain parameters. The noise performance of the reference clock is typically not known in advance and it can vary from application to application and over time. Time-to-digital converter (TDC) approach partially alleviates the limitations of BB-PLLs, but it should be noted that time resolution of an inverter-based delay line TDC is limited to multiple picoseconds, whereas the phase errors seen at the input of a phase locked I/O-class integer-N PLL are typically at or below the picosecond level. The implementation of sub-ps time-to-digital converters (TDCs) remains an active are of research and state of the art examples require significant analog content in terms of, for example, implicit [3] or explicit [4], [5] capacitive integration. Time amplifiers [6] and stochastic TDCs [7] have also been used to achieve sub-ps resolution, these techniques rely on amplifying and mismatch properties of the manufacturing process; these ADC-related techniques all require a trade off between dynamic range, resolution and complexity. In this work we introduce a high performance 32 nm SOI CMOS LC-tank based integer-N PLL for wireline communication applications, with a control loop implemented using a hybrid of digital and analog PLL techniques. The proposed hybrid PLL maintains the key benefits of the all-digital approach (compact design and CMOS friendly implementation), while at the same time preserving many of the linear phase response characteristics of conventional analog PLLs. The hybrid PLL architecture combines a linear analog proportional path control and bang-bang digital integral path control. The linearity of the proportional path control resolves the noise sensitivity issues of BB-PLLs outlined above and, therefore, makes the hybrid PLL particularly suitable for integration with a multi-channel wireline transceiver as a part of a large system. At the same time, the digital implementation of the integral path keeps the PLL small, programmable and scalable. The proposed architecture is free of the two main challenges facing an analog PLL implementation in a CMOS process optimized for digital applications: there is no need for a large, low leakage capacitor to perform the integrating function of the control loop, and no need for a wide dynamic range, low noise charge pump. Several works have explored different approaches to the problem of partitioning the PLL architecture between analog and digital implementations (see, e.g., [8], [9] or [10]). In this paper, we propose an LC-tank based hybrid PLL architecture,

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Fig. 1. The hybrid PLL architecture contains a simplified analog proportional path and a digital integral path.

in which the proportional path retains its analog characteristics and the integral path is implemented digitally using a bang-bang phase detector. The proportional path of the PLL is greatly simplified as compared to a conventional charge-pump PLL. It should be emphasized that in the proposed architecture the proportional control voltage always operates around its common mode position (when the loop is in phase lock) simply because the integrating function is removed from the analog control path. In addition, a novel implementation of digital control of the VCO is introduced, in which a redundant numbering scheme is used to enable the implementation of the PLL integral path DAC function directly in the VCO. Compared to a binary control scheme, this approach features significantly relaxed matching requirements. At the same time it offers a reduction in layout parasitics, and hence an increase in tuning range, as compared to a thermometer control scheme. The paper is organized as follows. In Section II we will review the implementation of the PLL. In Section III we will review the measurements of the prototype, and finally in Section IV we will conclude. II. ARCHITECTURE OVERVIEW The proposed dual-path hybrid PLL architecture is shown in Fig. 1. The feedback clock is compared to the reference clock by the phase and frequency detector (PFD). The PFD block provides a digital lead/lag signal (LATE) to the integral path and pulse width modulated UP and DWN signals to the proportional path. The PLL’s integral path is implemented digitally, eliminating the need for a large analog loop filter capacitor and benefiting from the strengths of scaled digital CMOS. The lead/lag signal is integrated in the INT block, which provides overflow (INC) and underflow (DEC) results to the redundant number control block and provides a 24-bit control word to the cascaded modulators. The redundant number control block output, along with the filtered output of the path, comprise the integral path oscillator control inputs. The proportional path is implemented in an analog fashion, providing pulsewidth modulated output to an analog varactor as in a traditional charge pump PLL, but with simplifications enabled by the dual-path approach. The feedback divider path includes an initial divide-by-2, followed by a divide-by-8

prescaler that provides the clock for the second , a divide-by-N that creates the feedback clock for the PFD, which is also the clock for both the integrator and the coarse first-stage . VCO band selection, implemented using a separate calibration loop, is enabled by a 4-bit VCO coarse tuning control input. In the proposed design, the PFD must support both the analog proportional and digital integral paths within the PLL. The chosen PFD implementation, shown in Fig. 2, uses a single block to create both sets of required outputs. A benefit of this approach is that it maximizes the sharing between the proportional and integral path phase decision infrastructure, reducing potential phase offset between the two PFD results. The operation of the PFD can be understood in terms of the timing diagram given in the right side of Fig. 2. The reference and feedback clocks drive synchronous set, asynchronous reset flip-flops that directly create the pulsewidth modulated UP and DOWN signals for the analog path, shown in the top portion of the timing diagram for the leading (first transition) and lagging (second transition) cases. In a digital bang-bang-based PLL, the input arbitrator is potentially susceptible to regular metastable events. This susceptibility occurs because the PLL is attempting to drive the input phase error to zero, which results in near simultaneous rising edge times of the inputs to the phase detector. Thus, the outputs of the early/late arbitrator, the first NAND latch in Fig. 2, are passed through a mutual exclusion element (Mutex) to create the metastability-hardened lead-lag decision outputs for the digital integral path, EARLY (first transition) and LATE (second transition) [11]. The function of the Mutex is to prevent propagation of its input signals to its outputs unless a voltage difference between the two inputs of at least one NFET threshold voltage is detected. In this way, the Mutex rejects unresolved logic levels from the first cross coupled NAND latch. It is still possible for metastability to occur in the control logic downstream from the phase detector if the time taken for the BB-PFD to resolve happens to correspond to exactly one period of system clock; however, the likelihood of such an occurrence is significantly less than that of metastabilty in the phase detector itself. The phase detector’s asynchronous reset is created by the Muller C element, which, when all input values match, creates an output that matches its input, else it holds its previous state. The time it takes for the bang-bang

FERRISS et al.: A 28 GHz HYBRID PLL IN 32 nm SOI CMOS

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Fig. 2. The phase detector produces two sets of outputs; one for use in the analog path, and one for use in the proportional path.

portion of the PFD to resolve acts as the reset delay for the analog portion of the PFD. The key observation driving the design of the PLL’s analog proportional path is that the use of the dual-path approach eliminates the need for the proportional path to support a wide frequency tuning range. In particular, once the PLL is locked, because the analog path is only managing proportional path feedback and not long term frequency control as in a conventional single-path analog PLL design (Fig. 3(a)), the proportional path control voltage will remain near the center of its tuning range. If the common mode for the proportional path is set to VDD/2, then the voltage drops for the up and down current sources within the PFD-driven charge pump will match. This observation suggests that the traditional high impedance current sources used in charge pumps can be replaced with switched resistors, resulting in a simpler, more CMOS-friendly implementation with improved flicker noise performance. The resulting proposed proportional path charge pump, with its associated loop filter, is shown in Fig. 3(b). Note that the loop filter does not include a series capacitor, so it has finite DC impedance. If, as shown in the figure, a differential implementation is chosen, the midpoint of the loop filter can be tapped directly to set the common mode, significantly simplifying common mode control versus that of the conventional design. Mismatch between up and down resistors has similar effect on PLL performance as mismatch between up and down currents in a conventional PLL, namely, reference spur generation. In the proposed design, however, matching between up and down currents can be improved with common centroid layouts that match resistor to resistor as shown in Fig. 3(b); such an approach cannot be used to match NMOS to PMOS devices in a conventional charge pump. Per our Monte Carlo simulation results, effective current mismatch in the proposed resistor-only scheme is approximately 1/3 that of a conventional charge pump current source approach. The impedances of the up/dwn switch resistors are significantly less than those of equivalent MOS based current sources; however this characteristic does not result in a more supply-sensitive PLL as compared to a single path analog PLL. First, as the proportional path does not support frequency tracking, its gain is significantly reduced as compared with that required in a single path PLL. Second, due to the symmetry of the differential control configuration, once the PLL is in phase lock, both sides of the differential

Fig. 3. (a) Example of a conventional differential charge pump and loop filter. (b) Proposed proportional path charge pump and loop filter.

Fig. 4. Review of the integral path control scheme.

proportional control nodes will be at the same voltage and have approximately equal VCO gain, and consequently provide a degree of common-mode rejection. To clarify the principles of the operation of the analog proportional path of the proposed design, first consider a transient example in which UP and DWN are both asserted. Because the common mode is maintained at VDD/2 in the proposed design, the up and down currents will match to the degree the pull up and pull down resistors match, hence nominally no change in DC control voltage will occur. If the feedback clock arrives at a time late with respect to the reference clock, this will results

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Fig. 5. Full integrating and proportional control scheme.

in an assertion of UP for a time longer than DWN. Then (from a small-signal perspective) a net up current of (Vdd/2)/ Rswitch will flow for . The resulting voltage change will be . With typical values of , , and , the voltage change of the control signal per of phase error is on the order of 0.2 mV, validating the small signal assumption for the locked condition. The proportional path gain can be modified by changing the size of the switched resistors; the prototype includes 1 k, 5 k, and 10 K switched resistors which can be independently enabled so as to change the proportional path gain. The loop filter ripple capacitor performs the same function as that in a conventional charge-pump PLL. In the proposed hybrid design, however, the proportional path gain is smaller than that of a charge-pump PLL. This reduced gain limits the thermal noise contribution of the loop filter resistor (R1 in Fig. 3); a simple analysis shows that this contribution is well below the noise contribution of the VCO. Fig. 4 provides details of the integral path control scheme, in which the early/late information encoded in the LATE signal from the BB-PFD is processed to drive the frequency control of the VCO. The integral path gain is controlled using a 16-bit word, , which is loaded using the prototype’s serial interface. The LATE signal selects whether is added to or subtracted from the running total held in the 24-bit accumulator; the magnitude of corresponds to the 16 LSBs of the accumulator. The accumulator output is used in two parallel paths to establish the control of the VCO. The first of these paths is used to control a coarse, digitally switched varactor bank, driving an increment operation when the accumulator overflows and a decrement operation when the accumulator underflows. Further detail regarding the implementation of this control scheme will be presented below. The second of these paths is used to drive a fine control RC-filtered varactor. In this path, the 24 bits of the accumulator are first quantized to 8 bits in the feedback clock domain, then the resulting 8 bits are then quantized to one bit in the faster prescaler clock domain. This cascaded approach allows the quantizer noise to be shaped to higher frequency but eliminates the need to perform the full 24-bit quan-

tization in the fast clock domain, thus saving power and reducing the timing challenges as compared with the single modulator approach. The output of this second is provided to the VCO either through an RC filter ( , ) or directly under serial interface control; the purpose of the direct path is to enable direct evaluation of the RC filter’s effectiveness in enhancing PLL performance. This RC filter affects integral path only. The pole location was placed well outside the loop bandwidth so as to limit changes to the loop dynamics, but well below the prescaler clock frequency (e.g., if GHz, prescaler clock GHz), so as to provide significant suppression (approximately 30 dB) of the noise. The key elements and benefits of the proposed approach can be understood in the context of Fig. 5, which summarizes the complete analog proportional and digital integral path control structure of the proposed PLL. The architecture’s analog components are both simple and friendly to low headroom CMOS implementation, while its digital components are built from standard cell library elements. The ripple capacitors are not only small, but, as they are not used over a wide voltage range, do not have to be particularly linear. The absolute values of the resistors used in the design are not critical, provided resistor-to-resistor tracking is reasonable. Finally, no external bias current or current mirroring is required, eliminating a source of noise found in conventional architectures. The switchable capacitor and varactor control structure of the VCO core is shown in Fig. 6. As described above, a 4-bit digital input driven from outside the main loop enables PLL coarse frequency band selection. Analog-controlled varactors are used for the analog proportional path as well as for the filtered fine control output of the integral path. The remainder of the integral path control is implemented digitally using a weighted capacitor bank as described in greater detail below. Once the PLL achieves phase lock, the integral path coarse bank will very occasionally be incremented or decremented when the digital integrator overflows or underflows, typically in response to drift in the center frequency of the VCO (this is separate from the integral path which updates continuously).


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Fig. 6. Review of the varactor control structure in the VCO core.

Fig. 7. Comparison of capacitor configurations (a) Thermometer weighted (b) Binary weighted (c) Linear weighted.

When these switching events occur, mismatch in the digitally switched capacitor bank can potentially result in transient frequency errors. Consequently it is desirable to use a scheme that minimizes the matching requirements in the capacitor bank. In a capacitor switching scheme, the most stringent worst case increment/decrement event occurs when the largest numbers of capacitors have to simultaneously be switched. There are many possible approaches to realizing the integral path capacitor bank, with Fig. 7 showing three of these possibilities. Fig. 7(a) shows an implementation using thermometer coding. The advantage of such an approach, is that it simplifies matching requirements—incrementing or decrementing requires only once capacitor change—but this benefit comes at the cost of a large total number of unit capacitors and control wires. The increase in control wires makes it difficult to maintain a small footprint for the varactor block due to design rule-driven inter-capacitor spacing requirements, leading to routing challenges and increased parasitic capacitance and inductance, each of which present issues in the context of a high frequency parasitic-sensitive VCO design. Fig. 7(b), by contrast, shows a binary implementation that minimizes control wire count. In this case, the cost of this benefit is much stricter matching requirements which are maximally severe at the major code transition, or 1000000 0111111 in the 7-bit design that would be required in the implemented prototype. Finally, Fig. 7(c) shows the proposed redundant numbering scheme developed and implemented for the prototype design, where a linearly weighted set of 12 capacitors enable the integral path-driven digital controls, supporting 78 discrete frequency

steps. The approach is redundant in that there are multiple configurations which can produce the same net capacitance. The benefit of the approach is that it offers an implementation-friendly compromise between the thermometer- and binary-encoded schemes, namely, reduced area requirements as compared to the former and reduced matching requirements as compared to the latter. Fig. 8 shows an example of the redundant numbering scheme in operation, with the initial state of the redundant numbering control vector being 0000 0000 0001. In the first six illustrated steps, the accumulator generates INC pulses, requesting that the integral path digitally controlled capacitance be incremented by one unit capacitance. In the first step, the ‘1’-weighted capacitor and the ‘2’ weighted capacitor are simultaneously switched, resulting in activation of two units of capacitance. In the third step, similarly, the weight ‘3’ capacitor and weight ‘2’ capacitor controls are swapped with the weight ‘1’ and all other capacitor controls left unchanged, resulting in activation of four units of capacitance. As illustrated in the rightmost column in the Figure, the net capacitor size can be incremented or decremented with at most two simultaneous switching events, in contrast to the major code transition in a binary weighted scheme. Note further that multiple control codes serve to activate the same nominal amount of capacitance, giving rise to the redundant numbering terminology for the architecture. The worst case incrementing event occurs when the largest capacitor (unit 12) has to be enabled, while the second largest (11) is disabled. This corresponds to a worst case simultaneous switching of of the total capacitors, as compared

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Fig. 8. Switching sequence example. The number of capacitors enabled can always be incremented or decremented with no more than two capacitor changes.


Fig. 10. The physical design of the

m

m prototype.

Fig. 9. VCO architecture. The VCO’s frequency control mechanism include the digitally switch linear scaled capacitors, the 4-bit coarse bank, the analog varactors for the proportional path, and the varactor for the integral path.

with 100% of the capacitors that must be switched in the major code transition of a binary scheme. The varactor architecture in the context of the overall architecture of the VCO implemented in the prototype PLL is shown in Fig. 9. The NMOS and PMOS cross coupled pairs provide a high gain gm cell and enable robust VCO startup. The value of the inductor is 0.4 nH, resonating with a total switchable capacitance of approximately 0.12 pF. The integral path analog varactor is sized to be slightly larger than the LSB of the digitally controlled varactors of the redundant numbering scheme. This design choice prevents dead zones (unreachable frequencies) from occurring in the integral path transfer curve. Fig. 10 shows the physical design of the PLL core. The overall m m area of the PLL is dominated by the area of the inductor. The area of the analog portion of the control loop is less than that of the digital, reflecting the simplification of the analog portion of the design in the realized dual-path hybrid PLL.

Fig. 11. Measured tuning range. The left axis shows the measured frequency at the divider-by-2 output, the right axes shoes the corresponding VCO frequency.

Fig. 12. Measured phase noise at 14 GHz output (28 GHz VCO).


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Fig. 13. Phase noise while varying loop gain parameters.

III. MEASUREMENTS The proposed dual-path hybrid PLL architecture was implemented in a 32 nm SOI CMOS test site suitable for probe cardbased evaluation. Fig. 11 shows the measured tuning range of the realized design, with the x-axis showing the 16 control bands (labeled 0 to 15) and the y-axis the measured output frequency; note that because the output follows the internal divide-by-two in the design, PLL operating frequencies are twice those reported in the left had Y-axis of this figure. As can be seen in the figure, the total supported tuning range is 23.8 to 30.2 GHz, with the measured results showing significant overlap between adjacent bands as desired. Fig. 12 shows a typical phase noise measurement of the implemented design. In this measurement (again taken at half-rate), the PLL was operating at 28 GHz from a 194.4 MHz input clock, resulting in measured 10 MHz offset phase noise of 116 dBc/Hz at 14 GHz ( 110 dBc/Hz translated to 28 GHz) and 200 fs integrated jitter over a 1 MHz to 1 GHz integration bandwidth. Fig. 13 shows the effect of modifying PLL control parameters on the phase noise characteristic of the realized prototype design, again with all results taken using the half-frequency PLL output. In the left side of the figure, the results of varying the proportional path gain are shown, with the expected increase in peaking as the proportional path gain is decreased with the integral path gain held constant clearly evident. In the right side of the figure, the results of varying the integral path gain are shown, with the expected increase in peaking as the integral path gain is increased while the proportional path gain held constant again clearly evident. These results clearly show the ability of the proposed dual-path hybrid design to support PLL noise characteristic shaping via independent control of integraland proportional-path controls. The results shown in Fig. 14, meanwhile, show the effectiveness of the RC filter in the integral path’s -modulated LSB output in improving PLL performance. When the RC filter is bypassed, the PLL not only generates significant unwanted spurs in its output spectrum at offsets around and beyond 100 MHz, but these spurs are further

Fig. 14. Addition of RC filter has a dramatic effect on both the high frequencyspurious content and the low frequency in-band nose.

nonlinearly processed within the loop and thus increase in-band (below 1 MHz offset frequency noise). When the RC filter is activated, however, both the spurs and the resulting additional in-band noise are dramatically reduced. Fig. 15 illustrates a further benefit of the proposed approach as compared to an all-digital architecture. In addition to the filter bypass mode described above, the prototype also supports a full bang-bang PFD-based digital operating mode, enabling direct comparison between the hybrid and all-digital personalities of the implemented design. In the experiment shown in the figure, the noise response of the PLL in each configuration was evaluated with and without modulation applied to the input reference clock. The intent of this experiment is to demonstrate the relative insensitivity to large signal disturbances of the proposed PLL’s transfer function as compared to that of a conventional digital PLL. As the integral path is identical in both cases, its gain was reduced for this test, making proportional path-driven behavior clear. In the results shown for the digital configuration (left, Fig. 15(a)), the modulated reference significantly increases in-band phase noise due to the strong noise sensitivity

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Fig. 15. Modulated of the reference clock, (a) in an all digital configuration (b) in a hybrid configuration.

TABLE I PERFORMANCE COMPARISON

of the BB-PFD transfer function. This undesirable effect is reduced in the hybrid implementation (right, Fig. 15(b)), benefiting from the reduced noise sensitivity of the hybrid design’s proportional path. The PLL is implemented in 32 nm SOI CMOS technology, with its core active circuits occupying an area of 0.0225 mm . The PLL supports a frequency range of 23.8–30.2 GHz and exhibits phase noise of 110 dBc/Hz at a 10 MHz offset from the carrier, as well as phase noise of 86 dBc/Hz at a 1 MHz offset from the carrier (dependent on configured PLL bandwidth); it draws 31 mW from a nominal 1 V supply. In Table I we compare this work with a selection of recently published analog and digital high frequency PLLs.

IV. CONCLUSION In this work, we have described an I/O-class 32 nm SOI CMOS LC-tank based integer-N PLL for wireline communication applications, with a control loop implemented using a hybrid of digital and analog PLL techniques. The proposed hybrid PLL features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. The measured jitter performance and tuning range of the PLL meets the requirements of a 28 Gb/s wireline communication link.

REFERENCES [1] A. Rylyakov, J. Tierno, H. Ainspan, J. O. Plouchart, J. Bulzacchelli, Z. T. Deniz, and D. Friedman, “Bang-bang digital PLLs at 11 and 20 GHz with sub-200fs integrated jitter for high-speed serial communication applications,” in IEEE ISSCC Dig. Tech. Papers, , Feb. 2009, pp. 94–95. [2] N. Da Dalt, “Markov chains based derivation of the phase detector gain in bang-bang PLLs,” IEEE Trans. Circuits Syst. II, vol. 53, no. 11, pp. 1195–1199, Nov. 2006. [3] M. Z. Straayer and M. H. Perrott, “A 12-bit 10 MHz bandwidth, continuous-time delta-sigma ADC with a 5-Bit, 950-MS/s VCO-based quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814, 2008. [4] R. Beards and M. Copeland, “An oversampling delta-sigma frequency discriminator,” IEEE Trans. Circuits Syst. II, vol. 41, no. 1, pp. 26–32, Jan. 1994. [5] C. Venerus and I. Galton, “Delta-Sigma FDC based fractional-PLLs,” IEEE Trans. Circuits Syst. I, vol. 60, no. 5, pp. 1274–1285, May 2013. [6] M. Lee and A. Abidi, “A 9 b, 1.25 ps resolution coarse-fine time-todigital converter in 90 nm CMOS that amplifies a time residue,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769–777, Apr. 2008. [7] V. Kratyuk, P. Hanumolu, K. Ok, U.-K. Moon, and K. Mayaram, “A digital PLL with a stochastic time-to-digital converter,” IEEE Trans. Circuits Syst. I, vol. 56, no. 8, pp. 1612–1621, Aug. 2009. [8] M. Perrott, Y. Huang, R. Baird, B. Garlepp, D. Pastorello, E. King, Q. Yu, D. Kasha, P. Steiner, L. Zhang, J. Hein, and B. del Signore, “A 2.5-Gb/s multi-rate 0.25-m CMOS clock and data recovery circuit utilizing a hybrid analog/digital loop filter and all-digital referenceless frequency acquisition,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2930–2944, Dec. 2006. [9] W. Yin, R. Inti, A. Elshazly, B. Young, and P. Hanumolu, “A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1870–1880, 2011. [10] A. Sai, T. Yamaji, and T. Itakura, “A 570 fs rms integrated-jitter ringVCO-based 1.21 GHz PLL with hybrid loop,” in IEEE ISSCC Dig. Tech. Papers, , Feb. 2011, pp. 98–100.


[11] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, “A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 42–51, Jan. 2008. [12] M. Ferriss, J. O. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, J. Tierno, A. Babakhani, S. Yaldiz, A. Valdes-Garcia, B. Sadhu, and D. Friedman, “An integral path self-calibration scheme for a dual-loop PLL,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 996–1008, Apr. 2013. [13] Z. Ru, P. Geraedts, E. Klumperink, X. He, and B. Nauta, “A 12 GHz 210 fs 6 mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO,” in Symp. VLSI Circuits, Jun. 2013.

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José A. Tierno (M’11) received the Engineering degree from the Universidad de la República, Montevideo, Uruguay, in 1988. He received the M.S. degree in electrical engineering in 1989 and the Ph.D. degree in computer science in 1995, both from the California Institute of Technology, Pasadena, CA, USA. From 1995 to 2012, he worked at the IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, on digital circuits for communications. Since 2012, he has worked at Apple Inc, Cupertino, CA, USA, as a research scientist. His main areas of interest are self-timed digital circuits, and digital replacement of analog circuits.

Herschel Ainspan received the B.S. and M.S. degrees in electrical engineering from Columbia University, New York, NY, USA, in 1989 and 1991, respectively. In 1989, he joined the IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, where he has been involved in the design of mixed-signal and RF ICs for high-speed data communications. Mark Ferriss received the B.E. degree from University College Cork, Ireland, in 1998, and the M.S.E and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2005 and 2008, respectively. From 1998 to 2002, he worked at Analog Devices, Limerick, Ireland. In July 2009, he joined IBM’s T. J. Watson Research Center, Yorktown Heights, NY, USA. His interests include RF communication circuits and analog-to-digital interface circuits.

Alexander Rylyakov received the M.S. degree in physics from the Moscow Institute of Physics and Technology, Moscow, Russia, in 1989, and the Ph.D. degree in physics from the State University of New York (SUNY) at Stony Brook, NY, USA, in 1997. From 1994 to 1999 he worked in the Department of Physics at SUNY Stony Brook on the design and testing of integrated circuits based on Josephson junctions. In 1999, he joined IBM T. J. Watson Research Center as a research staff member. His main current research interests are in the areas of digital phase-locked loops and integrated circuits for wireline and optical communication.

Daniel J. Friedman (S’91–M’92) received the Ph.D. degree in engineering science from Harvard University, Cambridge, MA, USA, in 1992. After completing consulting work at MIT Lincoln Labs and postdoctoral work at Harvard in image sensor design, he joined the IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, in 1994. His initial work at IBM was the design of analog circuits and air interface protocols for field-powered RFID tags. In 1999, he joined the mixed-signal communications IC design group and turned his attention to analog circuit design for high-speed serializer/deserializer macros. He managed the mixed-signal team from 2000 to 2009, focusing efforts on serial data communication and clock synthesis applications. In 2009, he became manager of the communication circuits and systems group, adding responsibility for teams in millimeter-wave wireless and digital communications IC design. He has authored or co-authored more than 40 technical papers in circuit topics including serial links, PLLs, RFID, and imagers. He holds more than 50 patents. His current research interests include high-speed I/O design, PLL design, and circuit/system approaches to enabling new computing paradigms. Dr. Friedman was a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC and the 2009 JSSC Best Paper Award given in 2011. He has been a member of the ISSCC International Technical Program Committee since 2008. He has served as the Wireline sub-committee chair for ISSCC since 2012.