A 3-Z-Network Boost Converter - IEEE Xplore

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 1, JANUARY 2015

A 3-Z-Network Boost Converter Guidong Zhang, Student Member, IEEE, Bo Zhang, Member, IEEE, Zhong Li, Dongyuan Qiu, Member, IEEE, Liqiang Yang, and Wolfgang A. Halang

Abstract—A novel boost converter is proposed in this paper, which consists of three active Z-networks and is then named as a 3-Z-network boost converter. A distinct advantage of this proposal is that it can reach a high-gain voltage and well fulﬁll the stringent requirements from industry, particularly renewable power systems, to boost low voltage from clean sources such as photovoltaic (PV) arrays and fuel cells to high voltages for grid-connected converters. Corresponding to different states of the diodes and currents of the capacitors, six operational cases of the proposed converter, including two continuous-current modes (CCMs) and four discontinuous-current modes (DCMs), are analyzed. It is then followed with the parameters design. Finally, simulations and experiments are conducted to verify the effectiveness of the proposed converter. Index Terms—Boost converter, continuous-current modes (CCMs), discontinuous-current modes (DCMs), high-gain voltage, Z-network.

I. I NTRODUCTION

W

ITH the advance of industrial applications, new industries such as the one based on renewable energy are unprecedentedly flourishing and have ever higher demands on the power electronics technology. For instance, renewable power systems require dc–dc boost converters to boost low voltages from clean sources such as photovoltaic (PV) arrays and fuel cells to high voltages for the grid-connected inverters [1]. The demand for such a converter can be also found in the back-up energy conversion for uninterruptible power systems, high-intensity discharge lamps for automobile headlamps, the front-end stage for the communication power system [2], to name just a few. In those applications, highly efficient and high step-up dc–dc converters are necessary to handle large Manuscript received January 24, 2014; revised March 26, 2014; accepted April 29, 2014. Date of publication May 29, 2014; date of current version December 19, 2014. This work was supported in part by the Key Program of the National Natural Science Foundation of China under Grant 50937001, in part by the Guangdong Strategic Emerging Industry Special Fund Project under Grant 2010A081002004, and in part by the German AiF-IGF-Project under Grant 17211N. G. Zhang is with the School of Electric Power, South China University of Technology, Guangzhou 510640, China, and also with the Faculty of Mathematics and Computer Science, FernUniversität in Hagen, 58084 Hagen, Germany (e-mail: [email protected]). B. Zhang, D. Qiu, and L. Yang are with the School of Electric Power, South China University of Technology, Guangzhou 510640, China (e-mail: [email protected]; [email protected]; epdyqiu@ scut.edu.cn). Z. Li and W. A. Halang are with the Faculty of Mathematics and Computer Science, FernUniversität in Hagen, 58084 Hagen, Germany (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2014.2326990

input current and sustain high output voltage. Theoretically speaking, the conventional boost converters can realize infinite voltage gain with an extreme duty cycle when ignoring parasitic parameters. Moreover, the conventional boost converters are restricted by the parasitic parameters of their components and suffer serious power loss. Furthermore, the modern semiconductor technology can still not provide efficient and economic high-voltage stress diodes and switches for the boost converters. In practical applications, the voltage gain of the conventional boost converters can maximally reach five to six times of the input voltage, which is far away from the practical requests [3]–[5]. To obtain the desired voltage, boost converters can be connected in series, which is, however, very complicated due to the additional switches and control units. Furthermore, the additional switches and control units degrade the reliability of the systems [6], [7]. A high-frequency isolation dc–dc converter with a high transformer turn ratio is applied to solve those problems [8], but the efficiency is thus reduced due to the transformer, and the volume and weight of the whole system increase. For example, quadratic boost converters are the most popular cascaded converters applied in practice, in which two switches and control circuits are excessively used, but cannot ensure sufficient voltage gains. Further, many improvements based on the cascading techniques have been made, i.e., a cascade Cockcroft–Walton voltage multiplier applied to a transformerless dc–dc converter [9], a high voltage-boosting converter based on bootstrap capacitors and boost inductors [10], a quadratic power converter [11], and different kinds of interleaved high step-up converters for reducing the current ripple and getting a high voltage gain [12]–[14]. However, those proposals suffer from the problems of using multiple switches and control units, which increase the complexity and cost of the systems and reduce their sufficiency and reliability. Some converters can reach high voltage gain by only one or two switches, e.g., a dc–dc multilevel boost converter [15] and a switched-capacitor-based active-network converter [16], but the voltage gain is still not large enough for industrial applications. A novel, simple, but efficient design was initiated by Peng via applying just an LC network, named as a Z-network, to couple the dc source with the converters, and thus, he proposed a novel source, which is different from the conventional voltage source and current source, and is named as a Z-source [17]. Since then, the Z-source technology has greatly advanced and has distinct advantages, e.g., it can realize a high voltage gain and, meanwhile, can be immune to shoot-through problems. Straightforwardly, to realize a high voltage gain in dc–dc

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ZHANG et al.: 3-Z-NETWORK BOOST CONVERTER

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The 3-Z-network boost converter can operate both in CCM and DCM. According to different states of the diodes and the currents of the capacitors, its six operational cases, including two CCMs and four DCMs, are analyzed in the following. III. CCM Fig. 1.

3-Z-network boost converter.

converters, Z-source technologies are also applied to boost the voltage, because Z-source converters can work in the shoot-through mode, and its output voltage can reach a broader range than that of the conventional ones. For example, Peng has proposed some novel Z-source circuits [18], [19] and corresponding control methods [20], [21]. Following Peng’s proposals, new Z-source circuits with high voltage gain have also been proposed, such as the algorithms for controlling the converters to reach high voltage gain [22], [23], generalized multicell switched-inductor and switchedcapacitor Z-source converters for high voltage gain [24], trans-Z-source inverters with the boost function [25], and quasi-Z-source-based isolated dc–dc converters for distributed power generation [26]. However, the voltage gains of these Z-source converters may be still not enough for many industrial applications, which puts forward a challenge for designing converters with even higher voltage gains. In this paper, a novel boost converter with three active Znetworks is proposed and thus named 3-Z-network converters, which not only have the advantages of the Z-network converters but also can reach much higher voltage gains. Moreover, the 3-Z-network converters operate not only in continuouscurrent modes (CCMs) but also in discontinuous-current modes (DCMs). CCM refers to the normal load condition, under which the traditional boost converters work. Due to the unstable energy source in renewable energy systems, such the PV systems, the load conditions become abnormal, corresponding to DCM. The remainder of this paper is organized as follows. Section II gives the design of the proposed 3-Z-network converter. In Sections III and IV, the proposed converter in both CCM and DCM will be analyzed, respectively. It is followed by the parameters design of the converter in Section V. In Section VI, simulations via PSIM will be conducted to verify the theoretical analysis. In Section VII, a prototype is built to illustrate the performance of the proposed converter. Finally, a conclusion is drawn in Section VIII. II. 3-Z-N ETWORK B OOST C ONVERTER The diagram of the proposed converter is depicted in Fig. 1, in which three active Z-networks are combined. It is different from the traditional Z-source networks, which normally consist of passive elements. In this 3-Z-network converter, Z-network 1 functions as the first boost part, consisting of inductors L1 and L2 and diodes D1 , D2 , and D3 ; Z-network 2 is the switch part, consisting of switch Q, capacitor C1 , and diodes D4 and D5 ; and Z-network 3 is the second boost part, consisting of L3 and L4 and diodes D6 , D7 , and D8 . A distinct feature of the proposed converter is that there is only one switch used.

For simplicity, it is assumed that 1) all the components are ideal, 2) the free-wheeling diode of the switch is ignored, and 3) L1 = L2 and L3 = L4 . In the periodic states (on and off) of switch Q, the inductor stores and releases energy alternately. Correspondingly, their currents increase and decrease alternately. Then, there correspond some cases to the current states of the inductors as the current decreases to be 0 and lasts for an interval, which is called the discontinuous-current case of inductors. Consequently, the inductors can have continuous or discontinuous currents under some combinations of the inductances, the load, and the duty. Therefore, the proposed converter can function in the CCM or the DCM, which then correspond to six modes, i.e., six linear equivalent circuits, as shown in Fig. 2(a)–(f), respectively. Therein, vL1 , vL2 , vL3 , and vL4 are voltages of L1 , L2 , L3 , and L4 , respectively. Assume the clockwise direction as positive directions of the reference currents, and the arrows shown in Fig. 2(a) refer to the positive directions of the inductor reference voltages. Moreover, the detailed states of the components in the circuit are shown in Table I. Here, the proposed converter’s performance in CCMs will be introduced in detail, i.e., Case 1: Mode 1 → Mode 2; Case 2: Mode 1 → Mode 2 → Mode 3; which are shown in Fig. 3. A. Case 1 As Fig. 3(a) shows, there are two modes in this case, namely, Modes 1 and 2, whose equivalent circuits are shown in Fig. 2(a) and (b). Denote D as the duty of switch Q, t0 as the beginning of one period, t1 as the mode transition instant from Mode 1 to Mode 2, and t2 = T as the end of the period. To describe the operation process of the converter in Case 1, key waveforms of the proposed converter in the steady state are shown in Fig. 4(a), where two modes are marked in two different colors within one period. Moreover, Fig. 4(a)(1) describes the driven voltage vg of switch Q; Fig. 4(a)(2) illustrates the waveform of iL1 (iL2 ), which is composed of two parts with the blue one referring to the waveform of iD1 (= iD3 ) and the red one to the waveforms of iD2 (= iD5 ); Fig. 4(a)(3) depicts the waveform of iL3 (iL4 ), which is also composed of two parts with the blue one referring to the waveform of iD6 (= iD8 ) and the red one to the waveform of iD7 (= iD9 ); and Fig. 4(a)(4) portrays the waveforms of iC1 . Therein, iL1 , iL2 , iL3 , iL4 , iD1 , iD2 , iD3 , iD5 , iD6 , iD7 , iD8 , iD9 , iC1 , and iC2 are the currents of L1 , L2 , L3 , L4 , D1 , D2 , D3 , D5 , D6 , D7 , D8 , D9 , C1 , and C2 , respectively. 1) Mode 1—t ∈ [t0 , t1 ]: As shown in Fig. 2(a), there are three loops in the circuit, marked in different colors, and the arrows in the circuit refer to the current direction in each loop. As Q turns on, diodes D1 , D3 , and D4 undertake positive

280


TABLE I S TATES OF C OMPONENTS IN D IFFERENT M ODES

Fig. 3.

Transitions between modes in CCM. (a) Case 1. (b) Case 2.

are shown in Fig. 4(a)(2), where iD1 = iD3 = iL1 = iL2 ; and iD4 , which is the current of D4 , endures iL1 + iL2 , namely, iD4 = iL1 + iL2 = 2iL1 . Accordingly, one has ⎧ i D 1 = iD 3 = iL 1 = iL 2 ⎪ ⎪ ⎪ ⎨ iD 2 = 0 iD4 = iD1 + iD3 = 2iL1 (1) ⎪ ⎪ v ⎪ L1 = V s ⎩ v L2 = V s

Fig. 2. Equivalent circuits. (a) Mode 1: Q, D1 , D3 , D4 , D6 , and D8 on, D2 , D5 , D7 , and D9 off. (b) Mode 2: D2 , D5 D7 , and D9 on, Q, D1 , D3 , D4 , D6 , and D8 off. (c) Mode 3: D2 , D5 , D7 , and D9 on, Q, D1 , D3 , D4 , D6 , and D8 off. (d) Mode 4: D2 , D7 , and D9 on, Q, D1 , D3 , D4 , D5 , D6 , D7 , and D8 off. (e) Mode 5: D2 and D5 on, Q, D1 , D3 , D4 , D6 , D7 , D8 , and D9 off. (f) Mode 6: Q, D1 , D2 , D3 , D4 , D5 , D6 , D7 , D8 , and D9 off.

voltages and turn on synchronously; meanwhile, D2 bears negative voltage and turns off. Thereafter, L1 and L2 are connected in parallel and then cascaded with D4 , Q, and Vs to form loop 1 with red lines. The source Vs discharges the energy to L1 and L2 , then iL1 and iL2 increase, and L1 and L2 store the energy. The waveforms (blue lines) of iD1 , iD3 , iL1 , and iL2

where vL1 and vL2 are the voltages of L1 and L2 , respectively. Meantime, D5 and D7 undertake negative voltages and turn off, yet D6 and D8 endure positive voltages and turn on. Accordingly, L3 and L4 are connected in parallel and then cascaded with Q and C1 to form loop 2 in blue. C1 discharges the energy to L3 and L4 , and iL3 and iL4 increase. Thus, L3 and L4 store energy. The waveforms of iD6 , iD8 , iL3 , and iL4 are shown in blue in Fig. 4(a)(3), and the waveform of iC1 is shown in Fig. 4(a)(4), where iD6 = iD8 = iL3 = iL4 , and iC1 = −2iL3 , respectively. Then, one has ⎧ i D 6 = iD 8 = iL 3 = iL 4 ⎪ ⎪ ⎪ ⎨ iD 5 = 0 iC1 = −2iL3 (2) ⎪ ⎪ v = v ⎪ L C 3 1 ⎩ v L4 = v C 1 where iL3 , iL4 , vL3 , vL4 , and vC1 are the currents of L3 , L4 , and the voltages of L3 , L4 , and C1 , respectively. Meanwhile, D9 endures the negative voltage and turns off, then the capacitor C2 and the load R are cascaded to form loop 3 in green. Therein, C2 discharges the energy to R, then the output voltage of the converter vo reads v o = v C2 where vC2 is the voltage of capacitor C2 .

(3)


281

Fig. 4. Key waveforms of the 3-Z-network boost converter in CCM. (a) Case 1. (b) Case 2. In each subfigure, (1) describes the driven voltage vg of switch Q; (2) illustrates the waveform of iL1 (iL2 ), composed of two parts with the blue one referring to the waveform of iD1 (= iD3 ) and the red one to the waveform of iD2 (= iD5 ); (3) depicts the waveform of iL3 (iL4 ), composed of two parts with the blue one referring to the waveform of iD6 (= iD8 ) and the red one to the waveform of iD7 (= iD9 ); and (4) portrays the waveform of iC1 .

2) Mode 2—t ∈ [t1 , t2 ]: At t1 , Q turns off, and the mode changes from Mode 1 to Mode 2, as shown in Fig. 2(b). As Q is off, D1 , D3 , D4 , D6 , and D8 undertake negative voltage and turn off, yet D2 , D5 , D7 , and D9 turn on and then form three loops in this mode. Therein, loop 1 is marked with red, namely, Vs –L1 –D2 –L2 –D5 –C1 , where Vs , L1 and L2 discharge energy to C1 , namely, Vs = vL1 + vL2 + vC1 . Moreover, iL1 and iL2 decrease as the red lines shown in Fig. 4(a)(2), and the currents of D2 and D5 are equal to iL1 for the cascaded connection, and iC1 increases as shown in Fig. 4(a)(4), namely, i = i = i = i D2

D5

L1

L2

i D 1 = iD 3 = iD 4 = 0 v L1 + v L2 = V s − v C 1 .

(4)

Vs , L1 , D2 , L2 , D5 , L3 , D7 , L4 , D9 , and C2 form loop 2 marked with red and blue lines, where Vs , L1 , L2 , L3 , and L4 discharge the energy to C2 and R, namely, Vs = vL1 + vL2 + vL3 + vL4 + vC2 , and iC2 decreases due to the discharge energy to the load R. Moreover, iL3 and iL4 decrease as the red lines shown in Fig. 4(a)(3), and the currents of D7 and D9 are equal to iL3 for the cascaded connection, namely, i = i = i = i D7

D9

L3

converter in Case 2 are shown in Fig. 4(b). Therein, three modes are marked with three different colors in one period. The operation process of the proposed converter in a switch period is analyzed in the following section according to the waveforms in Fig. 4(b). 1) Mode 1—t ∈ [t0 , t1 ]: The process is just like the descriptions of Mode 1 in Case 1. 2) Mode 2—t ∈ [t1 , t2 ]: The process is similar to the descriptions of Mode 2 in Case 1 except iC1 . Therein, iC1 decreases as shown in Fig. 4(b)(4), which is different from the increase of iC1 in Fig. 4(a)(4), because the energy stored in the inductors are not enough to charge the load in this case. 3) Mode 3—t ∈ [t2 , t3 ]: At t2 , iC1 , and iC2 decrease to 0, then Mode 3 appears, shown as Fig. 2(c), where Q, D1 , D3 , D4 , D6 , D7 , D8 , and D9 are off, and D2 and D5 are on. Thus, there are also two loops marked in different colors. Loop 1 is the same as loop 1 in Mode 2. In loop 2, iC1 decreases from 0 to negative, which means that not only Vs , L1 , and L2 but also C1 charge the energy to the following circuit, and they fulfill the same equations as in Case 1. IV. DCM

L4

i D 6 = iD 8 = 0 vL3 + vL4 = Vs − (vL1 + vL2 + vC2 ).

(5)

B. Case 2 Cases 1 and 2 are both CCMs. Nevertheless, different to Case 1, there are three modes in Case 2 due to the direction of iC1 , i.e., Modes 1, 2, and 3, whose equivalent circuits are shown in Fig. 2(a)–(c). Denote t0 as the beginning of one period; t1 as the mode transition instant from Mode 1 to Mode 2, i.e., t1 = t0 + DT ; t2 as the mode transition instant from Mode 2 to Mode 3; and t3 = T as the end of the period. To describe the operation process of the converter, the key waveforms of the proposed

Here, the performance of the proposed converter in four cases in DCM will be introduced, i.e., Case 3: Mode 1 → Mode 2 → Mode 4; Case 4: Mode 1 → Mode 2 → Mode 3 → Mode 5; Case 5: Mode 1 → Mode 2 → Mode 4 → Mode 6; Case 6: Mode 1 → Mode 2 → Mode 3 → Mode 5 → Mode 6, as shown in Fig. 5, and the corresponding states of the components are shown in Table I. A. Case 3 Different from Cases 1 and 2, Case 3 is a DCM when iL3 and iL4 are discontinuous. There are three modes in this case, i.e., Modes 1, 2, and 4, whose equivalent circuits are shown in Fig. 2(a), (b), and (d).

282

Fig. 5.


Transitions between modes in DCM. (a) Case 3. (b) Case 4. (c) Case 5. (d) Case 6.

Fig. 6. Key waveforms of 3-Z-network boost converter in DCMs. The descriptions are the same as that in Fig. 4. (a) Case 3. (b) Case 4. (c) Case 5. (d) Case 6.

Denote t0 as the beginning of one period; t1 as the mode transition instant from Mode 1 to Mode 2, i.e., t1 = t0 + DT ; t2 as the mode transition instant from Mode 2 to Mode 4; and t3 = T as the end of the period. The key waveforms of the proposed converter in Case 3 shown in Fig. 6(a) can describe the operation process, where three modes are marked in three different colors in one period. The operation process of the proposed converter in a switch period is analyzed in the following according to the waveforms in Fig. 6(a). 1) Mode 1—t ∈ [t0 , t1 ]: The process is exactly the same as that described in Mode 1 in Case 1. 2) Mode 2—t ∈ [t1 , t2 ]: The process is also nearly the same as that described in Mode 2 in Case 1. 3) Mode 4—t ∈ [t2 , t3 ]: When iL3 and iL4 decrease to 0 and Q keeps off, Mode 4 exists, which is described by

iD7 = iD9 = iL3 = iL4 = 0. Then, D7 and D9 are off, and the waveforms are shown in Fig. 6(a). As Fig. 2(c) shows, Q, D1 , D3 , D4 , D6 , D7 , D8 , and D9 are off, but D2 and D5 are on; there are also two loops marked in different colors. From loop 1 marked in red, i.e., Vs –L1 –D2 –L2 –D5 –C1 , one has iC1 = iD2 = iD5 = iL1 = iL2 . The source Vs , L1 , and L2 discharge the energy to C1 , so that vC1 increases, namely, iC 1 = iD 2 = iD 5 = iL 1 = iL 2 (6) iD1 = iD3 = iD4 = 0. In loop 2 marked in blue, C2 discharges energy to R. B. Case 4 Case 4 is also a DCM. It corresponds to the case when iL1 and iL2 are discontinuous. There are four modes in this case,


283

i.e., Modes 1, 2, 3, and 5, and their equivalent circuits are shown in Fig. 2(a)–(c) and (e). Denote t0 as the beginning of one period; t1 as the mode transition instant from Mode 1 to Mode 2, i.e., t1 = t0 + DT ; t2 as the mode transition instant from Mode 2 to Mode 3; t3 as the mode transition instant from Mode 3 to Mode 5; and t4 = T as the end of the period. The key waveforms of the proposed converter in Case 4 as shown in Fig. 6(b) illustrate the operation process. Therein, four modes are marked in four different colors in one period. The operation process in a switch period is analyzed in the following content according to the waveforms in Fig. 6(b). 1) Mode 1—t ∈ [t0 , t1 ]: The process is exactly the same as that described in Mode 1 in Case 2. 2) Mode 2—t ∈ [t1 , t2 ]: The process is exactly the same as that described in Mode 2 in Case 2. 3) Mode 3—t ∈ [t2 , t3 ]: The process is also nearly the same as that described in Mode 2 in Case 2. However, iL1 and iL2 decrease to be 0 shown in Fig. 6(b)(2), which is different from the waveforms of iL1 in Fig. 4(b)(2). Thereafter, Mode 5 occurs. 4) Mode 5—t ∈ [t3 , t4 ]: When iL1 and iL2 decrease to be 0, loop 1 is off. Then, C1 , L3 , and L4 discharge the energy to C2 and R. Meanwhile, C2 also discharge the energy to R. Hence, iC2 decrease from positive to negative. Thereafter, C2 , C1 , L3 , and L4 discharge the energy to R.

and 6, whose equivalent circuits are shown in Fig. 2(a)–(c), (e), and (f). Denote t0 as the beginning of one period; t1 as the mode transition instant from Mode 1 to Mode 2, i.e., t1 = t0 + DT ; t2 as the mode transition instant from Mode 2 to Mode 3; t3 as the mode transition instant from Mode 3 to Mode 5; t4 as the mode transition instant from Mode 5 to Mode 6; and t5 = T as the end of the period. The key waveforms of the proposed converter in Case 6 as shown in Fig. 6(d) illustrate the operation process. Therein, five modes are marked in five different colors in one period. The operation process in a switch period is analyzed in the following according to the waveforms in Fig. 6(d). 1) Mode 1—t ∈ [t0 , t1 ]: The process is exactly the same as that described in Mode 1 in Case 4. 2) Mode 2—t ∈ [t1 , t2 ]: The process is exactly the same as that described in Mode 2 in Case 4. 3) Mode 3—t ∈ [t2 , t3 ]: The process is exactly the same as that described in Mode 3 in Case 4. 4) Mode 5—t ∈ [t3 , t4 ]: The process is exactly the same as that described in Mode 5 in Case 4. 5) Mode 6—t ∈ [t4 , t5 ]: iC1 , iL3 , and iL4 decrease to 0 and Q keeps off, then Mode 6 occurs, which is shown in Fig. 2(f). Therein, C2 discharges the energy to R, and iC2 is constant.

C. Case 5

Here, the parameters of the proposed converter will be discussed according to the analyses above on the operation of the proposed converter both in CCM and DCM. Normally, the parameters design of a converter is to determine the rated voltages and rated currents of the components in the circuit. First, the output voltage Vo will be deduced as follows.

When iL1 and iL2 decrease to 0 in Mode 4 of Case 3, there is only loop 3 left, as shown in Fig. 2(f). It is Case 5. There are four modes in this case, i.e., Modes 1, 2, 4, and 6, whose equivalent circuits are shown in Fig. 2(a), (b), (d), and (f). Denote t0 as the beginning of one period; t1 as the mode transition instant from Mode 1 to Mode 2, i.e., t1 = t0 + DT ; t2 as the mode transition instant from Mode 2 to Mode 4; t3 as the mode transition instant from Mode 4 to Mode 6; and t4 = T as the end of the period. The key waveforms of the proposed converter in Case 5 as shown in Fig. 6(c) illustrate the operation process. Therein, four modes are marked in four different colors in one period. The operation process in a switch period is analyzed in the following content according to the waveforms in Fig. 6(c). 1) Mode 1—t ∈ [t0 , t1 ]: The process is exactly the same as that described in Mode 1 in Case 3. 2) Mode 2—t ∈ [t1 , t2 ]: The process is exactly the same as that described in Mode 2 in Case 3. 3) Mode 4—t ∈ [t2 , t3 ]: The process is exactly the same as that described in Mode 3 in Case 3. 4) Mode 6—t ∈ [t4 , t5 ]: iL1 and iL2 decrease to 0 and Q keeps off, then Mode 6 occurs, as shown in Fig. 2(f). Therein, C2 discharges the energy to R, and iC2 is constant. D. Case 6 When iL3 and iL4 decrease to 0 in Mode 5 of Case 4, then there is only loop 3 left shown in Fig. 2(f), which is Case 6. There are five modes in this case, i.e., Modes 1, 2, 3, 5,

V. PARAMETERS D ESIGN

A. Output Voltage and Voltage Stress of Components According to the analyses of Cases 1 and 2, the output voltage Vo is deduced as follows. In terms of the voltage–second constant theory, one has ⎧ DT T ⎨ 0 (vL1 + vL2 ) dt + DT (vL1 + vL2 ) dt = 0 (7) T ⎩ DT (v + v ) dt + (v + v ) dt = 0. L L L L 3 4 3 4 0 DT Substituting (1)–(5) into (7) leads to 2Vs DT + (Vs − VC1 ) (1 − D)T = 0 2VC1 DT + (VC1 − Vo ) (1 − D)T = 0.

(8)

From (8), one has V o = V C2 = V s V C1 = V s

1+D . 1−D

1+D 1−D

2 (9) (10)

It is remarked that the voltage of diodes is ignored in the deductions above. Similarly, one can obtain the output voltage

284


TABLE II VOLTAGE S TRESS OF E ACH S EMICONDUCTOR C OMPONENT IN CCM

Fig. 7.

Relationship figure of duty cycle D and voltage gain M .

Vop as Vop =

(Vs − 2VD )

1+D 1−D

− 2VD

1+D 1−D

(11)

where VD is the voltage of the diodes. According to (9), the relationships of duty cycle D and voltage gain M = Vo /Vs in conventional boost converters, quadratic boost converters, and 3-Z-network boost converters are depicted in Fig. 7 in different colors, respectively, with a zoom-in for 0 < D < 0.5. It is remarked that the proposed converter can reach a much higher voltage gain than the quadratic and the conventional ones. In terms of (9) and (10), the voltages of L1 , L2 , L3 , and L4 can be obtained as follows. Therein, VL1 , VL2 , VL3 , and VL4 refer to the average voltages of L1 , L2 , L3 , and L4 when Q is on and off, respectively. Thus, Vs , if Q is on (12) VL1 = VL2 = −V D , otherwise

V L3 = V L4 =

s 1−D

Vs 1+D 1−D ,

if Q is on

−Vs D(1+D) (1−D)2 ,

otherwise.

(13)

In terms of Kirhhoff’s voltage law, one can obtain the voltage of each compoent in the circuit as shown in Table II. B. Currents of Components Assuming a lossless circuit leads to Vs · Iin = Vo · Io , where Iin and Io are input and output currents, respectively. In terms of (9), one has Iin = Io

(1 + D)2 . (1 − D)2

Moreover, Iin can also be expressed as T DT 2iL1 dt + DT iL1 dt 0 Iin = = (1 + D)IL1 . T

(14)

(15)

Substituting (15) into (14) results in I L1 = I L2 = I o

1+D . (1 − D)2

(16)

Similarly, IL3 and IL4 can be expressed as I L3 = I L4 = I o

1 . 1−D

(17)

According to (1), (2), (4), (5), and Fig. 4(a), the average currents of the diodes are written as ⎧ ⎪ ID1 = ID3 = DIL1 = Io D(1+D) ⎪ (1−D)2 ⎪ ⎪ ⎪ ⎪ ID2 = ID5 = (1 − D)IL1 = Io 1+D ⎪ 1−D ⎪ ⎨ ID4 = 2DIL1 = Io 2D(1+D) (1−D)2 (18) ⎪ D ⎪ I = I = DI = Io 1−D D D L ⎪ 6 8 3 ⎪ ⎪ ⎪ ⎪ ID7 = ID9 = (1 − D)IL3 = Io ⎪ ⎩ I = D(2I + 2I ) = I 4D . Q L1 L3 o (1−D)2

C. Parameters of Inductors The parameter design of the inductor is to determine the rated current and inductance, given a permitted fluctuation range xL % (xL is preassigned), an output voltage Vo , an output current Io , and a switching period T . 1) Determination of the Rated Current: The rated currents of inductors can be obtained from (16) and (17). 2) Determination of the Rated Inductance: The ripples of the inductors also have great influence on the stability of the converter; consequently, the inductance must be designed in terms of the permitted ripples. The inductors in the converter can be designed based on the differential equation of inductance, i.e., L=

VL dtL diL

(19)

where VL is the voltage of the corresponding inductor as Q is on, dtL = DT is the time interval of Q as it is on, and diL is the current ripple of the corresponding inductor within the time interval, i.e., dtL . Denote the permitted error of IL by diL . diL is restrained by the permitted fluctuation range xL % as diL = xL %IL .

(20)


285

Substituting (20) into (19) leads to the inductance of L, i.e., L=

VL DT . xL %IL

(21)

Thereafter, substituting the average voltage of inductors in (12) and (13) for Q on, as well as (16) and (17) into (21) leads to ⎧ ⎨ L1 = L2 = Vs DT = Vs D(1−D)2 T xL %IL1 xL %Io (1+D) (22) ⎩ L3 = L4 = Vs (1+D)DT = Vs (1+D)DT . (1−D)xL %IL xL %Io 3

Hence, the range of the inductance can be determined based on 0 ≤ D ≤ 1, and the maximum is taken as the rated inductance. D. Parameters of Capacitors Similar to the parameter design of the inductor, the design of the capacitor is to determine the rated voltage and capacitance, given a permitted fluctuation range, xC % (xC is preassigned), an output voltage Vo , an output current Io , and a switching period T . 1) Determination of the Rated Voltage: The rated voltage of capacitors are determined in terms of (9) and (10). 2) Determination of the Rated Capacitance: The ripples of the capacitors have great influence on the stability of the converter, whose permitted fluctuation range can be used to design the capacitance. Then, the capacitors in converter is designed based on the differential equation of capacitors, i.e., C=

IC dtC dvC

(23)

where IC is the current of the corresponding capacitor as Q is on, dtC = DT is the time interval of Q as it is on, and dvC is the voltage ripple of the corresponding capacitor within the time interval, i.e., dtC . Denote the permitted error of VC by dvC . dvC is determined by the permitted fluctuation range xC % as dvC = xC %VC .

(24)

When Q is on, IC1 = 2IL3 , and IC2 = Io ; then, substituting these two equations and (24) into (23) leads to 2I 3 DT 2Io DT C1 = xCL%V = xC %V C1 s (1+D) (25) Io (1−D)2 DT Io DT C2 = xC %Vo = xC %(1+D)2 Vs . Therein, the range of the capacitance can be calculated according to (25), and the maximal one is taken as the rated capacitance. E. Parameters Design of Switching Devices Normally, the design of the diodes is to determine the rated voltage and rated current to keep the diodes safely operating for a long time. 1) Determination of the Rated Voltage: The voltage of switching devices are determined based on Table II.

Fig. 8. Waveforms of the 3-Z-network boost converter. (a) Case 1. (b) Case 2. (c) Case 3. (d) Case 4. (e) Case 5. (f) Case 6.

2) Determination of the Rated Current: The currents of the switching components are given in (18). VI. S IMULATION R ESULTS To verify the feasibility and validity of the proposed converter, PSIM software is applied for the simulation.

286

Fig. 9.


Prototype of the proposed converter.

Fig. 11. Experimental waveforms of case 2 with D = 0.2, R = 200 Ω. From the top to the bottom are the gate–source voltage of switch Q, vGS ; the drain–source voltage of switch Q, vDS ; the current of L1 , iL1 ; the current of L3 , iL3 ; the current of C1 , iC1 ; and the output voltage, vo .

Fig. 10. Experimental waveforms of case 1 with D = 0.5, R = 400 Ω. From the top to the bottom are the gate–source voltage of switch Q, vGS ; the drain–source voltage of switch Q, vDS ; the current of L1 , iL1 ; the current of L3 , iL3 ; and the output voltage, vo .

The preassigned parameters are as follows: Vs = 12 V, Vo = 108 V, and T = 10 μs. Further, assume the parameters of the converter as follows: C1 = 220 μF, C2 = 470 μF, L1 = L2 = 100 μH, L3 = L4 = 200 μH. The simulation results are shown in Fig. 8. In the six subfigures for six cases, from the top to the bottom are the driven voltage vg , the current of the inductors L1 (L2 ), L3 (L4 ) and the capacitor C1 , and the output voltage vo , respectively. VII. E XPERIMENTAL R ESULTS A prototype of 3-Z-network boost converter is built as shown in Fig. 9, and the parameters are chosen as follows for Case 1: C1 = 220 μF, C2 = 470 μF, L1 = L2 = 100 μH, L3 = L4 = 200 μH, R = 400 Ω, and T = 10 μs. The converter, shown in Fig. 9, is composed of L1 , L2 , C1 , C2 , switch Q (Type: IRFP250N), D1 –D8 (Type: SB5100), and D9 (Type: MBRF20200). IXDN404 IC is used to drive switch Q. The waveforms of the converter with an input voltage of 12 V are shown in Fig. 10, where, from the top to the bottom, are the gate–source voltage of switch Q, vGS ; the drain–source voltage


of switch Q, vDS ; the current of L1 , iL1 ; the current of L3 , iL3 ; and the output voltage, vo . Moreover, the output voltage is about 99.5 V. Furthermore, the mean currents of iL1 and iL3 are about 1.64 and 0.53 A, respectively. Hence, the experimental results verify the analytical and simulation results. Similarly, Figs. 11–15 show the results for Cases 2–6, where the parameter settings are as follows: C1 = 220 μF, C2 = 470 μF, L1 = L2 = 45 μH, L3 = L4 = 140 μH, T = 10 μs. It is remarked that the experimental results are consistent with the theoretical and simulation results. The efficiency of the converter can be described by 1+D 1+D )−2VD )( 1−D )) (((Vs −2VD )( 1−D Pout R = η= Pin Vs Iin

2 Vs (1 + D) − 4VD = Vs (1 + D)

2

(26)



287


Fig. 16. Comparison between the experimental and the expected efficiencies. Fig. 14. Experimental waveforms of case 5 with D = 0.25, R = 500 Ω. From the top to the bottom are the gate–source voltage of switch Q, vGS ; the drain–source voltage of switch Q, vDS ; the current of L1 , iL1 ; the current of L3 , iL3 ; the current of C1 , iC1 ; and the output voltage, vo .

where Pout , Pin , VD , and Iin are the output power, the input power, the voltage of diode, and the input current, respectively. A comparison between the experimental and the predicted efficiencies is shown in Fig. 16. VIII. C ONCLUSION A novel boost converter with three active Z-networks has been proposed in this paper, in which only one switch is used. It can reach a high gain voltage and well fulfill the stringent requirement from industry, particularly renewable power systems, to boost low voltage from clean sources such as PV arrays and fuel cells to high voltages for grid-connected converters. The proposed converter is analyzed in six different cases according to the states of the switches, including two CCMs and four DCMs. Moreover, the parameters design of the proposed converter has been discussed. Simulations and experiments have been conducted to verify the effectiveness of

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Guidong Zhang (S’13) was born in Guangdong, China, in 1986. He received the B.Sc. degree in electrical engineering and automation from the School of Automation and Information Engineering, Xi’an University of Technology, Xi’an, China, in 2008. He has been engaged in successive postgraduate and doctoral programs of study for a doctoral degree in power electronics and electric transmission at the School of Electric Power, South China University of Technology, Guangzhou, China, since September 2010. He is currently working toward the Ph.D. degree at FernUniversität in Hagen, Hagen, Germany. His research interests include power electronics converter topologies and their applications.

Bo Zhang (M’03) was born in Shanghai, China, in 1962. He received the B.Sc. degree in electrical engineering from Zhejiang University, Hangzhou, China, in 1982, the M.Sc. degree in power electronics from Southwest Jiaotong University, Chengdu, China, in 1988, and the Ph.D. degree in power electronics from Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 1994. He is currently a Professor and the Deputy Dean of the School of Electric Power, South China University of Technology, Guangzhou, China. He has authored or coauthored more than 350 papers and 18 patents. His current research interests include nonlinear analysis and control of power supplies and ac drives. Zhong Li received the B.Sc. degree from Sichuan University, Chengdu, China, in 1989, the M.Sc. degree from Jinan University, Guangzhou, China, in 1996, the Ph.D. degree from South China University of Technology, Guangzhou, in 2000, and the D.Sc. (Habilitation) degree from FernUniversität in Hagen, Hagen, Germany, in 2007. He is currently an Adjunct Professor with FernUniversität in Hagen. He serves as an Associate Editor for six international journals and has published four books with Springer-Verlag, 18 book chapters, 53 journal papers, and 44 conference papers. His research interests include fuzzy logic and fuzzy control, chaos theory and chaos control, intelligent computation and control, complex networks, and swarm intelligence. Dongyuan Qiu (M’03) was born in China in 1972. She received the B.Sc. and M.Sc. degrees from South China University of Technology, Guangzhou, China, in 1994 and 1997, respectively, and the Ph.D. degree from the City University of Hong Kong, Kowloon, Hong Kong, in 2002. She is currently a Professor with the School of Electric Power, South China University of Technology. Her main research interests include design and control of power converters, fault diagnosis, and sneak circuit analysis of power electronic systems. Liqiang Yang was born in 1989. He received the B.Sc degree from Xiangtan University, Xiangtan, China, in 2012. He is currently working toward the Master’s degree at the South China University of Technology, Guangzhou, China. His research interests include renewable energy power systems and Z-source converters.

Wolfgang A. Halang received the Ph.D. degree in mathematics from Ruhr-Universität Bochum, Bochum, Germany, in 1976 and the Ph.D. degree in computer science from the Universität Dortmund, Dortmund, Germany, in 1980. Since 1992, he has been the Chair of Computer Engineering with the Faculty of Electrical and Computer Engineering, FernUniversität in Hagen, Hagen, Germany, where he was Dean from 2002 to 2006. He has authored 12 books and some 350 refereed book chapters, journal publications, and conference contributions and has edited 20 books and holds 12 patents. His research interests include hard real-time computing with special emphasis on safety-related systems. Dr. Halang is the founder and was the European Editor-in-Chief of the journal Real-Time Systems, a member of the Editorial Boards of four further journals, and a Codirector of the 1992 NATO Advanced Study Institute on Real-Time Computing.