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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 4, APRIL 2012
A 5 GHz 0.95 dB NF Highly Linear Cascode Floating-Body LNA in 180 nm SOI CMOS Technology Anuj Madan, Member, IEEE, Michael J. McPartlin, Member, IEEE, Christophe Masse, William Vaillancourt, and John D. Cressler, Fellow, IEEE
Abstract—A 5 GHz CMOS LNA featuring a record 0.95 dB noise-figure is reported. Using an inductively-degenerated cascode topology combined with floating-body transistors and high-Q passives on an SOI substrate, record noise figure and superior linearity performance at 5 GHz are obtained. The low-noise amplifier (LNA) achieves up to 11 dB of gain while consuming 12 mW dc power, and is capable of supporting 802.11a WLAN applications. The impact of SOI body-contact on the LNA RF performance is described and linked to improved intermodulation performance. Index Terms—Intermodulation distortion, linearity, low-noise amplifier (LNA), radio-frequency integrated circuits (RFICs), system-on-chip (SoC) CMOS, WLAN.
I. INTRODUCTION
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IGH data rate wireless local area networks (LAN) have fueled the rapid growth of portable electronics. To keep the overall solution cost of portable devices low, the wireless transceiver should be highly integrated with the baseband as a system-on-chip (SoC) solution, preferably using a low-complexity CMOS process [1]. Due to the scaling-induced reduction in supply voltage, it has become increasingly difficult to integrate the RF front-end on the same chip with the digital baseband circuits, while also obtaining the required RF performance. As a result, “front-end modules” are typically used, which incorporate performance-critical blocks such as the RF switch and the low-noise amplifier (LNA) on the receive side, and the power amplifier (PA) on the transmit side [2]. In a typical radio receiver front-end, the LNA is one of the key components since it dominates the radio sensitivity. The LNA design involves tradeoffs between noise-figure (NF), gain, power dissipation, input matching, and harmonic content in the output signal. Adding in progressively lower power dissipation constraints inherent to battery-powered portable applications, a primary challenge in LNA design is achieving simultaneous noise and input matching Manuscript received May 09, 2011; revised September 27, 2011; accepted February 02, 2012. Date of publication March 19, 2012; date of current version April 11, 2012. A. Madan and C. Masse are with Skyworks Solutions, Inc., Woburn, MA 01801 USA (e-mail:
[email protected]). M. J. McPartlin and W. Vaillancourt are with Skyworks Solutions, Inc., Andover, MA 01810 USA. J. D. Cressler is with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250 USA. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LMWC.2012.2187882
at any given amount of power dissipation. Moreover, the amplifier’s compression point requirement also imposes a limitation on the LNA transistor size, making the simultaneous noise and input match even more difficult to achieve in practice. An integrated 5 GHz LNA implemented in floating body SOI CMOS technology is described in this letter. The active silicon layer is isolated from the substrate by buried-oxide and is surrounded by shallow-trench isolation on all sides. The buried oxide layer combined with the high-substrate resistivity decrease substrate noise injection by providing isolation from the substrate. Due to the low-loss dielectric substrate, SOI inductors have higher self-resonant frequency and quality factor than those fabricated on bulk silicon. In this work, the SOI CMOS technology, originally intended for RF 0.18 switch applications [3], allows one to achieve sub-1.0 dB NF for the 5 GHz LNA. This work reports state-of-the-art noise performance, linearity and improved LNA figures-of-merit for silicon-based 5 GHz LNAs targeting WLAN applications.
II. DESIGN OF THE CMOS LNA The schematic diagram of the proposed LNA is shown in Fig. 1. The LNA employs a cascode topology to realize the required gain and provide isolation between the receive port and the antenna. The inductive matching elements are a combination of bondwires and on-chip inductors, and the capacitive elements are implemented as on-chip MIM capacitors. The isolated SOI substrate enables high-Q inductors to minimize the loss through matching network. The inductively-degenerated LNA can simultaneously achieve minimum NF, input impedance matching, and maximum transconductance gain. The input impedance of the inductively degenerated LNA can be expressed as (1) where is the device transconductance and is the intrinsic gate-to-source capacitance of transistor M1. To match the input impedance to 50 , the imaginary part of the impedance can be eliminated by resonating and at an operating frequency of 5 GHz. The real part of the input impedance is shown as
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MADAN et al.: 5 GHZ 0.95 DB NF HIGHLY LINEAR CASCODE FLOATING-BODY LNA
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Fig. 1. Circuit schematic of the inductively-degenerated cascode LNA.
Fig. 3. S-parameters of floating-body and body-contacted LNA with integrated input and output matched to 50 .
Fig. 2. Die photograph of the fabricated LNA.
The inductors used are 0.4 nH for Ls, 3.7 nH for Lg, and 2.2 nH for load inductor; the simulated quality factors, based on electromagnetic simulations at 5 GHz are 7.8, 22.7, and 20.2, respecis chosen to ensure unconditively. The value of resistance tionally stable operation of the LNA up to 15 GHz. Transistors wide with a minimum gate length M1 and M2 are sized 128 of 0.18 .
III. EXPERIMENTAL RESULTS To validate the design and probe the impact of various techSOI nology options, the LNA has been fabricated in a 0.18 CMOS process, with both floating-body and body-contacted FETs. The die photograph of the proposed LNA is shown in Fig. 2. The active die area of the fully integrated LNA (excluding the pads). On-chip MIM is capacitors serve to decouple supply. All measurements were performed on a FR-4 board after mounting the die directly on the board. The measured S-parameters of the floating-body LNA are plotted in Fig. 3. Due to the combination of the on-chip matching network and the bond-wire inductance, the input return loss is 33 dB at 5 GHz, while the output return loss is 13 dB at 5 GHz. A small-signal gain of 11 dB at 5 GHz is obtained with a supply voltage of 1.5 V and total current of associated 8 mA. Due to additional input capacitance with the body-contacted FET, a slightly different inductor value at the input gives an input return loss of 22 dB, as shown in Fig. 3.
Fig. 4. De-embedded NF of the LNA.
The gain of the body-contacted LNA biased at the same current is reduced to 9.3 dB, primarily because of lower transconof the body-contacted device as compared to the ductance floating body device. is measured across A 0.95 dB NF with an error of five samples at room-temperature for the floating-body LNA at 5 GHz, as shown in Fig. 4. When the body terminal of the FETs is tied to its source terminal in the body-contacted LNA, the increased gate resistance due to the polysilicon abutting the body-contact degrades the NF to 1.9 dB at 5 GHz. Power handling capability of the LNA is critical for WLAN applications in order to avoid LNA compression and preserve the modulated signal received at the front-end. The input 1 dB for the LNAs was measured to be compression point , as shown in Fig. 5(a). A two-tone test with equal power levels at 5.000 GHz and 5.001 GHz was performed to measure the input third-order intercept point (IIP3), as shown in Fig. 5(b). The floating-body LNA has an IIP3 of 5 dBm while the body-contacted LNA has an IIP3 of 6.5 dBm. for a body-conMinimum-achievable noise-figure tacted device is 1 dB higher than the floating-body device, as
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dB) to the dc power consumption (in mW), which is more commonly used for comparing low-power LNAs. Furthermore, it can be expanded to include the NF, IIP3, and operating frequency (fc) as follows [9]. A larger FOM is better in all cases
Fig. 5. (a) Measured input P compression point, and (b) comparison of measured harmonics and IIP3 of the LNAs.
A comparison between the present LNAs and other recently published LNAs is presented in Table I [4]–[9]. It should be noted that all of the LNAs shown are fully integrated without off-chip components. By achieving a 0.95 dB NF while consuming 12 mW, this LNA exhibits the lowest NF and highest . Furthermore, the proposed LNA also meets the stringent wireless LAN standards demanding high linearity and powerhandling capability for the 802.11a/n standard. IV. CONCLUSION
Fig. 6. Simulated NF vice.
and extracted R comparison of the LNA input de-
TABLE I PERFORMANCE COMPARISON BETWEEN RECENTLY PUBLISHED LNAS
We have presented a fully-integrated 5 GHz LNA for 802.11a/n WLAN applications. This state-of-the-art LNA features a NF below 1.0 dB and has 11 dB power gain, while consuming 12 mW of power and maintaining an input return loss of 33 dB. The measured input 1 dB compression point at , while IIP3 is 5 dBm. The body-contacted 5 GHz is FET LNA performance is compared with the floating-body LNA. Due to the additional polysilicon gate resistance, the body-contacted FET based LNA is seen to have higher NF. REFERENCES [1] M. Zargari et al., “A dual-band CMOS MIMO radio SoC for IEEE 802.11n wireless LAN,” IEEE J. Solid State Circuits, vol. 43, no. 12, pp. 2882–2895, Dec. 2008. [2] C.-W. Huang et al., “A 5 5 mm highly integrated dual-band WLAN front-end module simplifies 802.11 a/b/g and 802.11n radio designs,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2007, pp. 665–668. [3] A. Botula et al., “A thin-film SOI 180 nm CMOS RF switch technology,” in Proc. IEEE Topical Meeting Silicon Monolith. Integr. Circuits RF Syst., Jan. 2009, pp. 1–4. [4] J. Borremans, S. Thijs, P. Wambacq, Y. Rolain, D. Linten, and M. Kuijk, “A fully integrated 7.3 kV HBM ESD-protected transformerbased 4.5–6 GHz CMOS LNA,” IEEE J. Solid State Circuits, vol. 44, no. 2, pp. 344–353, Feb. 2009. [5] F. Gianesello, D. Gloria, C. Raynaud, and S. Boret, “5 GHz 1.4 dB NF CMOS LNA integrated in 130 nm high resistivity SOI technology,” in Proc. Int. Symp. Integr. Circuits, Sep. 2007, pp. 96–99. [6] C.-P. Chang, J.-H. Chen, and Y.-H. Wang, “A fully integrated 5 GHz low-voltage LNA using forward body bias technology,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 3, pp. 176–178, Mar. 2009. [7] K. Han, J. Gil, S.-S. Song, J. Han, H. Shin, C.-K. Kim, and K. Lee, “Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2 GHz low noise amplifier,” IEEE J. Solid State Circuits, vol. 40, no. 3, pp. 726–735, Mar. 2005. [8] M. Kang, I. M. Kang, Y. H. Jung, and H. Shin, “Separate extraction of gate resistance components in RF MOSFETs,” IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1459–1463, Jun. 2007. [9] D. Linten et al., “A 5 GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS,” IEEE J. Solid State Circuits, vol. 40, no. 7, pp. 1434–1442, Jul. 2005.
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illustrated in Fig. 6. This is primarily attributed to the higher gate-electrode resistance for body-contacted device, which is independent of frequency [8]. To evaluate the performance of the LNAs, different figure-ofis the ratio of the gain (in merit (FOM) are often used.
