(TLP) current [11], corresponding to 2 kV HBM stress. Further, it has a power consumption of 9.7 mW, a power gain of 13.3 dB, and a noise figure of 2.9 dB, while ...
A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS D. Linten1, S. Thijs, M. I. Natarajan, P. Wambacq2, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Donnay and S. Decoutere Inter-university Micro-Electronics Center (IMEC) Kapeldreef 75, B-3001, Leuven, Belgium 1 also PhD student at the Vrije Universiteit Brussel, department ELEC-ETRO 2 also lecturer at the Vrije Universiteit Brussel
Abstract A 5.5 GHz fully integrated low-power ESD-protected lownoise amplifier (LNA), designed and verified in a 90 nm RF CMOS technology, is presented for the first time. This 9.7 mW LNA features a 13.3 dB power gain with a noise figure of 2.9 dB, while maintaining an input return loss of −14 dB.
Vbias MESD
MESD CDEC
CDEC Lload R M2
RFIN
C1
RFOUT
Lg
Keywords: 90 nm, RF CMOS, LNA, and ESD
M1 Cc
Cpad
Introduction Several emerging applications for portable electronic devices are being introduced primarily due to the availability of high data rate wireless local area networks. While classic CMOS technology nodes were previously not seriously considered for RF applications, the deep sub-micron technologies could offer an alternative solution and designer freedom. For instance, in the 90 nm CMOS technology node, transit frequencies well over 100 GHz has been achieved [1], and the commercial manufacturing options are increasingly becoming available. However, with downscaling also the maximum allowed voltage over transistors decreases, placing severe restrictions on analog design options. Recently, the realization of a 100 GHz Voltage-Controlled Oscillator (VCO) in 90 nm CMOS [2] has put CMOS in the mm-wave design. The design of a 5 GHz LNA and VCO [3][4] validated this technology node for low-voltage low-power, high performance RF frond-ends. Further, with the decrease of gate oxide thickness, CMOS circuits get more sensitive to stress from electrostatic discharge (ESD), e.g. by contact with human body. In this sense, circuits that are connected to the outside world via their inputs are usually most exposed to ESD stress. In RF systems, the LNA is usually connected to the outside world through the antenna. In addition, it is one of the most critical building blocks in any RF front-end. Therefore, the design and validation of the nominal performance and ESD robustness in state-of-the-art CMOS technologies is highly relevant. In this paper, the design and verification of a 5 GHz CMOS LNA with ESD protection in a 90 nm RF CMOS technology is presented for the first time. This LNA is protected against ESD up to 1.4 A Transmission Line Pulse (TLP) current [11], corresponding to 2 kV HBM stress. Further, it has a power consumption of 9.7 mW, a power gain of 13.3 dB, and a noise figure of 2.9 dB, while maintaining an input return loss of –14 dB. The input 1 dB compression point is -11.5 dBm, the third-order input referred intercept point (IIP3) is –2.7 dBm, both at 5.5 GHz.
VDD
LESD
Cpad
C2 Ls
LESD
Rpad
Rpad
Fig. 1 ESD-protected LNA schematic (core LNA circuit within dotted box)
This paper is organized as follows: the 90 nm RF CMOS technology and RF modeling approach used in this work is described in the next section. The LNA architecture and circuit design aspects in conjunction with ESD protection are described in section 3. Section 4 describes the measurement results, which are then compared to published data on similar, fully integrated 5 GHz LNAs in section 5. Technology The LNA has been fabricated in the IMEC 90 nm RF CMOS process on p-type 20 Ω.cm Si substrate with five-level copper interconnect structure. Passive components including high-quality MIM capacitors and inductors are available in this process. The minimum physical gate length of the MOSFETs can be as low as 70 nm with an effective oxide thickness of 1.5 nm and a threshold voltage (VT) of 0.3 V for the NMOS transistor (−0.3 V PMOS). The maximum supply voltage is 1.2 V. The NMOS transistor can achieve a state-ofthe-art gm, fMAX and fT, of 1250 mS/mm, 200 GHz and 150 GHz, respectively [3]. In order to design the LNA in this technology, MOS Model 11 parameters [5] have been used, based on extraction from a previous digital 90 nm CMOS process [6]. Circuit design and ESD protection A cascode stage topology LNA [7] with ESD protection (see Fig. 1) has been used as technology demonstrator. Both the input and output are matched to 50 Ω. By using a single
Gain and reverse Isolation [dB]
50 40
-S
12
30 20 10
S
21
0 -10 2
3
4
5 6 7 Frequency [GHz]
8
9
Fig. 3 Measured power gain and reverse isolation (S21 and S12, respectively).
0 Input and outout reflection [dB]
stage, power is saved and degradation of linearity is prevented. The power-constrained noise optimization technique by Shaeffer et al. [7], including the impact of the non-quasi-static input resistance [8], has been used to get an initial estimation of the aspect ratio and overdrive voltage of M1. The input and output nodes of the LNA are protected against ESD by the use of inductors (LESD) between these nodes and the ground. These inductors shunt away the hazardous ESD current from the core LNA circuit. Grounded gate NMOS transistors, typically used as ESD protection devices, are used as power clamps (MESD). In this way, all possible pin combinations are protected against ESD as required from ESD reliability point of view. More details on the ESD protection behavior can be found in [9]. At resonance, the ESD inductor compensates leftover parasitic capacitances (RF pad, decoupling capacitor Cc…). Similar approaches have been published before in 0.25 µm CMOS, however using only simulations and without any silicon verification [10]. Moreover, in that work off-chip components and the on-chip ESD inductor were integrated in the matching network. In this work, the ESD on-chip inductor has been added after the design of the core LNA circuit, minimizing the impact on the LNA performance. In other words, this LNA also operates well when LESD is omitted, as will be illustrated further with the LNA’s noise figure measurement results. Finally, capacitances CDEC are used for power supply decoupling.
-5 S -10
22
-15 -20 -25 -30 S
-35 -40 2
11
3
4
5 6 7 Frequency [GHz]
8
9
Layout Fig. 2 shows the micrograph of the LNA. The circuit area is 940 x1000 µm2. Both the input NMOS M1 and cascode NMOS M2 have an aspect ratio of 110 µm/90 nm. The multifingered transistors have their gates contacted on both sides in order to reduce the noise contribution from the gate resistance. All inductors are implemented on-chip with a grounded patterned poly-shield. The top 2 copper metal patterns were shunted with vias for the inductors in order to create a thick top metal level of approximately 1.3 µm. The inductors used are: 0.4 nH for Ls, 4.3 nH for LG, and 1.1 nH as load inductor, the measured quality factors (Q) at 5 GHz are 8.8, 7, and 7.8. The ESD inductors at input and output nodes have an inductance value of 3 nH, with a Q of 6.5 at 5 GHz. The chosen value is a compromise between noise figure degradation, input matching and ESD robustness of the LNA. VBIAS
VDD
CDEC CDEC
Lload M1, M2
RFIN CC
C2 C1
LG LS
LESD Fig. 2 LNA micrograph
RFOUT
LESD CDEC
Fig. 4 Measured input and output reflection coefficients (S11 and S22, respectively).
Experimental results The LNA has been measured on wafer. The gain with the LNA drawing 8.1 mA from a 1.2 V supply voltage is 13.3 dB at 5.5 GHz, and 13.4 dB at the peak (5.43 GHz), as shown in Fig. 3. The 3-dB bandwidth is 1350 MHz (4.68-6.03 GHz); the 1-dB bandwidth is 691 MHz (5.035-5.726 GHz). The reverse isolation for the LNA is approximately –30 dB within the bandwidth. Further, an input reflection of –14.2 dB (= S11) is measured at 5.5 GHz (Fig. 4). A small upward shift in frequency is observed in the S11 curve, with a minimum return loss of −38 dB at 5.99 GHz. This is due to an inaccurate model of the source degeneration inductor, as proven by re-simulations with updated models. However, still a good input matching is obtained over the entire operation 3dB bandwidth of the LNA: a reflection coefficient from –6.15 at 4.68 GHz to –33 dB at 6.03 GHz. An output reflection coefficient of –19 dB is measured at 5.5 GHz, and a minimum return loss of –21.7 dB at 5.46 GHz, as shown in Fig. 4. An output reflection below -4 dB is obtained over the entire 3-dB bandwidth of the LNA.
1-dB compression point [dBm]
-8
3.5 ESD-protected LNA 3
2.5
2 5
LNA without ESD protection
5.2
5.4 5.6 Frequency [GHz]
5.8
6
Fig. 5 Influence of ESD protection on the (measured) LNA noise figure (50 Ω).
The noise figure of the ESD protected LNA at 5.5 GHz, in nominal operation, is 2.95 dB, as shown in Fig. 5. The minimum noise figure of 2.9 dB occurs at 5.2 GHz. An identical LNA, but without the ESD-inductors, was also measured at the same power consumption. The noise figure decreased with about 0.25 dB, because of absence of the ESD inductor at the input. In order to investigate the nonlinear behavior of the LNA, the 1-dB compression point is measured by sweeping the RF power of the applied signal. At 5.5 GHz the compression point occurs at –11.5 dBm input power as shown in Fig. 6. The compression point over the entire operating range is shown in Fig. 7. The measurements to extract the third–order input referred intercept point (IIP3) are shown in Fig. 8. An IIP3 of –2.7 dBm has been obtained. These results demonstrate that a high dynamic range and a good linearity have been obtained in this design. The Transmission Line Pulse (TLP) [11] technique has been used to characterize the ESD robustness of the LNA. TLP pulses up to 1.4 A were applied at the input, positive with respect to ground, and no RF degradation was observed after ESD stress. This level corresponds to about 2kV Human Body Model (HBM) ESD protection. The power clamps can withstand up to 1.6 A TLP, corresponding to 2.5kV HBM.
Output power [dBm]
5 1 dB
0 -5 -10
-8.5 -9 -9.5 -10 -10.5 -11 -11.5 -12 5
5.2
5.4 5.6 Frequency [GHz]
5.8
6
Fig. 7 Measured 1-dB compression point over the LNA’s operating range. 20 0 Output power [dBm]
Noise figure 50 Ω [dB]
4
5.5 GHz
-20 -40 5.6 GHz -60 -80 IIP3 = -2.7 dBm
-100 -40
-30
-20 -10 Input power [dBm]
0
10
Fig. 8 Measurement of third-order input referred intercept point (IIP3) (two-tone test with RF input powers at 5.5 GHz and 5.55 GHz).
State-of-the-Art To compare the performance of our LNA to other designs, different figures of merit (FOM) that are common in literature, are used. The performance summary of the LNA, and a comparison with other fully integrated CMOS LNAs operating in the 5 GHz band, are shown in Table 1. The FOMs do not include the ESD performance. However, to the authors’ knowledge, this work is the first published fully integrated 5.5 GHz LNA with ESD protection. A first figure of merit (FOM1) for low-power RF amplifiers is the ratio of the gain in dB to the DC power consumption. The LNA described in this paper has a value of 1.38 for this FOM. This high value is achieved due to use of 90 nm CMOS technology. Further, this FOM can be extended to include the noise figure of the LNA as follows
-15 -11.5 dBm -20 -30
-25
-20 -15 Input Power [dBm]
FOM 2 [mW −1 ] = -10
Fig. 6 Measurement of 1-dB compression point at 5.5 GHz
-5
Gain[ abs ] ( NF − 1)[abs ] ⋅ PDC [mW ]
(1)
Brederlow, et al, [12] proposed a FOM that also includes IIP3, and operating frequency fC as follows FOM 3[ − ] =
Gain[abs ] ⋅ IIP3[mW ]. f c [GHz ] ( NF − 1)[abs ] ⋅ PDC [mW ]
(2)
Table 1 Summary of measured LNA performance and state-of the-art fully integrated 5 GHz LNAs References
Gate length fc NF Vdd Pdc Gain 3-dB BW [GHz] [dB] [V] [mW] [dB] [MHz] [µm] This Work 0.09 5.5 2.9 1.2 9.72 13.45 1350 W. Jeamsaksiri [3] 0.09 5.5 2.7 1.2 9.72 13 1485 D. Linten [4] * 0.09 5.5 3.6 0.6 2.1 11.2 1259 T. K.K. Tsang [16] 0.18 5.8 2.5 1 22.2 13.2 * 0.18 5.8 2.68 0.7 12.5 7 H.W. Chiu [13] 0.25 5.2 3 2 10 10 ** 0.25 5.2 2.17 2 10 11 E. H. Westerwick [14] 0.25 5.25 2.8 3 12 14.4 840 *** 0.25 5.25 2.5 3 24 16 840 Mukherjee [15] 0.25 5.5 4.8 2 10 8 -
S11 [dB] -16.2 -11.7 -28 -5.3 -7.1 -30 -45 -11.5 -12.3 -23.5
S22 [dB] -14.2 -14 -14 -10.3 -12.3 -12.3 -11.9 -10.3
S12 P1dB Input IIP3 FOM1 FOM2 FOM3 [dB] [dBm] [dBm] [dB/mW] [1/mW] [-] -30 -11.5 -2.7 1.38 0.51 1.51 -30 -11.2 -3.25 1.34 0.53 1.39 -33 -17.5 -8.6 5.33 1.34 1.02 -14 0.59 0.26 -9 0.56 0.21 -35 -8.3 0.3 1.00 0.32 1.77 -36 -8.3 0.3 1.10 0.55 3.05 -25.5 -11 -1.5 1.20 0.48 1.80 -26.4 -11.7 -1.5 0.67 0.34 1.26 -30 -1.5 10 0.80 0.12 6.84
ESD-Protection [kV] HBM 2 -
* : Folded cascode LNA topology ** : Wafer thinned to 20 µm *** : Differential circuit, the mentioned power consumption is its single-ended equivalent
From Table 1, it is clear that the FOMs of the CMOS LNA design described in this paper are among the best reported values of fully integrated 5 GHz band LNAs. Only H.W. Chiu, et al. [13] reported a higher FOM2 value for their LNA. Their remarkably low noise figure of 2.17 dB has been reached by applying a non-standard wafer thinning technique. The LNA reported by D. Linten, el al. [4] was optimized for low-power low-voltage operation, resulting in a high FOM1 and FOM2. Conclusions
A 5.5 GHz fully integrated, low-power LNA with ESD protection has been designed and verified experimentally in a 90nm RF CMOS technology. This state-of-the-art LNA features a power consumption of 9.7 mW, a 13.3 dB power gain with a noise figure of 2.9 dB, while maintaining an input return loss of –14 dB. The 3-dB bandwidth is 1.35 GHz (641 MHz 1-dB bandwidth). The input 1 dB compression point at 5.5 GHz is –11.5 dBm, the third-order input-referred intercept point (IIP3) is –2.7 dBm. To the authors’ knowledge, this work is the first published fully integrated 5.5 GHz LNA with ESD protection. The use of 90 nm CMOS has been found suitable for low power, high performance RF design around 5 GHz. The measurement results demonstrate that low noise figures and low power consumption can be achieved simultaneously with on-chip input and output matching networks and ESD protection. Acknowledgements
The authors would like to thank EU IMPACT IST-200030016 project and the Flemish IWT for their support, the IMEC PLINE for processing of the wafers, Andries Scholten from Philips Eindhoven for MOS Model 11 parameter extraction, Luc Pauwels for measurement assistance, and Johan Mees for all the design environment support. References [1] V.C. Venezia, A. J. Scholten, C. Detcheverry, H. Boots, W. Jeamsaksiri, L.Grau, D.B.M. Klaassen, R.M.D.A Velghe1, R. J. Havens, and L.F. Tiemeijer, “The RF potential of highperformance 100nm CMOS technology”, ESSDERC 2002 conf. Proceedings, p. 491-494. [2] L. M. Franca-Neto, R. E. Bishop, B. A. Bloechel, “A 64 GHz and 100GHz VCOs in 90 nm CMOS Using Optimum Pumping Method,” ISSCC 2004 conf. Proceedings, pp. 444-445. [3] W. Jeamsaksiri, A. Mercha, J. Ramos, D. Linten, S. Thijs, S. Jenei, C. Detcheverry,P. Wambacq, R. Velghe, S. Decoutere,”
Integration of a 90nm RF CMOS technology (200GHz fmax 150GHz fT NMOS) demonstrated on a 5GHz LNA”, accepted for publication 2004 symposium on VLSI circuits, Honolulu, USA. [4] D. Linten, L. Aspemyr, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Thijs, R.Garcia, H. Jacobsson, P. Wambacq, S. Donnay and S. Decoutere,” Low-power 5 GHz LNA and VCO in 90 nm RF CMOS”, accepted for publication 2004 symposium on VLSI circuits, Honolulu, USA. [5] www.semiconductors.philips.com/Philips_Models [6] D. Linten, S. Thijs, W. Jeamsaksiri, M. I. Natarajan, V. De Heyn, V. Vassilev, G. Groeseneken, A.J. Scholten, G. Badenes, M. Jurczak , S. Decoutere, S. Donnay and P. Wambacq, “Design-driven Optimisation of a 90 nm RF CMOS Process by use of Elevated Source/Drain”, ESSDERC 2003 conf. Proceedings, pp 43-46. [7] D. K. Shaeffer and T. H. Lee, “A 1.5–V 1.5-GHz CMOS: Low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745– 759, May 1997. [8] J. Chen, and B. Shi, “ Impact of Intrinsic Channel Resistance on Noise Performance of CMOS LNA”, IEEE Electron Device Letters, vol. 23, No.1, January 2002, pp. 34-36. [9] S. Thijs, M.I. Natarajan, D. Linten, T. Daenen, V. Vassilev, R. Degraeve, P. Wambacq, G. Groeseneken, “Implementation of Inductor Based ESD Protection for 5.5 GHz LNA in 90 nm RF CMOS – Concepts, Constraints and Solutions,” accepted for publication EOS/ESD symposium 2004. [10] P. Leroux, and M. Steyaert, “ High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection”, Electronic Letters, vol. 37, no. 7, March 2001, pp. 467-469. [11] B. Keppens et al., “Significance of the failure criterion on transmission line pulse testing,” Microel. Reliability 42, 2002, pp. 901-907. [12] R. Brederlow, W. Weber, J. Sauerer, S. Donnay, P. Wambacq, and M. Vertregt, “A mixed signal design roadmap”, IEEE Design & Test of Computers, Vol. 18, No. 6, Nov.-Dec. 2001 pp. 34 – 46. [13] H.W. Chiu, and S.S. Lu, ”A 2.17 dB NF, 5 GHz Band Monolithic CMOS LNA with 10 mW DC Power Consumption”, VLSI Circuits symposium 2002 conf. Proceedings, pp. 226-229. [14] E. H. Westerwick,” A 5 GHz Band Low Noise Amplifier with a 2.5 dB Noise Figure” IEEE International symposium on VLSI Technology, Systems, and Application conf. Proceedings,, pp. 224-227. [15] D. Mukherjee, J. Bhattacharjee, S. Chakaraborty, and Joy Laskar,” A 5-6 GHz fully integrated CMOS LNA for a dualband WLAN Receiver”, RAWCON 2002 conf. Proceedings,, pp. 213-215.
[16] T. K. K. Tsang, and M. El-Gamal,” Gain and Frequency Controllable Sub-1V 5.8 GHz CMOS LNA.”, ISCAS 2002 conf. Proceedings,, Vol. 4.,pp.795-798, May 2002.
