A 59GHz-to-67GHz 65nm-CMOS High Efficiency Power Amplifier

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Abstract—A two-stage single-ended Power Amplifier (PA) is fabricated for the 60GHz Wireless Personal Area Network. (WPAN) standard. It is based on the ...
A 59GHz-to-67GHz 65nm-CMOS High Efficiency Power Amplifier Sofiane Aloui, Eric Kerherve

Robert Plana

Didier Belot

IMS laboratory, UMR CNRS 5218 University of Bordeaux 33405 Talence Cedex, France Email: sofi[email protected]

LAAS-CNRS University of Toulouse Toulouse, France Email: [email protected]

STMicroelectronics Central R&D 1 Crolles, France Email: [email protected]

I. I NTRODUCTION The 7GHz band around 60GHz is free of use and fulfills the uncompressed HD data transfer for indoor WPAN applications. A 65nm CMOS technology provided by STMicroelectronics is used. Indeed, emerging CMOS technologies enable operating at millimeter Wave (mmW) frequencies while being competitive against IIIV technologies.

VDD Vg

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R (10 Ÿ) ZL R-L (10+j18 Ÿ)

R-L DC Bias point

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The difficulty in designing mmW CMOS PA consists in providing a maximum of output power (Pout ) with a reasonable PAE. Hence, the optimum load impedance (Zopt ) should be determined according to constant circles or load line characterizations rather than presenting the output conjugated ∗ impedance (Zout ) which optimizes only the gain. Fig. 1 illustrates the behavior of the transistor for two different load impedances (ZL ). When ZL is purely resistive, the load line is quasi-ideal. The slope of the line represents the real part of RL . The second ZL has the same real part and has an imaginary part to compensate the output capacitance of the power transistor. In this case, the load line represents a two-dimensional curve forming an ellipse. This is due to an important phase difference between drain current and voltage. The voltage and current swings are increased compared to the case when ZL is resistive. However, the area of the ellipse represents the reactive energy. A high area lowers the PAE and increases the transistor stress [1]. This paper presents experimental results highlighting the effect of the load impedance on the PA performances. It is organized as follows:

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A

Pin 60GHz

Ids (A)

Abstract— A two-stage single-ended Power Amplifier (PA) is fabricated for the 60GHz Wireless Personal Area Network (WPAN) standard. It is based on the 65nm CMOS technology from STMicroelectronics. The PA is biased in class A and uses distributed elements to perform impedances matching. Sparameters and large signal simulations are validated by measurement results. Load pull measurements are performed to get the best operation of the PA. It achieves a saturated output power (Psat ) of 12dB and offers Power Added Efficiency (PAE) of 15%. The die area is 0.29mm2 with pads.

Vds (V) Fig. 1.

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Load line shapes for different ZL

Section 1 describes the design of a 65nm CMOS 60GHz PA. Section 2 shows the PA performances in small and large signal domains. Section 3 details the PA characterization using load pull measurements. It consists in varying the load impedance to find the best performances of the PA. The load pull measurements enable to quantify the sensitivity (or robustness) of the power performances. Indeed, not all of them are affected (or improved). Finally, the PA is compared with PAs designed within the state of the art.

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Fig. 2.

Schematic of the 60GHz single-ended PA in 65nm CMOS technology

II. P OWER A MPLIFIER DESIGN The PA is a single-ended two-stage common source structure. The driver and the power transistors are sized to (1μm, 48, 1) and (1μm, 90, 1) respectively. Both of them are biased in the same conditions (Vgs , Vdd ) = (0.95V, 1.2V ) to have a maximum gm . The two stages are biased by Transmission lines (T-lines) that also feature the matching since a RF-short is presented to the targeted length of the T-line. The short is made thanks to MiM capacitors of 3pF. MiM capacitors are exclusively used to perform DC blocking and supply decoupling. Their values are set to roughly 150fF

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and 3pF respectively. The CPW topology is preferred and adopted for the design. Indeed, contrarily to microstrip lines, CPW T-Lines achieve easily high impedances (≥ 50Ω) keeping a correct quality factor (≈ 12). The major drawback of using CPW instead of MS is the misreading of the local resistance of the substrate (dope profile, process) whereas the MS line design and analysis ignore completely the substrate. Consequently the 50Ω CPW line dimensions are set to (widthline, gap) = (10μm, 6.5μm). It exhibits an attenuation of 1.6dB/mm at 60GHz. The input and output impedances are matched to 50Ω. Thanks to the absence of serial lines, the PA takes place within a silicon area of 0.29mm2 with pads. Fig. 2 and Fig. 3 show the schematic and the die photography of the PA. The ground of the circuit is distributed in all metal layers to reduce significantly the resistive and inductive effects of the ground connections. More details concerning T-lines and interconnect elements characterizations are detailed in [2]. Vg1

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A. Small signal performances G

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Fig. 3. Die photography of the 60GHz single-ended PA in 65nm CMOS technology

Measurements are carried out with an Agilent E83612 Vector Network Analyzer (VNA) to measure S-parameters from 10MHz to 110GHz. The simulated and measured Sparameters are reported in Fig. 4. The PA reaches a maximum of 13.2dB at 63GHz. This PA operates in the desired band and offers a minimum gain of 9.7dB from 59GHz to 67GHz. The input matching exhibits a -32dB return loss whereas S22 is measured to -15dB. The isolation parameter is more than 25dB from DC to 110GHz. The PA offers good performances in terms of matching and gain in the useful band. There is a good agreement between simulation results and measurement results.

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III. P ERFORMANCE IMPROVEMENTS WITH LOAD PULL SETUP

A. Load pull setup and measurements

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Contour Data: |ī| = 0.38 Phase ī = -75.5 Pout (dBm) = 11.45

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Fig. 4. Measured S-parameters at the bias point (Vgs , Vds ) = (0.95V, 1.2V )

B. Large signal performances Large signal simulation and measurement results summarizing the PA power characteristics at 63GHz are exhibited in Fig. 5. The PA is matched to 50Ω at input and output. Thanks to the operation in class A, the PA has a high OCP1 of 9.2dBm and a saturation power of 10.6dBm at 63GHz. The PA has a maximum PAE of 8.9% at 63GHz. In the compression region, the PAE still has a value close to its maximum. This characteristic is targeted in the context of WPAN applications due to the use of the OFDM signal.

Zopt determination to deliver a maximum of Pout at 63GHz

A Focus load pull system operating from 58GHz to 90GHz is used for load pull measurements. At 60GHz, the maximum delivered power is 8dBm which is sufficient to reach the Input Compression Point (ICP1 ) of the PA. To vary load and source of the DUT, two mechanical tuners are used but they can not sweep the overall Smith chart because of high frequency losses. Due to the tuner losses at 63GHz, the Smith chart is not completely covered and limited by a |Γmax | equal to 0.6 (cf. Fig. 6). The optima output impedances of the PA are presented at 63GHz. The real part of the impedance is close to 50Ω while the imaginary part is capacitive. B. Power performances enhancement The power performances are plotted in Fig. 7. Psat , gain and OCP1 are slightly increased while a considerable

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Fig. 5. Measured Pout and PAE at 63GHz at the bias point (Vgs , Vds ) = (0.95V, 1.2V )

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Fig. 7.

Measured Pout , gain and PAE at Zopt

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TABLE I C OMPARISON OF PA S IN 65 NM CMOS TECHNOLOGY FOR 60GH Z ReferenceFrequency [3]-60GHz [4]-58GHz [5]-58GHz [This work-50Ω]-63GHz [This work-LP]-63GHz

[Tech(nm)] [Foundry] [65][IBM] [65][IBM] [65][ST] [65][STM] [65][STM]

Number of stages 1 3 4 2 2

Gain (dB) 4.5 15 13.7 13.2 14

Psat (dBm) 8.5 11.5 14.2 10.6 12

OCP1 (dBm) 6 2.5 12.2 9.2 10

PAE (%) 8.5 11 4.2 8.9 15

Power Consumption (mW) 28 34 425 80 65

FoM(ITRS)

FoM.OCP1

6.1 313 74 84 237

24 564 1201 302 854

The ITRS FoM is used to compare the PAs performances [6]. It takes into account the gain, the PAE, the Ps at and the operating frequency (f ) as given in Eq. 1: F oM = Psat · Gain · P AE · f 2

(1)

Table I exhibits performances of CMOS 60GHz PAs. The ITRS FoM does not consider the OCP1 which reflects the linearity of the PA. Hence, a second FoM is added in Table I. Our work is ranked as one of the best realization since it has a good trade-off between gain, power and efficiency. IV. C ONCLUSION

Load line shapes for (ZS , ZL ) = (50, 50)and(ZSopt , ZLopt )

Fig. 8.

The design of a 65nm CMOS PA is presented. Simulation and measurement results are in good agreement in both small and large signal domains. The PA has a gain, an OCP1 and a PAE of 13dB, 9dB and 8% respectively at 50Ω. Those perfomances are improved by performing load pull analysis. Indeed, changing the load impedance of the PA has a slight impact on the gain, on the linearity and on the capability to provide power. The major impact concerns the DC power cunsumption. Finally, the PAE is enhanced from 8.9% to 15%.

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ACKNOWLEDGMENT The authors acknowledge the foundry support provided by STMicroelectronics. The authors thank Conseil Regional d’Aquitaine for the support of NANOCOM test bench.

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Measured PDC for (ZS , ZL ) = (50, 50)and(ZSopt , ZLopt )

improvement of the PAE is seen. The PAE rises from 8.9% to 15%. This experience highlights the influence of ZL in DC characteristic of the PA consumption and not only in the RF behavior. Indeed, the increase of the DC power consumption is demonstrated by getting a larger area of the ellipse with a 50Ω load impedance (cf. Fig 8). In this context, the PDC varies with Pout and/or Pin and achieves a maximum value of 80mW while it is always close to 65mW when Zopt is presented at the output of the PA (cf. Fig 9).

[1] N. SCHLUMPF, “Adaptation dynamique de la compression d’un amplificateur RF pour des signaux modules en amplitude et en phase”, Ph.D. dissertation, Ecole Polytechnique Federale de Lausanne, 2004. [2] S. Aloui, E. Kerherve, R. Plana, D. Belot, “RF-pad, Transmission Lines and Balun Optimization for 60GHz 65nm CMOS Power Amplifier”, IEEE RFIC Symposium, pp. 211-214, May 2010. [3] A.V. Garcia, S. Reynolds, J.O. Plouchart, “60GHz Transmitter Circuits in 65nm CMOS”, IEEE RFIC Symposium, pp. 641-644, June 2008. [4] W.L Chan, J.R Long, M. Spirito, J.J Pekarik , “A 60GHz-band 1V 11.5dBm Power Amplifier with 11% PAE in 65nm CMOS”, IEEE ISSCC Digest of Technical Papers, pp. 380-381, Feb 2009. [5] A. Quemerais, T. Moquillon, L. Huard, V Fournier, J.M Benech, N Corrao “DC hot carrier stress effect on CMOS 65nm 60 GHz power amplifiers”, IEEE RFIC Symposium, pp. 351-354, May 2010. [6] 2007 “International Technology Roadmap for Semiconductors, 2007 edition.”, http://www.itrs.net/.

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