A 90nm-CMOS, 500Mbps, Fully-Integrated IR ... - Oregon State EECS

0 downloads 0 Views 803KB Size Report
for clock/data recovery (CDR). Occupying 2mm2 die area, the transceiver achieves a maximum data rate of 500 Mbps, energy efficiency of 0.18nJ/b at 500Mbps, ...
A 90nm-CMOS, 500Mbps, Fully-Integrated IR-UWB Transceiver Using Pulse Injection-Locking for Receiver Phase Synchronization Changhui Hu,∗ Patrick Y. Chiang,∗ Kangmin Hu,∗ Huaping Liu,∗ Rahul Khanna,† and Jay Nejedlo



∗ Oregon †

State University, Corvallis, OR 97330, USA Intel DEG group, Hillsboro, OR 97124, USA

Abstract— A fully-integrated, 3.1-5GHz Impulse-Radio UWB transceiver with on-chip flash ADC is designed in 90nm-CMOS. A new scheme for receiver phase acquisition is proposed that uses pulse injection-locking to synchronize the receive clock with the transmitted data, eliminating the need for clock/data recovery (CDR). Occupying 2mm2 die area, the transceiver achieves a maximum data rate of 500 Mbps, energy efficiency of 0.18nJ/b at 500Mbps, and a RX-BER of 10−3 across a distance of 10cm at 125Mbps. Index Terms— Impulse radio (IR), UWB, equalization, injection-locking, transceiver.

I. I NTRODUCTION

AND

M OTIVATION

Impulse-radio systems have received much attention as a possible architecture for UWB transceivers due to the large data bandwidth, low spectral interference with nearby channels. Due to the low emitted power spectral density of -41.3dBm/MHz, impulse radio is especially well suited for low cost, low power and short-range wireless communications[1-6]. A. Conventional Impulse-Radio Receiver Architectures (a)

Vin(fIN )

Digital LNA

X

ADC CDR (PLL)

fLO

(b) LNA

CDR

X

ADC

Pulse Template

Digital CDR

CDR (PHASE) Phase (Adjust)

(c) LNA

ADC

X

Digital CDR

CDR (PHASE)

(d)

LNA

ADC

Digital CDR CDR (PHASE)

Fig. 1.

RX architecture overview

While recent research has demonstrated energyefficiency of impulse-based UWB transmitters [3], [4], the more critical problem lies within the receiver. Conventional IR-UWB receiver architectures are summarized

in Fig. 1: a) direct-conversion receiver using local oscillator multiplier; b) Direct-conversion receiver using pulse template multiplier [6]; c) non-coherent receiver with self-correlation [5]; d) direct over-sampling analog-digital converter (ADC)[7]. The LO direct-conversion architecture is the most common, and is similar to narrowband receiver systems. This approach typically consumes the most power, due to the high frequency of the local oscillator. In addition, due to the large data bandwidth, the lowpass filter is difficult to design, and ADC oversampling is still required to recover the optimal ADC sampling phase. In addition, a CDR is still required, as the local receiver clock may be plesiochronous from the transmitter clock. The pulse-template direct-conversion architecture is well used in coherent IR-UWB RX, but synchronization will be difficult and power consuming. The non-coherent, self-correlating receiver is an attractive option, as it simplifies the pulse-template synchronization. Unfortunately, bit-error rate will increase as the receiver will not be able to discriminate between noise and transmitted data. In addition, the design of a CDR loop is still required, as the demodulated data needs to be phase locked with the local receiver clock. The direct over-sampling ADC method is the most straightforward, as the pulse input is directly quantized by the ADC, moving the demodulation and CDR requirements to the digital baseband. Unfortunately, the power overhead for the over-sampling ADC is extremely expensive, as a multi-gigahertz, medium resolution ADC is necessary for a 3.1-10GHz transmitter bandwidth. One overarching constraint of all of these conventional structures is that some mechanism for synchronizing the receiver sampling clock with the incoming transmitted data is required. Because the eventual goal for IR-UWB systems is several hundred Mbps, the design of an oversampling CDR loop adds both system complexity as well as additional power consumption. B. Proposed Architecture: Receiver Pulse InjectionLocking Phase Synchronization In this work, we present a new receiver phase synchronization method using pulse injection-locking, as shown in Fig. 2. This technique provides several advantages over the previously described architectures. First, no CDR is necessary, as the received local oscillator is injection-locked

Vinj CLK ADC

Vin(fIN)

LNA

Vinj ADC Injection-Locked Recovered CLK CLKADC

VCO Fig. 2.

RX IL VCO

to the incoming pulses, and hence is automatically phasealigned with the transmitted clock. Second, the architecture is inherently a feed-forward system, with no issues with feedback loop stability. The proposed system is similar to a ‘forwarded clock’ receiver approach used for high-speed links which have been shown to be extremely energyefficient[10], but here the receiver sampling clock is locked to the actual incoming transmitted pulses, eliminating any requirement for a separate clock channel. Third, since the receiver clock is now injection-locked and synchronized with the transmitter, the ADC sampling requirements can be severely relaxed and now can run at the actual data rate. This is a significant advantage for power reduction, as a multi-gigahertz, over-sampling ADC is no longer necessary. II. S YSTEM OVERVIEW Transmitter Multi-path Equalization

CK

Ext Data

PRBS

CK

τ1

τ2

ILVCO

4GHz Ref

α

Pulse Window

NRZ→RZ

/N

Pulse Window

+/-

Pulse Window

LNA

/N

+/Transmitter

CK

5

Receiver

ADC Receiver Pulse Injection Locking

Fig. 3.

For some serious multi-path environment, such as computer chassis, multi-path reflections can degrade the receiver BER. In order to reduce the interference from nearby reflection, a multi-path transmitter equalizer is designed that can reduce the two most severe multi-path reflections [8]. Tap1 and Tap2 are delayed version of the main signal, with sign and coefficient control, depending on the actual multi-path channel environment [8]. B. Receiver Pulse Injection-Locking

β

Scan Chain (234 bits)

Phase Shifter

A. Multi-path equalization

CML summation

ILVCO Rx

Tx

bits such as current sources and resonant tank tuning. In the transmitter, OOK modulation is generated from a passive modulator, including a 215 −1 bit Pseudo-RandomBit-Sequence (PRBS) selectable for testing operation. An on-die, 3-5GHz LC-VCO is clock-gated to generate the transmitted pulses, where a pulse shaping control block is integrated to enable tunable pulse widths of 0.4-10ns. In the receiver, the received pulse is amplified by a 2-stage LNA and then directly injected into both the 5 level flash ADC and a 3.4-4.5GHz, injection-locked VCO (IL-VCO). After the receiver VCO is injection-locked and phase synchronized with the transmitted pulses, it is phase shifted and divided down to provide the ADC sampling clock. After the ADC sampling clock is divided down to the same frequency as the incoming data rate, the sampling clock is phase locked and aligned to the peak of the received input pulse, eliminating any requirements for baseband clock/data recovery. Optimally setting the phase position of the ADC sampling clock can be achieved by measuring the BER and building a bath-tub curve, sweeping through all possible phase positions. The 5-level flash ADC is designed using dynamic sense amplifiers with threshold-adjustable, current-steering DACs. The phaseshifter, which enables tunable phase delay of the ADC sampling clock, uses a Glibert-cell, current-summing DAC with a minimum step size of 7ps.

Output (4 bits)

Receiver clock phase acquisition with the received UWB pulses is very critical for achieving low power consumption as discussed in the introduction. It consists of a 2-stage LNA and an ILVCO as in Fig. 4. The proposed receiver clock recovery by using pulse injection-locking from the transmitted pulses, is analogous to sub-harmonic injection-locking. The effective division ratio N can be expressed as:

IR-UWB transceiver architecture

N The proposed IR-UWB transceiver is shown in Fig. 3, consisting of a multi-path equalization transmitter, a pulseinjection-locking receiver with an integrated ADC, an onchip PRBS TX-generator and RX-checker, and a 234-bit scan chain for low-frequency calibration of DC control

= =

fout fout = α · finj · n α · finj · (Wpulse /Tout ) 1 (1) α · finj · Wpulse

Where α is the possibility when data is “1”; finj is the data rate; fout and Tout are the the ILVCO output

ILVCO Rx

Pulse Width: 1ns Amplitude: 160mV

To Phase Shifter

LNA

Vinj

To ADC

Vout-

Vout+

Tx Rx Balun

Cap Bank LNA 2nd Stage

LNA 1st Stage

Rx Pulse width

Rx Pulse width 60

Vinj

Amplitude(mV)

40 20

Fig. 6.

0

-40 0

Transmitted signal and power spectrum

ILVCO

-20

1/finj 2

4

6 8 Time(ns)

10

12

14 vf

Fig. 4.

Receiver injection locking

frequency and period; and Wpulse is the pulse width as in Fig. 4. Similar to [9], the phase noise will degrade 20logN dB compared to the injected signal. From Eq.(1), we can see that increase injection pulse rate or pulse width, will reduce the the phase noise of ILVCO output, because more energy injected. III. M EASUREMENT R ESULTS The 2mm2 IR-UWB transceiver is built in 90nmCMOS, 1.2V mixed-signal technology as shown in Fig. 5. The chip is mounted on a PCB using chip-on-board (COB) assembly with an off-chip, low-speed scan interface through a NIDAQ/Labview module. RMS Jitter 7.6ps

2mm

Fig. 7.

Scan Chain

Current Source

Rx ILVCO

Programmable Divider Phase Shifter

LNA 2nd Stage

EQ

1mm

LNA 1st Stage

PRBS & Data Transit

Data Modulation

Tx ILVCO

ADC

Fig. 5.

Die photo

The measured transmitted signal and its spectrum are shown in Fig. 6. The amplitude of the pulse is 160mVpp, with a nominal pulse width of 1ns. Its frequency spectrum fulfills the FCC UWB spectral mask except for the GPS band, which can be achieved by the addition of a high pass filter. The maximum transmission data rate is 500Mbps. Fig. 7 shows the recovered IL-VCO clock locked to the LNA output, and after phase/data alignment of the pulse

ADC clock and received signal alignment

zero crossing with the ADC sampling clock. With a 1ns pulse width, the recovered clock jitter is 7.6ps-RMS. Fig. 8(a) shows the measured injection-locking range versus varying pulse width and pulse repetition rate. As can be seen, wider pulse width and higher data rate will improve the locking range, as more transmitted pulse energy synchronizes the receiver IL-VCO. Fig. 8(b) shows the measured close-in phase noise, from free running without injection, to pulse repetition frequencies (finj ) 125Mbps, 500Mbps, and sine wave injection. Lower phase noise is exhibited at higher injection rates, as the phase updates occur at a higher frequency, similar to the dynamics in a 1st-order phase-locked loop (PLL). The results also verify Eq.(1), 12dB phase noise difference between 125Mbps and 500Mbps pulse injection is observed. Without pulse injection, the free running VCO shows very large

Injection Locking Range(MHz)

data at 500Mbps.

80

Pulse Width 70

2ns 1.5ns Rx=1ns

60 50

IV. C ONCLUSION A fully integrated single-chip low-power IR-UWB transceiver with ADC in 90nm CMOS is presented. A novel pulse-injection-locking method is used for receiver clock synchronization in receiver demodulation, leading to significant power reduction by eliminating the high power ADC and mixer. The complete transceiver achieves a maximum data rate of 500Mbps, through a 10cm distance, consuming 0.18nJ/bit. And measured BER achieved 10−3 at 125Mbps through 10cm.

40 30 20 10 7.8125

15.625

31.25

62.5

125

250

500

Injection Pulse Rate f (Mbps)

(a) Pulse injection lock range vs. pulse width and pulse rate -50 sine

Phase Noise(dBc)

-60

500Mbps

-70

125Mbps

-80

No-injection

TABLE I

-90

P ERFORMANCE SUMMARY AND COMPARISON

-100 -110 -120

Work

CMOS (nm)

[1]

180

3.1-9

740

6500

1000

4.5

[2]

130

0-0.96

-

110

40

4.52

[3]

130

3.1-5

[4]

90

3.1-5

[5]

90

This

90

-130 -140 4 10

10

5

6

7

10 10 Frequency Offset(Hz)

10

8

10

Energy(pJ/b) Tx Rx

Data Rate (Mbps)

Size (mm2 )

9

(b) Pulse injection locked VCO phase noise vs. pulse rate

Fig. 8.

Frequency (GHz)

Injection locking measurement

phase noise at low frequency offset. While a long-string of empty data transitions would result in loss of phase synchronization, conventional DCbalanced codes such as 8b/10b can limit maximum run length. Transmission using the on-chip PRBS-15 modulator, exhibiting a maximum string of forteen zeros, showed no loss in receiver phase synchronization.

Tx Data

Rx Pulse(LNA Out)

Rx Clock

Rx Data

Fig. 9. Tx data, Rx clock, received pulse and recovered data(500Mbps)

The free-space measurement setup uses two UWB antennas that are placed 10cm away. Fig. 9 shows the transmitted digital data, received pulses after LNA gain, recovered Rx clock, and finally the received demodulated

31

8

47

1100 -

16.7

0.08(w/o pads)

3.1-5

-

2500

16.7

2.2

3.1-5

90

90

500

2

ACKNOWLEDGMENT

This work was funded by NSF-GOALI award #0901883. We thank Intel for gift donations, MOSIS for chip fabrication and Will Bettie for Labview support. R EFERENCES [1] Y. Zheng, et al., “A 0.18µm CMOS 802.15.4a UWB Transceiver for Communication and Localization,” ISSCC Dig. Tech. Papers, pp. 118-119, Feb. 2008. [2] M. Verhelst, et al., “A Reconfigurable, 0.13µm CMOS 110pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Sub-cm Ranging,” ISSCC Dig. Tech. Papers, pp. 250-251, Feb. 2009. [3] D. Lachartre, et al., “A 1.1nJ/b 802.15.4a-Compliant Fully Integrated UWB Transceiver in 0.13µm CMOS,” ISSCC Dig. Tech. Papers, pp. 312-313, Feb. 2009. [4] D. Wentzloff, et al.,“A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 118119, Feb. 2007. [5] F. Lee, et al.,“A 2.5nJ/b 0.65V 3-to-5GHz Subbanded UWB receiver in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 116-117, Feb. 2007. [6] L. Zhou, et al., “A 2Gbps RF-Correlation-Based Impulse-Radio UWB transceiver Front-End in 130nm CMOS,” IEEE RFIC Symp. Dig.,, pp.65-68, June 2009. [7] I.D.O’Donnell, et al., ”A 23mW baseband impulse-uwb transceiver front-end,”VLSI Circuits Symposium, pp. 200, Jun. 2009. [8] C. Hu, et al., “Transmitter Equalization for Multipath Interference Cancellation in Impulse Radio Ultra-Wideband(IR-UWB) Transceivers,” VLSI-DAT International Symposium,pp.307-310, April 2009. [9] J. Lee, et al., “Subharmonically Injection-Locked PLLs for UltraLow-Noise Clock Generation” ISSCC Dig. Tech. Papers, pp. 92-93, Feb. 2009. [10] K.Hu, et al., ”A 0.6mW/Gbps, 6.4-8.0Gbps Serial Link Receiver Using Local, Injection-Locked Ring Oscillators in 90nm CMOS”VLSI Circuits Symposium, pp. 46-47, Jun. 2009.