A Balanced Capacitive Threshold-Logic Gate - Springer Link

Analog Integrated Circuits and Signal Processing, 40, 61–69, 2004 c 2004 Kluwer Academic Publishers. Manufactured in The Netherlands.

A Balanced Capacitive Threshold-Logic Gate ´ ´ JOSE´ FERNANDEZ-RAMOS ´ ´ JAVIER LOPEZ-GARC IA, AND ALFONSO GAGO-BOHORQUEZ Departmento de Electrónica, Universidad de Málaga, Bulevard Louis Pasteur s/n, 29071 Málaga, Spain E-mail: [email protected]

Received October 22, 2001; Revised May 1, 2003; Accepted May 13, 2003

Abstract. In this paper a new threshold gate is proposed. Its main characteristics are high fan-in (128-inputs), low delay time (8.35 ns), low power consumption ( V (Nr A ) f (x) = 0 ⇔ V (Nr B ) > V (Nr A )

(2)

The above Eq. (2) is expressed by voltages, but it can be expressed by binary input signals as follows: f (x) = 1 ⇔ yi ≥ xi and i

f (x) = 0

otherwise

i

(3)

Note that (1) and (3) are functionally equivalents expressions. The circuit proposed performs threshold functions with a fan-in of n = 2m at most, where m is the number of capacitors in each bank, excluding CA0 and CB0. In order to perform a threshold function using the proposed gate, it is necessary to use several rules, which establish the way to connect the input variables to banks of capacitors A and B. This depends of the value and the sign of the weights in addition to the threshold value. As an example we consider the function f (x1 , x2 , x3 ) = x3 x2 + x3 x1 . A threshold structure that can perform this function is f (x1 , x2 , x¯ 3 ) = [1, 1, −2; 1]. Weight values other than one are realised by simply connecting in parallel the number of inputs indicated by the weights as shown in Fig. 2. In order to implement this function, or any function, using our circuit it is necessary to use the following rules: • The absolute value of the weight indicates the number of inputs that must be connected to the input variable associated with this weight. • The sign of the weight indicates the bank at which the input variable must be connected. If it is a negative weight, its associated input variable must be connected to Bank A, and if the weight is positive its associated input variable must be connected to Bank B. • The absolute value of the threshold indicates the number of inputs that must be connected to VDD . This is Bank B if the threshold is negative and Bank A if the threshold is positive. On the other hand, if the complement of the input variables is available, a minimal threshold circuit can be obtained by a simple modification of the gate structure which must have a threshold value T = 0. This modified structure has an optimal number of inputs. The implementation of the Boolean function previously considered by means of two new structures is shown in Table 1. The threshold function structure [1, 1, 2; 3] is turned into a new structure [1, −1, −2; 0] if the

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López-Garc´ıa et al. Table 1.

Structures of the function f (x1 , x2 , x3 ) = x3 x2 + x3 x1 . f (x1 , x2 , x3 ) = x3 x2 + x3 x1 → [1, 1, 2; 3] ⇔ [1, −1, −2; 0] [1, 1, 2; 3] w1 = 1, w2 = 1, w3 = 2, T = 3

[1, −1, −2; 0] w1 = 1, w2 = −1, w3 = −2, T = 0

• x1 → one input connected to Bank B.



• x¯ 2 → one input connected to Bank A.

• x3 → two inputs connected to Bank B.

• x¯ 3 → two inputs connected to Bank A.

• VDD → three inputs connected to Bank A.

• GND →two inputs connected to Bank B to equalize capacitances between banks.

• GND → one input connected to Bank A to equalize capacitances between banks. 8 inputs (4 per bank) are necessary

complemented inputs of x2 and x3 are available. The first structure is implemented using a B-CTL gate with fan-in = 8 and the second one with fan-in = 6. The last component of the BCTL gate to analyse is the comparator, which is shown in Fig. 3. This circuit has a simple and basic structure consisting of two stages. The first stage has a configuration with differential input and differential output. The second is a gain stage with an output voltage range rail-to-rail. The performance of this comparator is highly dependant on the tail current I B . The common mode input range (CMR) is obtained from the condition that the voltage at the node C should be sufficiently high to maintain M11 in the saturation

6 inputs (3 per bank) are necessary

region: VG4(min) = VG6(min) = VTN +

IB + β4

2I B β11

(4)

where VTN is the N-MOS transistor threshold voltage and β4 , β6 are the MOS transistor gain factors of M4 and M11, respectively. VG4(min) represent the minimum gate voltage of the M4 (or M6) transistor. The small signal gain is important in determining the minimum input range possible for the comparator. The larger the gain, the smaller the input range, therefore the precision of the comparator is improved and the fan-in of the threshold gate can be increased. Assuming that all the transistors are in the saturation region, and that the device pairs M1, M3; M5, M7; and M2, M8 act as current mirrors. The small signal gain of the comparator has the following value: β4 2 |Ad | · (5) λ 1 + λ2 IB where λ1 and λ2 represent channel modulation parameters of M1 and M2 (or M7, M8), respectively. Therefore, the minimum input range possible is: VDD I B Vi(min) (λ1 + λ2 ) (6) 2 β4 The condition for M4 and M6 are in saturation region is: IB VG4(max) = VG6(max) = VDD + VTN − |VTP | − (7) β3

Fig. 3.

(a) Schematics of the comparator and (b) Bias.

If this condition is not verified, the gain decreases and the minimum allowable input range increases.

A Balanced Capacitive Threshold-Logic Gate

Expressions (4), (6) and (7) indicate that CMR and the minimum allowable input range are improved when I B decreases, as well as the power consumption. Nevertheless, it is clear that a reduction of I B also causes an increment in the propagation delay; therefore I B should be selected as a trade-off between the fan-in of the gate and the admitted propagation delay. For a fixed value of propagation delay, the fan-in of the gate can be increased with an increment in the gain by means of the addition of new stages in cascade, which can be implemented by CMOS inverters, as is shown in Fig. 1. On the other hand, the current source circuit (Fig. 3(b)) can be turned off by means of the system clock signal in order to save power consumption at the reset phase. Therefore, the gate only consumes power in the evaluation phase. 3.

Design Restrictions and Discussion

As mentioned above, the main drawback of the BCTL gate comes up when the current source I B (tail-current) of the comparator is implemented. If the input vector has few inputs at high value, the voltage at the common nodes is below the lower limit of Eq. (4). This causes a gate malfunction because the voltage levels are not compared correctly. It is necessary to validate the correct behaviour of the comparator in the whole comparison range. A solution to this problem which saves a new external reference source and also avoids further design complications is based on adding a number of inputs (with their respective capacitors) to the gate permanently connected to the high level. This adds an offset voltage (Voffset ) at the common nodes of the capacitor banks. This offset voltage can be determined from the lower limit of the equation (4). We must set the condition (Voffset ) ≥ VG4 (min). The number of necessary extra inputs per bank (n E) that must be connected to the high level is given as the following expression: nE =

VG4(min) (Fan-in) + 1 · VDD − VG4(min) 2

Using the transistor dimensions listed in Table 2, we have determined the parameter n E = 30 for VDD = 3.3 V, I B = 110 µA, VG4(min) = 1.05 V and Fan-in = 64 + 64 = 128. This value of nE can be reduced, at the cost of increasing the propagation delay of the gate, which

Table 2.

Transistors size in Fig. 3.

Transistors M1, M3, M5, M7 M4, M6

65

W (µm)

L (µm)

9

0.6

60

0.6

M2, M8

3

0.6

M9

4

1

M10

10

1

M11

20

1

allows the transistor M11 to operate in the nonsaturation region. In this case it would be verified that VG4(min) = VTN = 0.72 V and I B < 110 µA. The result is nE = 18. To reduce the silicon area required, each group of extra capacitors can be replaced by a single capacitor whose area is equal to nE · Ci . However, if this capacitor is connected to VDD through a CMOS switch, which is composed by the respective NMOS and PMOS transistors and the inverter, the input reaches a higher voltage than the normal digital inputs because the switch causes a lower voltage drop, and so it is possible to reduce the size of this equivalent capacitor even more. It is analogous to reduce the number of extra inputs required. In order to evaluate the performance of the proposed circuit, we have simulated several circuit structures with different fan-in, but only the results of a 128-inputs BCTL threshold gate with nE = 20 are presented. This was simulated in a 0.6 µm double-poly CMOS technology, by using the HSPICE simulator. The CMOS transistor model was the BSIM3V3, with level = 49, from Austrian Micro Systems (AMS). To ensure correct behaviour under fabrication process variations, we have run 30 Monte Carlo simulations for every critical input vector. Variations around the nominal value of the following parameters have been taken into account: σVT = 3% for the transistor threshold voltage and σOX = 5% for the gate oxide thickness. Every digital input has been simulated with four parallelconnected unit capacitors of 8 fF each. Moreover, random and edge capacitor errors due to the fabrication process have been considered [13]. In the following, we will specify the digital input vectors by: (nA + nB, Out), where nA and nB are the number of digital inputs at high level in Bank A and Bank B, respectively, and Out represent the output digital value of the gate for that input vector. The critical input vectors simulated were: (64 + 64,1), (63 + 64,1),

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López-Garc´ıa et al.

Fig. 4. Monte Carlo simulations using HSPICE for input vectors (64 + 64,1) → (64 + 63,0) & (2 + 0,0) → (0 + 1,1).

the same number of digital inputs at logic one in both banks have higher delays because the difference in voltage between banks is lower. Moreover, we have found that the larger the fan-in the smaller the step voltage for adjacent input vectors and, consequently, the smaller the voltage difference between banks when both banks have the same number of inputs at logic one. The operation of the B-CTL gate with fan-in = 128 (64 inputs per bank) has been analysed for different combinations of inputs at logic one. Figure 5 is shows the delay time versus nA (number of inputs at logic one in Bank A) and versus nB (number of inputs at logic one in Bank B). As seen in Fig. 5, the higher delays are over the nA = nB line. 4.

(64 + 63,0), (63 + 63,1), (63 + 61,0), (32 + 32,1), (31 + 32,1), (32 + 31,0), (0 + 0,1), (2 + 0,0), (1 + 0,0) and (0 + 1,1). Figure 4 shows Monte Carlo simulations for two cycles of the gate performance when the input vectors are changed on the reset phase. In the first simulation the input vector is (64 + 64,1), which is changed on the reset phase to (64 + 63,0), and in the second simulation the input vector is (2 + 0,0), which is changed to (0 + 1,1). The maximum delay was 7.15 ns for the most critical input vector (0 + 0,1). Input vectors with

Fig. 5.

Asynchronous and Synchronous Functioning

The B-CTL gate is also capable of evaluating a large number of successive input vectors in between two consecutive reset phases because the evaluation process itself is non-destructive due to charge conservation. The stored charge changes slowly because of the leakage currents through the reset analog switches S A and S B (Fig. 1), therefore a reset phase is periodically required to avoid gate malfunctioning but the frequency of this operation is very low whatever the Fan-in. Figure 6 shows a simulation in which a continuous evaluation

Number of inputs (nA, nB) at logic one versus delay time.

A Balanced Capacitive Threshold-Logic Gate

poly2) structures. The unit weight capacitance thus implemented has an estimated value of 5.3416 fF and each digital input uses four unit capacitors parallelconnected. The number of extra capacitors in every bank is equal to 20. The input switches of Bank A and Bank B are arranged on the left side and on the right side, respectively, of the layout. The layout area is 430 × 310 µm. The HSPICE simulations described in Section 3 and other delay and power consumption estimations have been verified from files extracted generated with the CADENCE design framework software for the AMSCUQ 0.6 µm CMOS process. The deviations between the two configurations are minimal except that the maximum delay time was increased from 7.15 to 8.35 ns for the most critical input vector (0 + 0,1). Applications using only one threshold gate have been also considered from layouts. An OR function implemented for B-CTL gates with different fan-in, where a single input rises to logic one while the remaining inputs are in logic zero. The results are shown in Table 3. Another two situations more have been evaluated. In the first one, all inputs in Bank A are connected simultaneously to VDD and the inputs in Bank B are connected simultaneously to GND. In the second situation, all inputs of the gate are connected simultaneously to VDD . The results are also shown in Table 3. Another application has been a Muller C-element [14], which is commonly used for joining signal transitions to indicate the completion of an operation, which is divided into smaller operations. An m-input C-element can be viewed as a logical and of m events, where an event can be a 0 → 1 or 1 → 0 transition. The output of a Muller C-element is made equal to the value of input after all the inputs reach the same value; otherwise, the output remains the same. A Muller C-element with 64 inputs can be implemented using a 128-inputs BCTL gate, where 63

Fig. 6. Continuous evaluation of input vectors in the same evaluation phase.

Fig. 7.

Asynchronous connection of BCTL gates.

of input vectors within the same evaluation phase is carried out. These input vectors are changed every 15 ns. Note that e signal is scaled. This last feature permits an asynchronous connection as is shown in Fig. 7. Note that the proposed gate only needs one clock signal. This means that all threshold gates in a circuit can be sharing the same system clock signal for all of them. Moreover, no other external control signal is necessary for the circuit functioning. These qualities produce an easier circuit layout. 5.

Layout Considerations and Applications

A layout of the 128-inputs BCTL gate with nE = 20 in 0.6 µm double-poly CMOS technology is shown in Fig. 8. The weight-implementing capacitors are built as multiples of minimum geometry cpoly (poly1Table 3.

Delay times and power consumptions of the B-CTL gate.

B-CTL gate

Fan-in = 20

67

Fan-in = 30

Fan-in = 64

Fan-in = 128

OR function delay time

2.102 ns

158 µW

2.583 ns

163 µW

2.722 ns

191 µW

6.85 ns

302 µW

Inputs Bank A → VDD Inputs Bank B → GND

0.44 ns

165 µW

0.87 ns

181 µW

1.25 ns

219 µW

2.67 ns

394 µW

Inputs Bank A→VDD Inputs Bank B→VDD

0.739 ns

172 µW

1.17 ns

194 µW

1.38 ns

196 µW

3.46 ns

375 µW

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López-Garc´ıa et al.

Fig. 8.

Layout of 128-inputs BCTL gate.

inputs of Bank B are connected to the output of the gate and one input of this bank is connected to logic zero. The inputs of the Muller C-element are the inputs of the Bank A. The Muller C-element output changes between logic levels for (0 + 0,1) and (64 + 63,0) input vectors. The maximum delay time of this Muller C-element is 8.35 ns, which coincides with the propagation delay of the input vector (0 + 0,1).

circuits, in general, with high reliability, real-time digital signal processing, and neural networks on silicon. In these kinds of applications threshold functions with a low number of logic levels are necessary, but this means threshold gate structures with high weight values. Therefore, threshold gates with high fan-in are required. Acknowledgment

7.

Conclusions

A new CMOS threshold-logic gate has been proposed. Simulation results of 128-input gates indicate that this threshold gate can operate with high fan-in, low power consumption, and asynchronous/synchronous functioning. This design eliminates dependency on a highly precise external analog reference voltage. The gate developed is a generic threshold gate in which the threshold function is carried out by comparison between two capacitor arrays that perform the arithmetic operation of sum-of-products. OR-functions and Muller C-element applications have been considered for the proposed gate. Other possible applications are the design of efficient binary adders [15] and arithmetic

The authors wish to thank the anonymous referees for their constructive comments. References 1. S. Muroga, Threshold Logic And its Applications. Wiley Interscience: New York, 1971. 2. S.L. Hurst, “An introduction to threshold logic: A survey of present theory and practice.” The Radio and Electronic Engineer, pp. 339–351, 1969. 3. A.L. Larson, “A TTL compatible threshold gate.” IEEE Journal of Solid-State Circuits, vol. SC-8, pp. 470–471, 1973. 4. K.J. Schultz, R.J. Francis, and K.C. Smith, “Ganged CMOS: Trading standby power for speed.” IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 870–873, 1990.

A Balanced Capacitive Threshold-Logic Gate 5. T. Shibata and T. Omi, “A functional MOS transistor featuring gate-level weighted and threshold operations.” IEEE Transactions on Electron Devices, vol. 39, no. 6, pp. 1444–1455, 1992. ¨ 6. H. Ozdemir, A. Kepkep, B. Pamir, Y. Leblebici, and U. C ¸ ilingiroglu, “A capacitive threshold-logic gate.” IEEE J. SolidState Circuits, vol. 31, no. 8, pp. 1141–1149, 1996. 7. I. Hatirnaz, F.K. Gurkaynak, and Y. Leblebibi, “Realisation of a programmable rank order filter architecture using capacitive threshold logic gates.” ISCAS99, 1999 IEEE International Symposium on Circuits and Systems, 1999. ¨ 8. Y. Leblebibi, H. Ozdemir, A. Kepkep, and U. C ¸ ilingiroglu, “A compact parallel (31,5)-counter circuit based on capacitive threshold-logic gates.” IEEE Journal of Solid-State Circuits, vol. SC-31, pp. 1177–1183, 1996. 9. A. Schmid, D. Bowler, R. Baumgartner, and Y. Leblebibi, “A novel analog-digital flash converter architecture based on capacitive threshold logic gates.” ISCAS99, 1999 IEEE International Symposium on Circuits and Systems, 1999. 10. M.J. Avedillo, J.M. Quintana, A. Rueda, and E. Jiménez, “Low power CMOS threshold logic gate.” Electronics Letters, vol. 31, no. 25, pp. 2157–2159, 1995. 11. J. Fernandez-Ramos, J.A. Hidalgo-López, M.J. Mart´ın, J.C. Tejero, and A. Gago, “A threshold-logic gate based on clocked coupled inverters.” International Journal of Electronics, vol. 84, no. 4, pp. 371–382, 1998. 12. F. Krummenacher, “High voltage gain CMOS OTA for micropower SC filters.” IEE Electronic Letters, vol. EL-17, no. 4, p. 170, 1981. 13. J.B. Shyu, G.C. Temes, and K. Yao, “Random errors in MOS capacitors.” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1070– 1076, 1982. 14. D.E. Muller, W.S. Bartky, “A theory of asynchronous circuits.” Proc. Int. Symp. on Theory of Switching, vol. 29, pp. 204–243, 1959. 15. J. Fernandez Ramos and A. Gago, “Two operand binary adders with threshold logic.” IEEE Transactions on Computers, vol. 48, no. 12, pp. 1324–1337, 1999.

Javier López-Garc´ıa received the M.Sc. and Ph.D. (with honors) degrees in Computer Science Engineering from the University of Málaga, Spain, in 1995 and 2001 respectively. Since 1992, he has been working at the Department of Electronic in the University of Málaga, where he is currently a Chief of Laboratories and Associate Professor of Computer Science from 1998. His current research interests include arithmetic

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circuits design with Threshold Logic and low-voltage high-speed analog integrated circuit design.

José Fernández-Ramos received the degree of Licenciado en Ciencias Físicas (Branch of Electronics) from the University of Seville, Spain, in 1984. From 1984 to 1990, he worked as a design engineer in electronics of the R&D department of INFESA, Spain. In January of 1991, he joined the University of Málaga as an assistant professor in informatic and electronic engineering. He received the Ph.D. degree in March of 1998 with the dissertation on the design of arithmetic circuits with Threshold Logic. His current research interests include arithmetic circuits design with Threshold Logic and analog mixed-signal integrated circuit design for threshold gates, digital signal processing, and electronic hearing aids.

Alfonso Gago-Bohórquez received the degree of Licenciado en Ciencias F´ısicas (Branch of Electronics) from the University of Seville, Spain, in 1974. In September of 1975, he joined the University of Seville as an assistant professor in physics and electronic engineering. He received the Ph.D. degree in November of 1979 with the dissertation on the design of nonlinear networks. Since 1989, he has been a professor of electronic and computer engineering with the Department of Electronics of the University of Málaga, Spain, where the heads a research group on analog and digital integrated circuit design. His current research interests include computer arithmetic, digital signal processing and electronic hearing aids.