A Bi-flyback PFC converter with low intermediate bus voltage and tight output voltage regulation for universal input applications1 Weihong Qiu, Wenkai Wu*, Shiguo Luo, Wei Gu, and Issa Batarseh *
School of Electrical Engineering and Computer Science University of Central Florida Orlando, FL 32816 Email:
[email protected] Abstract: A single-stage Bi-flyback power factor correction topology is proposed in this paper. By adding a secondary winding to BIFRED choke inductor, there are two discharging paths for choke inductor: to load or to intermediate capacitor. In this topology, the intermediate bus voltage will be limited to below 400VDC for universal voltage applications, and DC/DC conversion cell can operate in CCM. A 150W prototype unit based on this topology has been built and tested in the lab with experimental results that show good performance.
I. INTRODUCTION Power Factor Correction (PFC) converter is necessary for many electronic equipments to meet harmonic regulations and standards, such as IEC 1000-3-2. For low power applications, single-stage PFC converter is a better choice considering cost and performance. Typical single-stage PFC topologies with tight output voltage regulation were proposed in [1]. In those topologies, a PFC cell is integrated with a DC/DC conversion cell, and both cells share active switches and controller. But those topologies suffer from high intermediate bus voltage and high current stresses. Some methods to reduce the intermediate bus voltage were discussed in [2]. But most of those methods will bring high distortion to line current waveform, resulting in reduced power factor. An effective scheme to limit intermediate bus voltage was proposed in [3]. By adding a secondary winding to the boost inductor, there are two discharging paths for boost inductor: to the intermediate storage capacitor or directly to the load. It means that some input power is directly transferred to the load without being processed by DC/DC conversion cell, referred as parallel power transfer in [4,5]. This scheme can limit the intermediate bus voltage with little influence on input current waveform, and the DC/DC conversion cell can operate in CCM without high voltage punishment at light load conditions. In this paper, the scheme in [3] is applied to BIFRED converter, which was discussed in [6,7], resulting in a topology to be known as Bi-flyback topology, as shown in Figure 1(a). The first flyback transformer T1 in the PFC cell operates in DCM to obtain high power factor. The secondary flyback transformer T2 in DC/DC conversion cell operates in
CCM to reduce the current stress and achieve tight output voltage regulation. This topology can limit the maximum intermediate bus voltage under 400VDC for universal voltage applications, and achieve high power factor and high efficiency. In practical circuit, snubber circuit is necessary due to transformer leakage inductance. Two topologies with snubber circuit are shown in Figures 1(b) and 1(c). Similar topology with active clamp circuit was presented recently for 110V input application [8]. Here it was used for universal line voltage applications, and a special control scheme was implemented to control the intermediate bus voltage as presented in [9]. The operation of topology in Figure 1(a) was discussed, and experimental results of a 150W @ 28VDC prototype was shown to verify its operation. T1
D1
n1 : 1
T2 n2 : 1
V in
D2
C0
+
| V in |
VDS
S
-
-
CS
+
VO
-
V CS
(a) Basic topology T1
n1 : 1
D1 T2 n2 : 1
Vin
+
D2
C 0 Vo
S1
CS
(b) With low loss snubber circuit T1
D1
n1 : 1
T2
Vin
n2 : 1
L2 S2
D2
+
S1
C DS
Cc
+
C 0 Vo +
Cs
Fig. 1. Proposed Bi-flyback PFC converter
256
+
+
(c) With active clamp circuit
1. This work was partially supported by NASA-STTR grant #NAS10-00038.
0-7803-7404-5/02/$17.00 (c) 2002 IEEE
APECOR Co. Research Pavilion #453 12424 Research Parkway Orlando, FL 32826
II. OPERATION PRINCIPLE s
For simplification, all components are assumed to be ideal here. The basic topology in Figure 1(a), with PFC cell operating under DCM and DC/DC conversion cell operating under CCM for entire line period, will be discussed here. The proposed Bi-flyback topology consists of two flyback circuits: The first PFC flyback circuit is composed of transformer T1, rectifier input bridge, diode D1, output filter capacitor Co and Power MOSFET S; The second DC/DC flyback circuit includes transformer T2, intermediate bus capacitor CS, diode D2, output filter capacitor Co and Power MOSFET S. The second flyback circuit operates like conventional DC/DC flyback circuit. For PFC flyback circuit, there are two discharging paths for transformer T1, depending on instantaneous input voltage and intermediate bus voltage. When input voltage is low, T1 will discharge its magnetizing energy to the load via diode D1 during S OFF period, like typical flyback transformer. When input voltage is high, T1 operates like a boost inductor and discharges its magnetizing energy to intermediate capacitor through T2 primary winding. When T1 operates like flyback transformer, it is referred to as flyback mode, and as boost mode when T1 works as boost inductor. So there are two operation modes for this topology. The operation modes over one line cycle are shown in Figure 2.
t
i1
I1P
iD1
n1 * I 1P
t
B o o st
F ly b a c k
B oost
F ly b a c k
M od e
M o d e
M ode
M ode
M o de
I 2O
I2P
i2
t
iD 2
n2 * I2P
VDS
t
VCS + n 2 * V o
t
t0
t2
t1
t3
(a) Operation waveforms D1
Vin
D2
i1
+
T1
i2
n1 : 1
T2
C0
n2 : 1
Cs
+
VCS
(b) Equivalent circuit during ON period D1
iD1 D2
Vin T1 n2 : 1
t
t
x
− tx
iD 2
T2
n1 : 1 V C S + (n 2 − n 1 ) ⋅ V O
T 2
T 2
T 2
+ tx
T − tx
VO
S
|V in | F lyba c k
t
Cs +
Fig. 2. Operation mode in one line period
C0
VO
-
S
T
+
VCS
(c) Equivalent circuit during OFF period
A. Flyback mode When rectified line voltage |Vin(t)| is less than VCS+n2Von1Vo (n1: the turn ratio of T1, n2: the turn ratio of T2), Transformer T1 works like a flyback transformer, and the topology operates like two independent flyback converters. All input power during this mode is directly transferred to the load through T1. Meanwhile, the DC/DC flyback cell will deliver some power from intermediate capacitor to load, in order to keep tight output voltage regulation. The equivalent circuits and operational waveforms are shown in Figure 3. Interval 1 (to ~ t1): Switch S is turned on at to. The rectified line voltage |Vin(t)| is applied to primary winding of T1. The current in T1, i1 in Figure 3, increases linearly. The intermediate bus voltage VCS is applied to primary winding of transformer T2, causing its current i2 to linearly increase also. Since PFC cell operates in DCM, i1 starts increasing from zero.
Fig. 3. Operation of flyback mode
Interval 2 (t1 ~ t2): S is turned off at t1. T1 discharges through its secondary winding and deliveries stored magnetizing energy to the load. The current (iD1) in T1 secondary winding decreases linearly. T2 also discharges its magnetizing energy to the load via its secondary winding. The voltage across transformer T1 primary winding is n1Vo, while the voltage across T2 primary winding is n2Vo. So the voltage across switch S, VDS, is equal to VCS+n2Vo, which is higher than |Vin(t)|+n1Vo. The input rectifier bridge is blocked. Interval 3 (t2 ~ t3): At t2, all magnetizing energy in T1 is transferred to the load. Current iD1 reaches zero and diode D1 keeps it at zero. The current in T2 secondary winding, iD2, continues to decrease until the switch is turned on at t3. Then a new switching cycle begins. Switching period TS is equal to t3-t0.
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B. Boost mode When the line voltage goes higher, |Vin(t)| > VCS + n2Vo n1Vo, the voltage in transformer T1 primary winding during S OFF period is VDS–|Vin(t)|, i.e. VCS+n2Vo-|Vin(t)|, which will be less than n1Vo. It means that diode D1 in T1 secondary winding discharge path will not conduct. T1 works like a boost inductor and discharges its magnetizing energy only through its primary winding. The proposed topology at this mode will operate as BIFRED topology in [6, 7]. T1 transfers some input power to intermediate storage capacitor CS and some input power to the load through T2. Meanwhile, T2 will also transfer some power from intermediate capacitor to the load in order to keep tight output voltage regulation. The equivalent circuits and operational waveforms are shown in Figure 4. S
t
i1
I 1P
t
iD1
t I 2O
I2P
i2
voltage across the intermediate bus capacitor, Vcs, is applied to T2 primary winding, which causes the current i2 in Figure 4 to linearly increase also. Interval 2 (t1 ~ t2): Switch S is turned off at t1. T1 current i1 will decrease linearly and discharge its magnetizing energy through DC/DC transformer T2 primary winding and intermediate capacitor. So T2 primary winding current i2 is equal to T1 current i1, which will be reflected to T2 secondary winding. The current (iD2) in T2 secondary winding consists of magnetizing current of T2 and reflected current of T1 current i1. And T2 magnetizing current will decrease linearly since output voltage is applied to T2 secondary winding. The voltage across T2 primary winding is n2Vo. So the voltage across S, VDS, is equal to VCS+n2Vo. The voltage across transformer T1 primary winding is VCS+n2Vo-|Vin(t)|. Interval 3 (t2 ~ t3): At t2, i1 reaches zero and the input rectifier bridge prevents it from going negative. And iD2, which only consists of magnetizing current of T2 in this interval, continues to decrease until the switch is turned on at t3. At t=t3=to+TS, the switching cycle repeats.
t
III. STEADY-STATE ANALYSIS
I1P
iD 2
n 2 * ( I1P + I 2 P )
VDS
A. Mode boundary According to the discharging path of T1, there are two different operation modes over one line period. Based on the operation analysis in last section, rectified input voltage is equal to VCS+(n2-n1)Vo at boundary of two modes. In first quarter of line period, the boundary time for two modes is given by:
t
VCS + n2 * Vo
t
t0
t1
t3
t2
(a) Operation waveforms D1
Vin
tx =
D2 +
i1
T1
i2
n1 : 1
T2
C0
n2 : 1
S Cs
+
V + n2Vo − n1Vo 1 sin −1 cs Vp ω
(1)
since
VO
vin (t ) = V p sin(ω t )
VCS
(2)
Since the operation of this circuit is symmetrical over the line period, it is easy to obtain all mode boundary for this topology, as shown in Figure 2.
(b) Equivalent circuit during ON period D1 T2 n2 : 1
Vin
i1
T1 n1 : 1
+ S
i2
iD 2
VDS
-
D2
Cs
B. Stead-state equation for intermediate bus voltage Assume that the input current is sinusoidal waveform and synchronous with the input voltage. Then the input power waveform will be sinusoidal also, since Pin(t)= Vin,peakIin,peaksin2(ωt) = Vin,peakIin,peak[1-cos(2ωt)]/2. According to analysis in last section, during flyback mode, all input power is transferred to the load; during boost mode, some input power is stored in intermediate bus capacitor and some is transferred to the load through T2. Magnetizing power delivered by T2 is controlled to keep total transferred power equal to output power, in order to keep tight output voltage regulation. The power flow over one line cycle is shown in Figure 5.
+ C0
VO
-
+
VCS
(c) Equivalent circuit during OFF period Fig. 4. Operation of boost mode
Interval 1 (to ~ t1): S is turned on at to, resulting in rectified line voltage |Vin(t)| applied to T1. The current in T1 primary winding, i1 in Figure 4, increases linearly. And the
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I1P =
Pi n Po
t
P1
W1 =
Po
t tx
T 4
T 2
− tx
Direct transferred power by T1 W c s 1 : discharging
Pin: P11: P1: P2:
voltage over each switching cycle. So when switch is turned off at t1, the magnetizing energy stored in T1 is equal to
t
P2 T 2
T 2
+ tx
T − tx
L1 I1P 2 D 2Ts2 vin ,Ts 2 = 2 2 L1
(5)
The above magnetizing energy in T1 is completely transferred to the load. In order to keep tight output voltage regulation, i.e. Vo constant, the total power delivered respectively by T1 and T2 should be equal to output power in each switching cycle. So the power delivered by T2 in one switching cycle is:
T
Direct transferred power by T2
W c s 2 : discharging
(4)
where L1 is the primary inductance of T1, Ts is switching period, and vin ,Ts is the moving average value of the input
t P1 1
DTs vin ,Ts L1
W c s 3 : c harging
Input power Power transferred by T1 at flyback mode Power transferred by T1 at boost mode Power delivered by T2 Fig. 5 Power flow over a line period
P2 = Po −
Since the operation of the proposed topology is symmetrical, only operation in the first quarter of line period needs to be analyzed. Based on following assumptions, we will calculate the intermediate bus voltage: All circuit components are ideal; Switching frequency is much higher than line frequency, and the input voltage can be assumed to be constant over one switching period; The intermediate bus capacitor is large enough to assume that its voltage is constant. In order to keep its voltage constant, the charging energy and discharging energy of intermediate bus capacitor in each line period should be balanced; Tight output voltage regulation to keep output voltage constant. So the charging energy and discharging energy of output capacitor in each switching period should be equal. In order to achieve high power factor, PFC cell should operate in DCM; while DC/DC conversion cell can operate in CCM to reduce current stresses on power components. So, we assume that PFC cell operates in DCM, and DC/DC cell operates in CCM in following analysis. DC/DC conversion cell of the proposed topology in Figure 1(a) is a typical flyback topology. When it operates in CCM, the duty cycle should be constant for the entire line period to achieve tight output regulation. According to flyback circuit formula, the duty cycle is given by: n2Vo (3) D= Vcs + n2Vo
W1 D 2Ts vin ,Ts 2 = Po − 2 L1 Ts
(6)
In the flyback mode, all power delivered by T2 is from intermediate capacitor. So the total discharging energy from intermediate bus capacitor during flyback mode (0~tx) is given by: tx
Wcs1 = ∑ P2Ts
(7)
t =0
where tx is the boundary time between flyback mode and boost mode, with vin(tx) = VCS+(n2 - n1)Vo. Since switching frequency is much higher than line frequency, the summation Equation (7) can be converted to following integration combining with Eq. (6) and replacing vin ,Ts by vin(t): tx tx D 2Ts (8) Wcs1 = ∫ P2dt = ∫ Po − vin (t )2 dt 0 0 2 L 1 In the boost mode (tx~T/4), both transformers are charged during ON period, and T1 is completely discharged through T2 primary winding and intermediate bus capacitor, while T2 will discharge some magnetizing energy to load during OFF period in each switching cycle. According to Figure 4, discharging period (t1~t2) of transformer T1is equal to:
t2 − t1 =
During the flyback mode (0 ~ tx), in a given switching cycle, transformer T1 is charged by rectified input voltage during S ON period, and is completely discharged to the load during S OFF period. According to the operation waveform in Figure 3(a), the peak current in T1 at t1 is given by:
I1P L1 Vcs + n2Vo − vin ,Ts
(9)
The operation of two modes during S ON period (t0 ~ t1) is same, so Eq. (4) is also effective in boost mode. Based on Eqs. (4) and (9), the average input current flowing through T2 and intermediate bus capacitor in one switching cycle is yielded as: i1( avg ) =
vin ,Ts 2 (t2 − t1 ) D 2Ts I1 P = 2Ts 2 L1 Vcs + n2Vo − vin ,Ts
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(11)
So the average input power, P1a, charged to intermediate bus capacitor in one switching cycle is given by: P1a = Vcsi1( avg ) =
Vcs vin ,Ts 2 D 2Ts 2 L1 Vcs + n2Vo − vin ,Ts
(12)
During boost mode (tx ~ T/4), total charging energy from input to intermediate bus capacitor is given by: T 4
T 4
tx
tx
D 2Ts Vcsvin (t ) 2 dt 2 L1 Vcs + n2Vo − vin (t )
Wcs 3 = ∫ P1a dt = ∫
(13)
And the average input power, P1b, directly transferred to load by T2 during S OFF period in one switching cycle is: n2Vo vin ,Ts 2 D 2Ts 2 L1 Vcs + n2Vo − vin ,Ts
P1b = n2Voi1( avg ) =
(14)
tx
∫ LV
P2b = Po − P1b = Po −
2
n2Vo vin ,Ts D Ts 2 L1 Vcs + n2Vo − vin ,Ts
T 4
=∫ tx
T 4
D 2Ts n2Vovin (t )2 Wcs 2 = ∫ P2bdt = ∫ Po − dt 2 ( ) L V n V v t + − 1 2 o cs in tx tx
(16)
In steady state, the voltage across intermediate bus capacitor is constant, so its charging and discharging energy should be balanced in each line period, i.e. Wcs1+Wcs2=Wcs3. Combining Eqs. (2), (3), (8), (13) and (16), yields the equation of intermediate bus voltage given by: Ts n2 2V p 2Vo 2 L1 (Vcs =
T 4
sin(ω t ) 2 dt cs + n2Vo − V p sin(ω t )
+ n V ) ∫V 2 o
tx
Ts n2 2V p 2Vo 2 t x sin(2ω t x ) PoT − − 2 4ω L1 (Vcs + n2Vo ) 2 2
LV 1 CS dt + L2VP2 sin(ωt )2
L2VP 2 sin(ωt )2 − LV 1 CS (VCS + n2Vo − Vp sin(ω t ) )
dt 2 n2 L2VoVP 2 sin(ωt )2 + LV 1 CS (VCS + n2Vo − Vp sin(ωt ) )
(18)
There is another operation condition: DC/DC conversion cell operates in CCM for some time and in DCM for some time in one line period. The equation of intermediate bus voltage can still be derived based on the above method. Those equations show the relationship between intermediate bus voltage and other circuit parameters. It is a transcendental equation that can be solved by mathematical software, such as MathCAD.
(15)
In the boost mode, all transferred magnetizing energy in T2 is the discharging energy from intermediate bus capacitor. So the total discharging energy from intermediate bus capacitor during boost mode (tx ~ T/4) is given by: T 4
2
1 CS
0
Since the sum of P1b and delivered magnetizing power of T2 should be equal to output power, the transferred magnetizing power of T2 during S OFF period is equal to: 2
b) Calculate the power transferred to load by DC/DC flyback cell in one switching cycle; c) The sum of power obtained in steps a) and b) should be equal to output power for each switching cycle. So duty cycle can be derived from this relationship; d) Calculate the charging and discharging energy of intermediate capacitor in one line period, using the same method in above CCM analysis; e) The charging and discharging energy should be balanced for each line period. So the final equation of intermediate bus voltage is achieved. Here, we just gave the final equation for DC/DC conversion cell in DCM operation as following:
C. Condition for PFC cell in DCM In order to achieve high power factor, PFC cell should always operate in DCM. The maximum charging voltage and the minimum discharging voltage across transformer T1, and the maximum power processed by PFC cell all happen at T/4, when Vin(T/4)=VP. So PFC cell will operate in DCM for the entire line period if it operates in DCM at T/4. In order to keep PFC cell in DCM, i1, in Figure 4(a) in transformer T1 should reach zero before a new switching cycle begins, which means that: t2 − t1 ≤ t3 − t1
(17)
Above equation is only applicable to the condition that DC/DC flyback cell operates in CCM during entire line period. When load is very light or inductance of T2 primary winding is low, DC/DC flyback cell may enter DCM. In DCM, the duty cycle will keep changing according to input instantaneous voltage in order to achieve tight output voltage regulation. Since the power processed by DC/DC flyback conversion cell under DCM can be easily calculated, the equation can be obtained by the following steps: a) Calculate the power directly transferred to load by PFC cell in one switching cycle;
(19)
while: t3 − t1 = (1 − D )Ts
(20)
Combining Eqs. (3), (9), (19) and (20), we obtain the following condition for PFC cell in DCM: VCS ≥ VP
(21)
where Vp is the peak value of input voltage. So the intermediate bus voltage should always be higher than the peak value of input voltage in order to keep PFC cell in DCM.
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Fig. 6. Input current and input voltage at 100W output and 110V input Top: current (1A/div) Bottom: voltage (200V/div)
DC capacitor voltage (V)
400 350 300 250 200 150 100 0
30
60 90 output power (W)
265V
220V
120
150
110V
85V
Fig. 7. Measured intermediate bus voltage versus output power 0.98 0.975
Power factor
D. Features By adding another discharging path to PFC inductor, the proposed topology benefits from following features: a) The maximum intermediate bus voltage is limited. Only at boost mode when input voltage is higher than VCS+n2Vo-n1Vo, intermediate bus capacitor Cs is charged by input power. The higher intermediate bus voltage, the less charging power. So the maximum intermediate bus voltage will be limited to Vin,peak + n1Vo -n2Vo. Carefully selecting transformer turn ratio n1 and n2, the maximum intermediate bus voltage can be set to a little higher than the peak value of input voltage to achieve low voltage stresses and high power factor. For universal voltage (85~265VAC,RMS) applications, the maximum intermediate bus voltage can be controlled to less than 400VDC, allowing single commercial 450VDC capacitor to be used in this topology. Since the maximum intermediate bus voltage is limited, DC/DC conversion cell can operate in CCM for low current stresses, without problem of high voltage at light load existing in the conventional single-stage PFC converter [1]. b) Part of load power is processed by the main switch only once. In the flyback mode, all input power is directly transferred to load by T1. In the boost mode, some input power is directly transferred to the load by T2, and some input power is stored in intermediate bus capacitor and then delivered to the load by DC/DC cell. So the total power processed by active switch is less than that in conventional single-stage PFC converter. The approach of processing less power was known as parallel power transfer in [4][5]. It will lower current stresses on power components and improve efficiency, as discussed in [4][5]. IV. EXPERIMENTAL RESULTS
0.97 0.965 0.96 0.955 0.95
One prototype based on the topology shown in Figure 1(c) has been built and tested to verify its operation principle. The main design specifications are: Input: 85~265VAC,RMS Output: 28VDC @ 150W Switching frequency: 200kHz T1: primary inductance L1 = 30uH, turn ratio n1 = 4 T2: primary inductance L2 = 375uH, turn ratio n2 = 3.8 Figure 6 shows experimental waveforms of input current and voltage at 100W output and 110VAC,RMS input. Figure 7 shows the variation of intermediate bus voltage versus output power at different input voltage conditions. The maximum voltage across intermediate capacitor is about 390VDC for universal input voltage and all load condition. Figures 8 and 9 gives the measured power factor and efficiency versus input voltage at 150W load. Measured power factor is 0.974 with 83.2% efficiency at 110V input and 150W load.
0.945 85
115
145
175
205
Input voltage (V)
235
265
Fig. 8. Measured power factor at 150W load 0.84 0.835
Efficiency
0.83 0.825 0.82 0.815 0.81 0.805 85
115
145
175
205
Input voltage (V) Fig. 9. Measured efficiency at 150W load
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235
265
In topologies shown in Figures 10(a-g), the PFC cell is a modified boost type PFC cell with an extra winding added to its choke inductor. In Figure 10(h), the extra winding is added to choke inductor of buck PFC cell. Figure 10(i) shows an example of modified topologies with SEPIC PFC cell. It is similar to the topology in Figure 1(b). Figure 10(j) illustrates a modified topology by applying this concept to BIBRED topologies presented in [6]. All those topologies benefit from the same advantages discussed above.
V. DERIVED TOPOLOGIES As reported in [3], the scheme of adding an extra winding to input inductor to limit intermediate bus voltage, can be applied to most of existing single stage PFC topologies, such as topologies with boost, buck, SEPIC, buck-boost or Cuk PFC cells [1], and a family of single-stage PFC topologies will be derived. Figure 10 shows some sample topologies obtained by modifying existing singlestage PFC topologies.
VI. CONCLUSION
+
Vo
Vo
-
-
(a) With forward DC/DC cell
A single-stage, single-switch Bi-flyback PFC topology is discussed in this paper. It can effectively limit the intermediate bus voltage below 400VDC allowing single commercial 450VDC capacitor to be used. Its simple configuration and good performance makes it suitable for universal voltage low power PFC converter applications.
+
+ +
(b) With flyback DC/DC cell
ACKNOWLEDGMENTS +
+
Vo
Vo
-
-
(c) With series/parallel forward DC/DC conversion cell
The authors would like to acknowledge the help of Dr. Peter Kornetzky from Institute for Microelectronic and Mechatronic Systems in Germany for valuable discussions. REFERENCES
(d) With series/parallel flyback DC/DC conversion cell
[1]. Redl, R.; Balogh, L.; Sokal, N.O., “A new family of single-stage isolated power-factor correctors with fast regulation of the output voltage”, PESC '94, P1137 -1144 vol.2, June 1994
Vo
+
Vo
-
-
(e) With two switches forward DC/DC conversion cell
[2]. Qiao, Chongming; Smedley, K.M., “A topology survey of single-stage power factor corrector with a boost type input-current-shaper”, APEC 2000, P460 -467 vol.1, March 2000
+
+ +
[3]. Luo, Shiguo, “Front-end converters design and system integration techniques in distributed power systems”, PhD dissertation, Univ. of Central Florida, 2001
(f) With two switches flyback DC/DC conversion cell
[4] Jiang, Y.; Lee, F.C.; Hua, G.; Tang, W, “A novel single-phase power factor correction scheme”, APEC '93, P287 –292, March 1993 [5] García, O.; Cobos, J.A.; Prieto, R.; Alou, P.; Uceda, J.; “Power Factor Correction: A Survey”, PESC ’01, P8-13, vol. 1, June 2001 [6]. Madigan, M.; Erickson, R.; Ismail, E., “Integrated high quality rectifierregulators”, PESC '92, P1043 -1051 vol.2, June 1992
+ +
Vo
-
[7]. Willers, M.J.; Egan, M.G.; Murphy, J.M.D.; Daly, S., “A BIFRED converter with a wide load range”, IECON '94, P226 -231 vol.1, 1994
+ Vo -
(g) With half bridge DC/DC cell
+ +
[8]. Jin, C.; Ninomiya, T., “A novel soft-switched single-stage AC-DC converter with low line-current harmonics and low output-voltage ripple”, PESC 2001, P660-665, vol.2, June 2001
(h) With flyback DC/DC cell
[9]. Wu, W.; Qiu, W., Gu, W., Batarseh, I., “A modified control method to alleviate DC voltage stress in active clamp PFC AC/DC converter with universal input”, to be published in APEC 2002
+
Vo
Vo
-
+
(i) Modified SEPIC PFC cell with flyback DC/DC cell
(j) Modified BIBRED
Fig. 10. Derived family of single stage PFC topologies
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