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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 8, AUGUST 1996

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A Capacitive Threshold-Logic Gate ¨ Hakan Ozdemir, Member, IEEE, Asım Kepkep, Student Member, IEEE, Banu Pamir, Student Member, IEEE, Yusuf Leblebici, Member, IEEE, and U˘gur Cilingiro˘ ¸ glu, Member, IEEE

Abstract— A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-ofproduct and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fan-in 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described.

I. INTRODUCTION

T

HRESHOLD logic (TL) originally emerged in the early 1960’s as a unified theory of logic gates, which includes conventional switching logic as its subset [1]–[5]. The formal TL gate can perform not only and/or primitives but any linearly separable Boolean function. Since the basic gate is functionally more powerful than those of the conventional logic, many complex functions can be synthesized in TL with lesser number of gates in a shorter logic depth. The higher the complexity of the Boolean function, the greater the relative advantage of TL. On the other hand, the complexity of a Boolean function is closely associated with the number of variables involved, a fact that clearly indicates parallel vector processing as the most promising application area for TL. This, however, requires a basic TL gate structure of much larger fan-in in comparison with the conventional logic gates. Despite the theoretically obvious merits, TL has never had a significant impact in practice, most probably due to the limited success achieved in developing a suitable TL gate on silicon. Although several bipolar TL gates have been proposed in the 1970’s [6], [7], their fan-in and integration density were inadequate for a full-scale exploitation of TL properties. It seems that this logic attracted only a limited research interest in the early MOS era, which was obvious from its gradual disappearance from textbooks on logic. One notable TL development of the CMOS era is the ganged-CMOS gate [8], whose applications included median filter [9], edge-triggered flipflop [10], Muller -element Manuscript received July 3, 1995; revised January 30, 1996. This work was supported in part by the Technology Development Fund of Turkey under ¨ Contract TTGV-036 and by the following members of ˙ITU-ETA Foundation: Alcatel-Teleta¸s AS, ¸ Bekoteknik AS, ¸ Neta¸s AS, ¸ Simko AS¸ and Vestel AS. ¸ The authors are with the ETA Design Center and Department of Elec¨ tronics and Communications Engineering, ˙Istanbul Technical University, ˙ITU Ayaza˘ga Kamp¨us¨u, Maslak-80626, ˙Istanbul, Turkey. Publisher Item Identifier S 0018-9200(96)05701-0.

and Losq’s voter [11]. This TL gate has indeed proved to be favorable in integration density. However, the nonlinearity and power consumption resulting from hard-wiring the outputs of ratioed CMOS inverters limit the available fan-in to less than about ten. This, in turn, severely limits the applicability of ganged-CMOS in large-dimensional signal processing. The recently disclosed Neuron MOS transistor ( MOS) is another TL gate in CMOS [12]–[14]. However, even the most advanced MOS gate relies on UV erasure for initialization, and has a stray-sensitive and process-dependent resolution, as a result of which, the fan-in cannot be improved much beyond what is offered by ganged-CMOS. A TL gate is functionally very similar to a hard-limiting neuron of binary inputs, and some very densely integrated artificial neuron architectures are now available. This fact justifies a renewed attempt to build a viable TL gate architecture. We have exploited the capacitive synapse architecture of [15] and [16] to this end and have developed what we call the capacitive threshold-logic (CTL) gate. Although a TL gate operates on binary variables and produces binary outputs, its internal computation is carried out with analog signals. A large fan-in in such an analog environment calls for a tight matching of physical components in hardware implementation. Poly-to-poly capacitors, which are available in all standard mixed-mode CMOS technologies, are the best components in this respect. This is the main reason why we have selected a capacitive neural architecture for adoption as a TL gate. Indeed the CTL gate features an experimentally verified fan-in capacity of at least 250 for equally weighted inputs at a connection density of 3.2 10 mm . Besides, the gate is soft programmable to any symmetric Boolean function by means of threshold adjustment through an external voltage. This feature is most beneficial particularly in those applications involving -out-of- decoding. In this paper, we describe, analyze, and experimentally confirm the operation and performance of the CTL gate. First, in Section II, we briefly present the fundamental aspects of TL. This is followed in Section III by a description of the basic operation and properties of the CTL gate including some of its system applications. A detailed analysis leading to identification of electrical limitations and design constraints is presented in Section IV. Experimental results obtained from a test chip are disclosed in Section V. Finally, in Section VI, conclusions of this work are summarized. II. FUNDAMENTAL ASPECTS OF THRESHOLD LOGIC A threshold gate is defined as an -input logic gate, such that the output of the gate is determined by the following set

0018–9200/96$05.00  1996 IEEE

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of relations if

(1)

if

(2)

are the binary input variables, Here and is the Boolean (switching) logic function realized by the threshold gate. represents the weight corresponding to the th input variable. Although weights are generally treated as real numbers, we assume—without loss of generality—positive integer weights in CTL realizations. represents the gate threshold, which also is treated generally as a real number, but is to be restricted in CTL implementations , where is an integer satisfying to . Therefore, the minimum difference between and in a CTL gate is expected to be 1/2. A Boolean function thus represented by the output of a threshold gate is called a threshold function. Notice that while all threshold functions are, by definition, Boolean functions, not all Boolean functions can be represented as threshold functions. On the other hand, it can be easily shown that all Boolean functions can be realized by a two-level network consisting of TL gates. Furthermore, a TL gate with fixed weights can be soft programmed to many distinct Boolean functions simply by properly adjusting the threshold . An -input threshold-logic gate with , and , for example, will realize an -input or gate. Changing the threshold to will program the gate to the and function. The very same gate can function as a majority gate (for an odd ) or (for an even with ). Threshold gates thus offer a capability to realize many complex Boolean functions with a smaller number of gates and/or fewer logic levels in comparison with the conventional logic gates. This should result in a better areal density and/or a higher processing speed, particularly in those applications involving a large number of input variables. On the other hand, the number of input variables that can be handled by a TL gate is ultimately limited by the linearity of the sum-ofproducts function defined in (1) and (2). The limited resolution attainable with nonlinear processing elements such as bipolar junction transistors (BJT’s) or MOSFET seems to be the main drawback of all previous attempts to build a viable TL gate on silicon.

Fig. 1. Circuit schematic of a CTL gate of m inputs.

stage is equipped with a reset switch. This CTL architecture is a unipolar version of the capacitive neural network configuration proposed in [16]. The gate operates in a two-phase nonoverlapping clock scheme comprising a reset phase defined by the clock and an evaluation phase defined by . In a reset phase, the row voltage is reset to the logic threshold voltage of the first inverter stage of the comparator, while the capacitor . bottom plates are precharged to a reference voltage The resetting feedback of the comparator is removed at the end of . This leaves the row of capacitor upper plates practically floating until the arrival of next reset phase. Throughout this time, only the leakage current of the comparator reset . switch can alter the charge established on the row during Evaluation phase begins with the arrival of . Binary input signals, , are forced onto the columns, and consequently, row voltage is perturbed from . Ignoring, for the time being, the charge the reset level injection and leakage effects associated with the comparator reset switch, and thus assuming row-charge conservation, the perturbation can be expressed as (4) where itance

is row total capacitance including the stray capac, i.e.,

Defining

and setting the reference voltage to III. OPERATION, PROPERTIES, AND APPLICATIONS OF CTL inputs, shown schematically in Fig. 1, A CTL gate of comprises a) a row of weight-implementing capacitors, , which are built in multiples of a unit to satisfy capacitor (3) and b) a chain of identical inverters which functions as a comparator to generate the output. Note that the first inverter

(5) and substituting these expressions together with (3) into (4), we obtain (6) This perturbation is turned into a binary output voltage as described by the following equations for a comparator with

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even number of inverter stages if

(7)

if

(8)

If is odd, then a complementary output is generated. Functionality as a threshold gate can now be proved by defining

and then comparing (7) and (8) with (1) and (2), respectively. A CTL gate has the unique property of soft programmability of the Boolean function it performs. This capability arises from the fact that the threshold , hence the function, is determined by via the row charge established during a reset phase. The function thus programmed is valid for the entirety of the following evaluation phase, but, of course, can be changed by altering in the subsequent reset phase. Unlike conventional dynamic CMOS gates, which necessitate a precharge phase before evaluating each new input vector, a CTL gate is capable of evaluating a large number of successive input vectors in between two consecutive reset phases. This capability is a result of the fact that the evaluation process itself is nondestructive. However, row-charge leakage through the reset transistor acts as a time dependent offset, which slowly degrades the effective threshold in the evaluation phase. Periodic reset restores the threshold before the gate starts malfunctioning. Since the rate of leakage is much slower than the rate by which a CTL evaluates an input vector, a sequence of multiple input vectors can be processed in one evaluation period. Essentially, therefore, a CTL gate represents a dynamic asynchronous logic. CTL gates are directly cascadable in the asynchronous mode of operation. As depicted in Fig. 2(a), all gates are simultaneously reset in , and they simultaneously evaluate in . Also, it is possible to directly cascade CTL gates in a pipelined mode of operation, but in this case the evaluation phases of two successive stages must be controlled by two separate nonoverlapping clocks, and , as shown in Fig. 2(b). We have already applied the CTL concept in parallel counter and serial/parallel multiplier design. The parallel counter was built in a 31-in/5-out configuration using a total of 20 CTL gates arranged in a two-level logic. The sum-of-weights per gate is 32 (in the first level) or 64 (in the second level). It is interesting to note that a functionally equivalent design with conventional logic would have necessitated the complexity of 26 full adders. The fabricated circuit fits into (583 297) m silicon in a 1.2 technology, and operates asynchronously on 31-b vectors at a processing speed of 16 Mvectors/s [17]. 8)-b multiplier application utilizes a 16-b parity The (8 module built with nine CTL gates arranged in an effective logic depth of two. It occupies 0.07 mm silicon and is capable of operating at clock frequencies up to 30 MHz [18]. The versatility of CTL is now being demonstrated with a second party of more complex applications. One of these is a

(a)

(b) Fig. 2. Cascading CTL gates. (a) The asynchronous mode, in which all gates evaluate in  E simultaneously. (b) The synchronous mode, in which signal flow is pipelined with two nonoverlapping evaluation clocks.

rank-order filter (ROF) based on Kar and Pradhan’s algorithm [19], which relies on a -out-of- function, where, and represent the rank and window size, respectively. Implementing this function with a single CTL gate of adjustable threshold leads to an extremely compact ROF bit slice with soft-programmable rank. Another application demonstrating the areal density attainable with CTL involves a ROM in which the corresponding bits of a block of words are stored as or in a CTL gate, whose threshold is set to 1/2. A third application involves a novel image filter algorithm implemented with 16 30-b parallel CTL counters. This design is aimed at high processing speed. To this end, it exploits the ability of CTL to process high-dimensional data in lesser number of logic layers. The prototypes of these three designs are presently being tested. Detailed descriptions, including test results, will be published elsewhere.

IV. ELECTRICAL LIMITATIONS AND DESIGN CONSTRAINTS As explained in Section II, the smallest nominal difference between and in a TL gate is 1/2. According to (6), therefore, the smallest expected magnitude of in

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a CTL gate is given by (9)

whose expectation value is given by (9). Assuming a random distribution in with a standard deviation , defining , and substituting (5) for , we obtain from (13) the following expression for :

In order for the CTL gate output to saturate at the proper rail level, this minimum row perturbation must satisfy (10) denotes the minimum perturbation required for where saturating the output, while the remaining four terms on the right-hand side represent the row-referred offset voltages due to comparator stage mismatch, charge injection, leakage current, and capacitor mismatch, respectively. Assuming a symmetrical inverter, can be expressed as

where is the gain of an inverter stage and is the MOSFET is the minimum perturthreshold voltage. Note that bation required at the input of the final comparator stage, and the total comparator gain up to that node is . is dominated by the random mismatch between the threshold voltages of the first and second inverter stages and can be modeled with

(14) where

Mismatch in small capacitors is mainly due to edge effects, and the resulting standard deviation is only a very weak function of the capacitance [20], [21]. We, therefore, assume that is independent of . Having modeled all offset components, we can now assess the implications of the minimum perturbation condition (10). Substituting (9), (11), (12), and (14) into (10), and assuming a case of sufficiently large sum of weights, where the approximation (15) is justifiable, we arrive at the following lower limit for unit capacitance:

is due to an injection of channel charge onto the row as the reset switch of the comparator is cut off at the end of the reset phase. Its magnitude is given by (11) where

is the magnitude of the charge injected. is the deviation in row voltage due to row charge leakage via reset switch in the evaluation phase. The magnitude of this offset grows in time and reaches a maximum at the end of the evaluation phase. Assuming a time-independent leakage current , this offset can be expressed as (12)

As explained in Section III, all capacitors in a CTL gate are realized in multiples of a unit capacitor . Processrelated systematic errors in the resulting capacitors are thus minimized. Also ignoring nonlinear effects, we attribute solely to the random mismatch among the capacitors attached to the row. To model , we consider a CTL gate under a minimum row-perturbation condition. This condition occurs unit capacitors receive from when a total of inputs. An expression for the resulting row perturbation can be obtained from (4) as follows:

(13)

(16) For an interpretation of this result, first, note from (9) and (15) that minimum perturbation is virtually independent of because is proportional to for a large sum of weights. For the very same reason, however, the injection, leakage, and capacitor mismatch components of the offset increase with the decreasing because these components are inversely . This is why has a lower limit. While proportional to the above-mentioned three components of the offset can be reduced by increasing , both and are invariant to because these two are independent of . Therefore, , the minimum perturbation, which itself is independent of should exceed the sum of these two regardless of the value of . This sets a lower limit on to which the minimum perturbation is inversely proportional. This limit is obtained from the denominator of (16) as follows:

The lower limit of the unit capacitance and the sidelength of the corresponding square-geometry capacitor are plotted in Fig. 3 as a function of the sum of weights for a) , e.g., , e.g., a majority gate, and a nor gate, b) , e.g., a nand gate. Parameter values are c) as follows: V, mV, fC, fA, ms, fF (calculated from (11) of [20] assuming a poly-to-poly oxide of thickness 50 nm, a local-edge variation of standard deviation

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Fig. 3. The minimum unit capacitance and the sidelength of the corresponding square-geometry poly-to-poly capacitor as a function of the sum-of-weights.

Fig. 4. A generic schematic of the  MOS gate [12].

0.05 m, a correlation radius of 0.5 m, and a sidelength of 3.4 m). Note that the case representing the majority gate is the worst case for the lower limit of . This is due to the fact that capacitor mismatch offset is maximized for the majority function, as can be easily deduced from (16). Still, however, the plot in Fig. 3 indicates the possibility of accommodating a sum-of-weights of 256 with 4 m capacitors. Also note that the upper limit of the sum of weights is 530. These figures clearly attest to the very large fan-in capacity of a CTL gate. Another electrical limitation in a CTL gate arises from the dynamic range of row voltage. Suppose all inputs receive a binary-0, that is, . This, together with (15), yields from (6) the following expression for row perturbation:

which, for a gate programmed to implies in magnitude. a negative row perturbation exceeding Since is expected to be around , such a magnitude results in a row-voltage down-surge below the ground. This can be tolerated only if the reset switch of the comparator is implemented with a PMOS transistor, so that the surge does not forward-bias the reset switch junction attached to the row. Now suppose . This leads to

which, for a gate programmed to , implies , and hence, a rowa positive perturbation exceeding voltage upsurge above . In this case charge injection can be avoided only if the switch is implemented with an NMOS transistor. The necessity to select either a PMOS or an NMOS reset switch, therefore, limits the implementable range of as follows:

with an NMOS reset switch, with a PMOS reset switch.

(17)

It is important to note that these threshold limitations do not impair the functional generality of a CTL gate. It suffices to use complements of input variables and adopt the complementary output to implement a Boolean function with an NMOS switch for . Similarly, a CTL gate with a PMOS switch can be programmed to a Boolean function requiring . Having identified the electrical limitations of a CTL gate, we can now present a comparative assessment of a CTL gate with respect to a MOS gate. The latter has been introduced as a static logic gate having the general architecture shown in Fig. 4 [14]. Notice the absence of reset and referencevoltage provisions, and the presence of a threshold adjustment capacitor, or . It is obvious that the architecture of a MOS gate is simpler than that of a CTL gate. Absence of reset makes MOS operationally simpler as well. Furthermore, the gate has no dynamic range limitation as in CTL. However, the relative simplicity of the structure does not necessarily lead to a denser structure because, as explained next, the fan-in is severely limited. Row perturbation in a MOS gate, defined as the difference between the row voltage and the inverter logic threshold

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Fig. 5. Circuit diagram of the test stack. f i marks the output of the gate of fan-in i . Columns are grouped into eight blocks of 1, 2, 4, 8, 16, 32, 64, and 128 unit capacitors to reduce input pin count. However, a capacitor is missing at the crosspoints X 1 6 =f 3 0 and X 32 =f 6 2 .

V. EXPERIMENTAL RESULTS

voltage, is described by (18) is row total capacitance including where and or , and is row charge. Comparing the numerator of this equation with that of (4), one immediately recognizes two process-dependent parameters, and , and , in place of the adjustable voltage . one stray parameter, In [14], an initial UV reduction of is proposed, but since the row floats throughout device lifetime, any future charge build up due to carrier injection cannot be ruled out. The distribution and uncertainty in these three parameters severely limit the sum-of-weights capacity of MOS. The largest reported sum of weights is less than ten, and the prediction is made that it is by no means practical to increase it to 256 [14]. It is the introduction of dynamic reference and reset that does away with the gate initialization problem and eliminates straysensitivity and process-dependence in CTL. This is why a CTL gate can have more than an order of magnitude higher capacity of sum-of-weights. A MOS gate can be programmed by driving the threshold adjustment capacitor with a reference voltage instead of . As can be shown from (18), however, the size of must be comparable to the total of all weight-implementing capacitors in order to be able to program the gate to all possible threshold values using a reference voltage in between two rail levels. In a CTL gate, where no threshold adjustment capacitor is employed, programmability is available at no expense on areal density. From speed point of view, we expect little, if any, disparity between MOS and CTL for a given fan-in. However, at the larger system level, CTL is expected to yield a better speed performance because its superior fan-in generally results in a shorter logic depth.

To test the ideas put forward in previous sections, we have designed a test chip containing several CTL gates. The chip has been fabricated in ORBIT 1.2 double-metal double-poly CMOS technology. The basic test circuit, shown in Fig. 5, consists of a stack of four gates of 30, 62, 127, and 255 unit capacitors each. Inputs to these gates are binary encoded to reduce pin count of the chip. For example, the capacitors of the 255-unit gate are combined into eight separately accessible blocks with 128, 64, 32, 16, 8, 4, 2, and 1 units. A column-driver cell comprising an NMOS column reset switch and an input transmission gate defines a column pitch of 4.0 m. The comparator features an NMOS reset switch to comply with (17) and consists of two inverter stages and a dummy switch attached to its input for charge-injection compensation. Although the overall gain available from two stages is too low to saturate the output for large fan-in, nonsaturation facilitates observability of row dynamics, and hence enables a quantitative assessment of row perturbation. The row pitch defined by the comparator is 7.8 m. Defining the area bounded by column and row pitches as the connection area, we calculate a connection density of 3.2 10 mm . The size of the connection area accommodates a capacitor of size 6.4 m 1.8 m corresponding to a unit capacitance of 7.2 fF. Fig. 6 shows a part of the layout where the comparators and the first seven columns (1-unit, 2-unit, and 4-unit blocks) of all four gates are placed. Notice that column driver cells are staggered to reduce column pitch. Waveforms in Fig. 7 show the measured comparator output voltage in all four CTL gates implementing the or function. They all exhibit the expected response of toggling above when the number of binary-1 inputs equals or exceeds unity. Also observable is the inadequacy of a two-stage comparator for generating saturated outputs in large fan-in gates.

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Fig. 6. Part of the layout of the experimental CTL gate stack where the comparators (upper left quadrant), X 1 ; X 2 , and X 4 column drivers (lower right quadrant), and the associated unit capacitors (upper right quadrant) are shown. THE NOMINAL VALUE

AND

TABLE I EXPERIMENTAL LIMITS

OF

Vr e f

IN

mV

As explained in Section III, a CTL gate offers soft pro. Shown in Fig. 8 grammability through the adjustment of are the output waveforms measured for the case of all gates being programmed to generate a binary-1 only if the number of binary-1 inputs equals or exceeds 14. All gates are seen to successfully implement the 14-out-of- function.

Fig. 7. Experimentally obtained output voltage waveforms for all four gates performing the OR function. Notice that just one binary-1 input suffices to toggle the output above Vt h . Also obvious from all waveforms is that a two-stage comparator cannot produce a saturated output in response to a single binary-1 input.

The results of a different set of experiments conducted for the purpose of characterizing the sensitivity of a CTL gate to the reference voltage are given in Table I. This table compares the nominal value of calculated from (5) with the in which the gate remains functional. measured range of Note that each of the four different gates has been tested for or, 14-out-of- and majority functions. Except for the cases of majority-programming of the 127 and 255 fan-in gates, the indeed falls inside the measured range. nominal value of These results clearly confirm the prediction based on Fig. 3 that very large fan-in gates are possible in CTL. The two cases of exception can be explained with a systematic capacitance mismatch error made in the physical design of these gates. The offset arising from this error increases with and reaches a maximum for the majority function. As mentioned previously, the comparators are equipped with only two stages to facilitate observability of row dynamics. This has precluded buffering for speed. Therefore, no meaningful dynamic testing could have been conducted on the experimental gates. Instead, the dynamic behavior has been evaluated with post-layout HSPICE simulations. Fig. 9 shows simulated waveforms of both two-stage and four-stage comparator outputs for the or function in all four gates. These

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Fig. 8. Experimentally obtained output waveforms for all four gates performing  14-out-of-m function. Notice that outputs toggle above Vt h only if 14 or more inputs receive a binary-1.

waveforms depict a reset phase followed by an evaluation phase in which a single input rises to binary-1 while all other inputs remain in a binary-0 state. The propagation delay increases from 6 ns to 12 ns as the fan-in increases from 30 to 255. The apparent irregularity of the rate of increase is a result of the systematic capacitor mismatch error mentioned previously. Simulations, conducted after correcting the error in the extracted circuit file, indicate a logarithmic dependence on fan-in. The dependence on fan-in is related to the fact that most of the propagation delay occurs in the front-end units of the inverter chain, where signal swing is still small. The larger the fan-in, the greater the number of inverter units operating in this slower state because the worst-case row perturbation is inversely proportional to fan-in. The favorable speed performance indicated by these simulations were later confirmed on the parallel counter and multiplier circuits, as mentioned in Section III. VI. CONCLUSION The premise of this work is the observation that the synthetic advantages offered by threshold logic can only be exploited with a dense, fast, and standard-CMOS compatible logic gate of large fan-in capacity. With these objectives in mind, we have developed a generic threshold-logic gate in which the key

Fig. 9. HSPICE simulation results for all four gates performing the OR function. Note that following a reset phase ending at about t = 5 0 ns, a single input is raised to binary-1 at t = 8 0 ns. t P L H is the corresponding propagation delay time.

arithmetic operation of sum-of-products is carried out by an array of capacitors while thresholding is done by a comparator in the form of an inverter bank. Predictions based on analytical and numerical evaluation have been tested on a chip containing a stack of four such gates. The following is a summary of the experimentally confirmed conclusions of this work. • The structural simplicity of a capacitive connection leads to a high connection density limited only by the size of I/O devices, as exemplified by the experimental test stack, where density is above 3.2 10 mm . The silicon area efficiency thus offered has been confirmed experimentally with further application of the CTL concept in the form of parallel counter and multiplier circuits. • The gate can be used synchronously or asynchronously, but it also needs to be periodically reset. However, the frequency of this operation is very low even in the case of a very large fan-in.

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• The experimentally confirmed fan-in of 255 represents two orders of magnitude improvement over the conventional and/or gates. The simulated propagation delay is a mere 12 ns even at this level of fan-in. The high processing speed offered by CTL has been experimentally confirmed on parallel counter and multiplier designs. • The gate can be soft programmed by setting the threshold with a dc voltage. Although the weights remain fixed, a very large set of Boolean functions can still be pro-out-ofgrammed. A straightforward example is the function with programmable , which is of significant use in signal processing, as demonstrated by the ROF application.

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¨ Hakan Ozdemir (M’87) received the B.S. and M.S. degrees in electronics from ˙Istanbul Technical University, ˙Istanbul, Turkey, in 1982 and 1985, respectively, and the Ph.D. degree in electronics from Southampton University, Southampton, U.K., in 1992. Since 1992 he has been employed as an Assistant Professor at the Electronics and Communications Engineering Department of ˙Istanbul Technical University. He also works as a Senior Designer and Project Manager at ETA ASIC Design Center, ˙Istanbul. His main research area is the transistor-level design of digital and analog circuits. His research interests also include technology development for micromechanical structures and interface circuits for microsensors. ¨ Dr. Ozdemir was an Honors Scholar of the Turkish Scientific and Technological Research Council from 1988 to 1992.

REFERENCES [1] M. Dertouzos, Threshold Logic: A Synthesis Approach. Cambridge, MA: M.I.T. Press, 1965. [2] S. T. Hu, Threshold Logic. Berkeley, CA: University of California Press, 1965. [3] P. M. Lewis and C. L. Coates, Threshold Logic. New York: Wiley, 1967. [4] R. O. Winder, “The status of threshold logic,” RCA Rev., vol. 30, pp. 62–84, 1969. [5] S. Muroga, Threshold Logic and Its Applications. New York, Wiley, 1971. [6] A. L. Larson, “A TTL compatible threshold gate,” IEEE J. Solid-State Circuits, vol. SC-8, pp. 470–471, 1973. [7] B. A. Wooley and C. R. Baugh, “An integrated m-out-of-n detection circuit using threshold logic,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 297–306, 1974. [8] K. J. Schultz, R. J. Francis, and K. C. Smith, “Ganged CMOS: Trading standby power for speed,” IEEE J. Solid State Circuits, vol. 25, pp. 870–873, 1990. [9] C. L. Lee and C.-W. Jen, “Bit-sliced median filter design based on majority gate,” in Proc. Inst. Elec. Eng.-G, vol. 139, pp. 63–71, 1992. [10] J. M. Quintana, M. J. Avedillo, and A. Rueda, “Hazard-free edgetriggered D flipflop based on threshold gates,” Electron. Lett., vol. 30, pp. 1390–1391, 1994. [11] J. M. Quintana, M. J. Avedillo, A. Rueda, and J. L. Huertas, “Practical low-cost CMOS realization of complex logic functions,” in Proc., 12th European Conf. Circuit Theory and Design, 1995, pp. 51–54. [12] T. Shibata and T. Ohmi, “A functional MOS transistor featuring gatelevel weighted sum and threshold operations,” IEEE J. Solid-State Circuits, vol. 39, pp. 1444–1455, 1992. [13] , “Neuron MOS binary-logic integrated circuits—Part I: Design fundamentals and soft-hardware-logic circuit implementation,” IEEE Trans. Electron Devices, vol. 40, pp. 570–576, 1993. , “Neuron MOS binary-logic integrated circuits—Part II: Sim[14] plifying techniques of circuit configuration and their practical applications,” IEEE Trans. Electron Devices, vol. 40, pp. 974–979, 1993. [15] U. Cilingiro˘ ¸ glu, “Capacitive synapses for microelectronic neural networks,” in Proc. IEEE Int. Symp. Circuits and Systems, 1990, pp. 2082–2985. [16] , “A purely capacitive synaptic matrix for fixed-weight neural networks,” IEEE Trans. Circuits Syst., vol. 38, pp. 210–217, 1991. ¨ [17] Y. Leblebici, H. Ozdemir, A. Kepkep, and U. Cilingiro˘ ¸ glu, “A compact parallel (31, 5)-counter circuit based on capacitive threshold-logic gates,” in Dig. Tech. Papers, European Solid States Circuits Conf., 1995, pp. 390–393. ¨ [18] Y. Leblebici, H. Ozdemir, A. Kepkep, and U. Cilingiro˘ ¸ glu, “A compact (8 2 8)-bit serial/parallel multiplier based on capacitive threshold logic,” in Proc. European Conf. Circuit Theory and Design, 1995, pp. 55–58. [19] B. K. Kar and D. K. Pradhan, “A new algorithm for order statistic and sorting,” IEEE Trans. Signal Processing, vol. 41, pp. 2688–2694. [20] J.-B. Shyu, G. C. Temes, and K. Yao, “Random errors in MOS capacitors,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1070–1076, 1982. [21] J.-B. Shyu, G. C. Temes, and F. Krummenacher, “Random error effects in matched MOS capacitors and current sources,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 948–955, 1984.

Asım Kepkep (S’92) received the B.S. and M.S. degrees in electronics from ˙Istanbul Technical University, ˙Istanbul, Turkey, in 1991 and 1994, respectively. He is presently working toward a Ph.D. degree at the University of Illinois at UrbanaChampaign. Since 1991 he has been working as a Research Assistant at the Electronics and Communications Engineering Department of ˙Istanbul Technical University. Between 1992 and 1995, he was also with ETA ASIC Design Center, ˙Istanbul, as a designer working on cell-based and full-custom ASIC development. His research interests are in the area of gate and transistor level design of VLSI circuits and in simulation and modeling of semiconductor devices. In 1994, Mr. Kepkep received an Honors Scholarship of the Turkish Scientific and Technological Research Council.

Banu Pamir (S’92) received the B.S. and M.S. degrees in electronics from ˙Istanbul Technical University, ˙Istanbul, Turkey, in 1988 and 1991, respectively. Since 1988 she has been working as a Research Assistant at the Electronics and Communication Engineering Department of ˙Istanbul Technical University, where she also studies toward a Ph.D. degree. From 1992 to 1994, she was also with ETA ASIC Design Center, ˙Istanbul, developing fullcustom mixed-mode industrial ASIC’s. Her research interest is in the area of microelectronic implementation of emerging logic techniques.

Yusuf Leblebici (S’88–M’91), for a photograph and biography, see p. 1024 of the July issue of this JOURNAL.

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U˘gur Cilingiro˘ ¸ glu (M’86) received the M.S. degree in electrical engineering from ˙Istanbul Technical University, ˙Istanbul, Turkey, in 1973, and the Ph.D. degree in microelectronics from Southampton University, Southampton, U.K., in 1978. In the years 1973–1984 and 1986–1988, he held Assistant Professor and Associate Professor positions at ˙Istanbul Technical University, where he has been working as a Professor since 1991. He was on the faculty of the Electrical Engineering Department of Texas A&M University, College Station, TX, between 1984 and 1986 and 1988 and 1991. He presently holds an adjunct professorship at the same department. Prior to 1984, he worked as a consultant with the Turkish Scientific and Technological Research Council contributing to the establishment of a semiconductor technology R&D facility at Kocaeli, Turkey. Between 1986 and 1988, he was a consultant to Teleta¸s AS, ¸ organizing industrial training courses on CMOS technology and ASIC design. He spent the summer of 1990 at Hewlett Packard, Manufacturing Test Division, where he conceived and developed the capacitive pin-open board-testing technique known today as HP TestJet Technology. Presently he is holding the position of academic coordinator at ETA ASIC Design Center, ˙Istanbul, Turkey. He holds several U.S. patents, and is the author of the book Systematic Analysis of Bipolar and MOS Transistors (Artech House, Norwood, MA, 1993). His research activity in the past has involved all aspects of microelectronic circuits, devices, and technology. Most recently, he has been active in the area of engineered intelligence on silicon. Dr. Cilingiro˘ ¸ glu received a CENTO Scholarship in 1973, a Fulbright Research Fellowship in 1984, and an Eta Kappa Nu Outstanding Professor award in 1991.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 8, AUGUST 1996

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