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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 2, FEBRUARY 2015

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A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter for Sub-mW Energy Harvesting Applications Inna Vaisband, Student Member, IEEE, Mahmoud Saadat, Student Member, IEEE, and Boris Murmann, Senior Member, IEEE

Abstract—Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been standard CMOS process and simulation simulated in a 0.25 results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and . The power conversion deliver a maximum load current of 100 efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%. Index Terms—Charge pump, dynamic power management, switched-capacitor converter.

I. INTRODUCTION

W

IRELESS sensors have become increasingly popular in applications such as smart buildings and structures, industrial control, and health monitoring. Typically, batteries are the energy sources for these sensors; however, they have a limited lifetime and therefore need to be replaced or recharged. Moreover, they significantly increase the size and cost of the sensor. An alternative approach to power wireless sensors is ambient energy harvesting [1]–[5]. In an ambient energy harvesting sensor, a transducer converts a form of ambient energy such as light, vibration, or temperature difference, to electrical energy.

Manuscript received May 28, 2014; revised August 03, 2014 and September 05, 2014; accepted September 20, 2014. Date of publication November 11, 2014; date of current version January 26, 2015. This paper was recommended by Associate Editor F. M. Neri. I. Vaisband is with the Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627 USA (e-mail: vaisband@ece. rochester.edu). M. Saadat and B. Murmann are with the Department of Electrical Engineering, University of Stanford, Stanford, CA 94305 USA (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSI.2014.2362971

Then, a power management circuit converts the volatile electrical power generated by the harvester to a regulated power source for sensor circuits. Ideally the power management circuits for low-power energy harvesting should meet four design criteria [6]: 1) the ability to operate across wide input voltage and power ranges; 2) high efficiency across the operating range; 3) accurate output voltage regulation; 4) small size. The power management circuit can be implemented using an inductor-based DC-DC converter, linear regulator, or a switched-capacitor DC-DC converter [7]–[21]. Inductor-based DC-DC converters are efficient at high current levels but they require a bulky off-chip inductor, and therefore they do not meet the size requirement of compact energy harvesting applications. Linear regulators exhibit relatively small area and can be fully integrated in standard CMOS processes. The voltage supplied by a linear regulator cannot be higher than the input voltage. In addition, the efficiency of linear regulators decreases with higher input to output dropout voltage. Alternatively, switched-capacitor (SC) DC-DC converters have high efficiency at low current levels and can be fully integrated in standard CMOS processes. Therefore, we consider the design of a switched-capacitor based power management circuit for energy harvesting applications in this paper. Several power management circuits based on the switchedcapacitor architecture have been published in the literature. Reference [1] describes a design for sub-milliwatt application to extract the maximum power from a thermoelectric source but it does not regulate the output voltage. The work of [4] describes the design of a reconfigurable charge pump, but it targets a maximum output power of just 10 and the reported peak efficiency is only 65%. Reference [22] presents a reconfigurable switched-capacitor DC-DC converter with variable frequency but it is designed for operation with a fixed input voltage (1.2 V). Reference [2] demonstrates a reconfigurable charge pump converter operating efficiently over a wide input voltage range but it is designed for load currents in the range of several tens of milliamperes, increasing the current budget for controller design. In our target power range, such a high power controller cannot be adopted. Existing reconfigurable switched-capacitor converters [11]–[13], [16], [22]–[32] are based on optimization heuristics. Alternatively, the proposed power management approach is based on a closed-form power expression and proposes a control algorithm that automatically reconfigures both the gain ratio and frequency of the converter, adaptively optimizing the power efficiency. The proposed closed-form expression for

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Fig. 1. Series-parallel charge pump with flying capacitors connected (a) in phase, and (b) in parallel to the load during the series to the input during the phase.

near-optimal power efficiency is the first theoretical result to provide an important, intuitive insight into power dissipation of a wide range of SC converters. Our design has the following characteristics. First, to support a wide input voltage range, the switched-capacitor converter is designed to be reconfigurable: It adjusts its voltage gain and frequency based on the operating condition of the converter. Second, our design is targeted to operate with DC voltages from 0.5 V to 2.5 V. This range covers operation with solar cells, high voltage thermoelectric generators and rectified AC sources. Finally, since a wireless sensor typically consumes tens to hundreds microwatts of power, we aim at delivering at least 100 W of power to the load (comprised of sensor circuits). The target output voltage is 1.2 V and the regulation window is from 1 V to 1.4 V. The rest of this paper is organized as follows. Section II presents the architecture of the converter in detail. In Section III, a set of basic and generic closed-form equations is derived to describe the output voltage and power consumption of the converter. Section IV discusses the control design based on the equations found in Section III. The controller is designed to meet load regulation requirements, while maintaining high efficiency. To evaluate the voltage regulation algorithm, MATLAB simulation results are provided at the end of this section. Section V presents transistor-level circuit design and simulation results. II. SERIES-PARALLEL RECONFIGURABLE SC CONVERTER A. Programmable Gain In order to generate multiple voltage gain ratios, we use the series-parallel charge pump architecture in our design [29], [33], [34]. A series-parallel charge pump uses two clock phases and can step-up or step-down the input voltage by changing the connection of capacitors from one phase to another. Fig. 1 shows the basic of operation of this architecture for the step-down case. , the flying capacitors are connected During the first phase in series and charged by the input voltage, (the output capacitor is connected to the load). The charges stored on the flying capacitors are determined . During the based on the connection of the capacitors in , the capacitors are connected in parallel to second phase the load and therefore the stored charges are redistributed. Using the charge conservation principle, we can determine the voltage during the steadygain ratio, and thus the output voltage state operation. The generalized form of the series-parallel architecture is known as general transposed series-parallel (GTSP) architecture in the literature [34]. Fig. 2 illustrates this architecture and it can be shown that the conversion ratio for this case is:

Fig. 2. General transposed series-parallel charge pump configuration with flying capacitors connected (a) in series within each of the columns during the phase , and (b) in parallel within each of the rows during the phase .

, where the is the number of flying capacitors in the -th column connected in series to the input voltage in . The voltage gain equation implies that the GTSP architecture and . These gain can generate many gain ratios between ratios can be calculated from the following equation

(1) The number of available voltage gain ratios increases exponentially with [34]. Having more gain ratios increases the accuracy of the output voltage. However, it also increases the number of flying capacitors, increasing the chip area, complexity of the switch network, and switching losses. Therefore, should be chosen based on the requirements on an optimal the output voltage regulation. As an example, possible conversion gain ratios and output voltage are evaluated here for two and . In this simulation, the value of values of : each flying capacitor is 200 pF and the charge pump frequency is 1 MHz. The input voltage varies from 0.5 V to 2.5 V and load . With four flying capacitors, 15 current varies from 0 to 100 voltage gain ratios are generated, exhibiting voltage regulation of 1.2 V 200 mV. With six flying capacitors, the number of gain ratios increases to 81, exhibiting better voltage regulation 100 mV. The higher number of flying capacitors of 1.2 V significantly improves the output voltage regulation at the cost of chip area and the complexity of the switch network. In this design, since the target output voltage range is 1.2 V 200 mV, we use four flying capacitors. Also, out of 15 available gain ratios generated by four capacitors, eight gain ratios are sufficient to regulate the output voltage within the target window. The selected gain ratios are: 0.5, 0.6, 0.75, 1, 1.33, 1.66, 2, 2.5. Some applications demand tighter output voltage regulation than 200 mV. In that case, a larger number of flying capacitors should be used to improve the regulation range of the output voltage. The proposed control algorithm still applies to a converter with more flying capacitors. Alternatively, a compact linear regulator can be added to the output of this DC-DC converter. Since the drop-out voltage for that linear regulator is small, the impact on the overall efficiency will be limited. Under no-load and lossless conditions, the output voltage of the converter only depends on the input voltage and the conversion gain . However, as the load curincreases, the output voltage drops linearly prorent portional to the load current. This is due to the effective output resistance of the converter. Furthermore, the switching loss of the converter and the nonzero source resistance degrade the regulation and efficiency of the converter. To understand the effect

VAISBAND et al.: A CLOSED-LOOP RECONFIGURABLE SWITCHED-CAPACITOR DC-DC CONVERTER

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Equations (3) and (4) imply that the source resistance is also much smaller than , (5)

Fig. 3. Charge pump model [23].

of these nonidealities on the operation of the converter, a suitable model is presented in the next section. Using this model, we derive equations for the output voltage and efficiency of the converter. Then, the derived equations are used to design an algorithm to control the reconfigurable charge pump converter in a power efficient manner.

We use this assumption and neglect the effect of to simplify the calculation of the output voltage and efficiency in the rest of this paper. A scale factor is used in this work to define a . Substituting the shunt resistance as (5) and in (2), and output resistance neglecting the effect the source resistance, the output voltage is:

B. Simplified Model for an Open-Loop SC Converter The steady-state behavior of an SC converter can be modeled using a two-port circuit. This circuit has three components: , and a shunt an ideal transformer, an output resistance [23]. The ideal transformer models the theoresistance retical no-load gain of the SC converter. The output resistance accounts for the charge redistribution losses, and the shunt resistance models the switching loss and gate driving loss as well as loss due to parasitic capacitances [35]. The output voltage in steady state can be found by analyzing the circuit in Fig. 3: (2) is the input voltage, is the input source resiswhere is the load current. tance, and is a function of the switching frequency The value of , the charge transfer capacitors , and resistance of the in general switches. Finding a closed-form equation for is a complex problem and may not lead to useful results. However, Seeman and Sanders [23] developed closed-form for two asymptotic cases: The slow equations for switching limit (SSL) and the fast switching limit (FSL). In the SSL case, the switches and all the other conductive elements are assumed to be ideal. The switching period is this case is longer than the charging time constant, and the current flow is therefore impulsive. For the FSL case, the switch resistances dominate and the capacitors act as voltage sources. Thus, the capacitors do not approach equilibrium state, and the current flow is therefore nearly constant. In this design, the operation of the converter is close to the SSL case, because the typical time constant of charging each flying capacitor with integrated switches is shorter than the switching period. It can be shown (see [23, eq. (9)]) that under the SSL condition, the following equation can be used to calculate the output resistance of the converter: (3) During the first phase of the operation, the flying capacitors are charged within the half of the switching period by the input . To assure the SSL asvoltage source via source resistance sumption, the source resistance should meet the following condition: (4)

(6) As this equation implies, the voltage drop increases with the and can be compensated by increasing either load current, the gain or the switching frequency. Total power loss in a charge pump is determined by the power , , and , shown in Fig. 3, dissipated in resistors

(7) The power loss under the SSL assumption can be rewritten by , , , and substituting in (6) into (7), yielding, (8) The power efficiency of the system is, therefore, governed by the clock frequency and exhibits parabolic behavior with . The power loss within the converter is dominated by the voltage drop at low frequencies and increases term: with larger load currents, degrading the power efficiency of the converter. At high switching frequencies, the power loss is dominated by the gate driving and switching loss. C. Efficient Voltage Regulation Given a specific conversion ratio , a regulating frequency can be determined based on (6) to generate the target output voltage, . (9) To minimize the power conversion losses, a certain gain setting, , can be found to minimize in (9), yielding (10) The dependency of the power loss and switching frequency on voltage gain is illustrated for a specific case in Fig. 4. In this plot, frequencies that regulate the output values are shown for voltage and the corresponding different gain values , exhibiting the minimum power loss at and . and values that regulate The precise the output voltage while minimizing the power conversion

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Fig. 5. Power loss (normalized by the output power frequency for a set of parameters , and . Fig. 4. Regulating frequency (normalized by the output power a set of parameters , and

[MHz] and power loss ) for different gain values , ,

,

) vs. switching ,

Fig. 6. Frequency , regulating frequency [%] (normalized by the output power , of system parameters , and , and gain values

and power loss ) for a set , .

[%] and ,

.

losses can be determined based on (9) and (10). However, the in (10) leads to a complicated closed-form equation for expression that is impractical for implementation. Therefore, and a simpler algorithm to operate the converter near needs to be developed. This algorithm is presented in the following section. D. Voltage Regulation at Near-Minimum Power Loss and To simplify the closed-form expressions for , first we study the dependency of the power loss on frequency for a specific voltage gain. Fig. 5 illustrates the , , power loss vs. frequency when: , , and . According to this plot, minimum power loss occurs at 3.75 MHz but we also observe that the power loss is almost constant at frequen) cies near (determined based on (11) (12) is larger than 250 in the region of interest, Note that meeting the SSL condition in (3) for all practical values of in this work. The frequency in (11) is proportional to the load and can be evaluated in hardware using a varicurrent able-gain current sense amplifier. Operating the SC converter does not guarantee minimum power dissipation at in (10). However, the power loss at switching frequencies that are close to the frequency , does not vary significantly. that exhibits Thus, if the regulating frequency minimum power loss is close enough to the frequency , then the power loss is near its minimum value. The frequencies , , and power dissipated within the regulating frequency are shown SC converter operated at a corresponding in Fig. 6 for different gain values . To achieve output regulation at near-minimum power loss, the SC converter should that meets both the regulation operate at a frequency [in (9)] and near-minimum power loss [in (11)] requirements at minimum gain . In the example shown in is Fig. 6 the near-optimum frequency , causing slightly higher lower than power loss than .

,

This approach leads to a simple control algorithm that can be efficiently implemented in hardware. In addition, due to the low sensitivity of the converter to frequency variations around (see Fig. 5), PVT variations are expected to be efficiently mitigated with the proposed regulation approach. The control algorithm is described in more detail in the following section. III. PROPOSED CONTROL ALGORITHM FOR EFFICIENT VOLTAGE REGULATION Summarizing the results of the previous section, the control algorithm scales the switching frequency based on the load current for high efficiency conversion and changes the gain value, , for the output voltage regulation requirements. The controller block senses the load current and output voltage and varies the gain ratio and switching frequency as control parameters. Given a set of available discrete voltage gains , the corresponding set of frequencies can be determined based on (12), constituting a set of gain-frequency pairs that satisfy the near-minimal power loss requirement. To regulate the output voltage at near-minimal power loss, the controller should find the pair that satisfies the regulation requirement. The control algorithm shown in Fig. 7 finds the solution gain and frequency. The operation is based on two regulating steps and a query. During the fine regulation step, the frequency is scaled lin. Once the output voltage is settled, it is comearly with pared against the target output voltage (1.2 V). If regulation is not met, the gain setting is increased (decreased) if the output voltage is too low (high) and the frequency is updated again.

VAISBAND et al.: A CLOSED-LOOP RECONFIGURABLE SWITCHED-CAPACITOR DC-DC CONVERTER

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Fig. 7. The proposed algorithm for voltage regulation at near-minimal power loss.

This loop continues until the output voltage is within the regulation window. To avoid unstable operation of the gain control loop, hysteretic comparators and a timing circuit are implemented which is described in Section IV-B. The loop is guaranteed to settle because for any combination of input voltage and load current, there is a gain setting that meets the regulation requirement. To evaluate the control algorithm, the input voltage, , is swept from 0.5 V to 2.5 V in 0.1 V steps. For every value of the input voltage, the load current is varied from 0 (no load) to 100 (full load) in 10 step. Fig. 8 shows the MATLAB simulation results. For every value of the input voltage and load current , the near-optimal configuration and the switching frequency are calculated based on the algorithm shown in Fig. 7. Then the output voltage and efficiency are calculated. The simulation results confirm that over the entire range of the input voltage and load current, the output voltage remains within the regulation limits. Furthermore, the postulated efficiency of the converter is higher than 74% for all cases, and exhibits 83% peak efficiency. Under similar load constraints, the converter in [22] is able to achieve 70% efficiency. Peak efficiency of 58% to 81% is reported for power management circuits [1], [3], [4], [26]. The proposed power management system, therefore, yields higher power efficiency than the existing SC DC-DC converters operating under similar constraints. The limited set of discrete gains, and the proposed near-optimal power approach degrade the power efficiency compared to the optimal power solution with continuous gain values. The difference between power efficiency of the two approaches is shown in Fig. 9, showing that the near-optimal solution is less efficient than the optimal solution by at most 3% for all values. Note that both the and are proportional to (see (8)–(12)), yielding an optimal and ) near-optimal efficiency that does not depend on . The difference between the optimal and near-optimal efficiency shown in Fig. 9 is therefore not a function of the load current. Thus, the power conversion with near-optimal voltage regulation leads to high efficiency operation of the converter.

Fig. 8. Output voltage regulation in Matlab for step-up power conversion for step-down , and .

and ,

Fig. 9. Efficiency degradation of the near-optimal solution compared to the optimal power solution.

IV. DESIGN VALIDATION IN A 0.25 PROCESS

STANDARD CMOS

The closed-loop converter is designed in a 0.25 standard CMOS process. The typical output power is 120 and the die size is 1.5 mm 1.7 mm. The power density of the proposed converter is therefore 47 . The design of the open-loop converter is presented in Section IV-A. The implementation of the proposed controller is discussed in Section IV-B and top-level simulation results of the closed-loop converter are presented in Section IV-C. A. Design of the Open-Loop Converter The open-loop converter consists of four flying capacitors, eighteen switches and their driving circuits, and a multiplexer. The digital multiplexer circuit selects the correct gate signal for each switch based on three gain selection bits, (corresponding to the eight gain settings). Fig. 10 shows a simplified schematic diagram of the open-loop converter.

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Fig. 12. Simulation of the open-loop converter for all gain settings , , , , . Fig. 10. Simplified schematic diagram of the open-loop converter.

. The gain setting is increased from 0.5 to 2.5 every 62.5 . To verify the accuracy of the model presented in Section II-B, a behavioral model is created using verilogA and simulated under the same conditions. The blue and red waveforms represent the output voltage of the transistor-level circuit and the behavioral model, respectively. The steady-state error between the two waveforms is less than 20 mV for all gain settings. The transient error is higher (less than 50 mV) mainly because the initial voltages of the flying capacitors are not included in the behavioral model. B. Design of the Proposed Controller

Fig. 11. (a) Switch realization for a single flying capacitor, and (b) the bootstrapped switch.

Fig. 11(a) shows a flying capacitor and five switches connecting it to the input and output rails, ground, and the bottom and top plates of the following capacitor. The flying capacitors are implemented using metal-insulator-metal (MIM) capacitors to minimize the parasitic bottom-plate capacitance to the substrate. The post-layout extraction shows only 1% parasitic capacitance (2 pF for each flying capacitor) leading to a negligible impact on the overall efficiency of the converter. The switches connecting the bottom plate of the flying capacitors to ground have been implemented using NMOS transistors. The gate driver for this switch is a simple digital buffer. For the other switches, NMOS transistors are used to conduct the capacitors currents but since the source voltage of those switches depend on the configuration of the converter and the input and output voltages, they utilize the gate bootstrapping technique [36]–[38]. Fig. 11(b) shows the circuit for gate bootstrapped switches. This technique guarantees the conduction of each switch by providing a gate-source voltage higher than the threshold voltage of the main switching transistor. The sizes of the main NMOS switches determine the gate driving loss and charge transfer time-constant of the converter; therefore need to be optimized. Although the SSL condition requires complete settling of the charge transfer within each half cycle, the switches are sized just wide enough to allow several time-constants for the charge transfer at the highest switching frequency to reduce the gate driving loss. The size of bypass capacitors depends on the value of source resistance. The source resistance of is used in this paper to meet the SSL . requirement, yielding a bypass capacitance of Fig. 12 shows the simulation results of the open-loop converter. Here, the input voltage is 1 V, the clock frequency is 2 MHz, the load capacitance is 5 nF and the load current is 10

The simplified block diagram of the controller circuit is shown in Fig. 13. The controller is designed to implement the algorithm described in Fig. 7 and it has four key building blocks: 1) A load current sensor. Fig. 14 shows a simplified block diagram of this block. We use the current conveyor concept [39] consisting of two matched PFET devices with the width ratio of 200 to 1. The wide device conducts the current to the load and the narrow device conducts 0.5% of the load current to be used for frequency generation. This block is active only when the output voltage of the converter falls inside the regulation window. This condition is detected by the output voltage comparators and indicated by (short form of Power GOOD) signal. 2) A current-controlled oscillator (CCO) to generate the clock according to (11). Since this block has to support a wide range of oscillation frequency, a time-based oscillator as shown in Fig. 15 has been employed. The sensed current is fed into this oscillator and mirrored to charge and discharge the capacitor . The voltage of this capacitor is compared to reference voltages proportional to the input voltage to generate CLK signal. The discharge rate of the capacitor is designed to be much faster , creating a high duty cycle (90% in this design) at CLK output. Using a combinatorial logic circuit, the CLK signal is used to generate the two non-overlapping clock phases, oscillating with frequency (13) is a reconfigurable current-mirror ratio where to implement the configuration dependent term, , in (11). Therefore, this oscillator is well-suited to generate the desired clock frequency described by (11). It should be noted that is implemented

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the counter, the gain setting, for its duration to allow the settling of the output voltage before the gain setting is updated. The duration of hold pulse should be determined based on the settling time of the output voltage. This settling time is proportional to the clock frequency, output resistance, and load capacitor. It should be noted that the converter does not require additional start-up mechanisms. The conversion is activated when input voltage is about 0.6 V with the initial gain and frequency values of, respectively, 0.5 and 200 KHz.

Fig. 13. The block diagram of the closed-loop charge pump.

Fig. 14. The block diagram of the load current sensor.

Fig. 15. The block diagram of the current-controlled oscillator.

with MIM capacitors, the same type of capacitor used to implement flying capacitors to improve matching. 3) Two hysteretic voltage comparators to compare the output voltage against the reference voltage (1.2 V) and decide if the gain value should be increased or decreased in the next control cycle. 4) An up-down counter to generate the gain setting for the charge pump based on the output of voltage comparators. When the gain setting is updated, a short reset pulse is generated and sent to the charge pump core to reset the charge on all flying capacitors, smoothing the transitions of the output voltage from one gain setting to another and limiting the potential spike currents and voltages occurring at the gain transitions. The flying capacitors recharge to new values within the first half cycle after the reset period. Furthermore, the gain transition triggers the generation of a hold pulse. This pulse holds the state of

C. Simulation Results of the Closed-Loop Converter To evaluate the performance of the closed-loop converter, line regulation and load regulation simulations are performed at the transistor level. The results of these two simulations are presented in this section to show both the steady-state and transient response of the output voltage when input voltage and load current vary across the operating range of the converter. Also, the efficiency of the converter is evaluated at the end of this section for a single operating point of and . 1) Line Regulation Simulation: Fig. 16 shows the simulation results of the converter when the input voltage is swept from 0.6 V (minimum) to 2.4 V (maximum) and vice versa. In this simulation, the load current is 20 and the values of the flying capacitors and load capacitor are 200 pF and 5 nF respectively. The staircase waveform (magenta) shows how the gain setting is updated as input voltage (blue) varies to maintain the output voltage (red) inside regulation boundaries (orange lines). This simulation verifies the functionality of the closed-loop control over the entire input-voltage range. 2) Load Regulation Simulation: Fig. 17 shows the load regulation simulation results of the closed-loop converter. In this simulation, the input voltage is 1.8 V and load current varies from 0 (no-load) to 100 (full-load). Similar to the previous simulation, the values of the flying capacitors and load capacitor are 200 pF and 5 nF respectively. In this simulation, the converter settles at the gain setting of 0.75. The no-load output voltage at this gain setting is 1.35 V. Over the entire load current range, the gain setting is fixed but the switching frequency tracks the load current according to (12) to improve the efficiency. 3) Efficiency Simulation Results: The efficiency of the closed-loop converter is evaluated for and . The source resistance is 10 to meet the SSL requirement. Fig. 18 shows the steady state waveforms of the output voltage (red), input current (blue), and load current (magenta) for several switching cycles. In this simulation, the charge pump converter operates at frequency of 3.06 MHz and gain of 0.75. The average current from the input is 85 . Therefore, the power conversion efficiency in this case is: (14) Note that the efficiency of the converter with the proposed approach does not necessarily decrease with frequency, but de, input voltage pends on the configuration parameter and load current . For specific , , and , the converter may, therefore, exhibit higher than 80% efficiency at higher, , frequencies, as shown in Fig. 8. The corresponding power loss of the converter is 31.1 . Fig. 19 shows the loss breakdown of the converter. Five loss

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Fig. 18. The steady-state operation of the charge pump circuit. , , , , . Fig. 16. Line regulation simulation of the closed-loop converter when ramps up (down) from 0.6 V (2.4 V) to 2.4 V (0.6 V) in 10 ms. , , , . The two y-axes stand for the gain values (range from 0.5 to 2.5), and the corresponding indices in the array of gains (range from 0 to 7).

Fig. 19. The pie diagram of the loss contributors during the steady-state opera, , , , , tion. , .

Fig. 17. Load regulation simulation of the closed-loop converter when load to 100 . , , , current varies from 0 .

components contribute to the overall power loss: 1) Inherent loss), which charge redistribution loss of the converter ( accounts for 15.5 or half of the total loss. 2) Gate driving and switching loss, ( loss) is 8.5 . 3) Loss of the current sensor and the current-controlled oscillator. These two blocks consume 4 of power to generate non-overlapping clock phases running at 3.06 MHz. 4) Controller and reference generator loss is just 0.8 . 5) The loss of the internal voltage selector circuit is 1.2 . Our model shown in Fig. 3 predicts a conversion efficiency of 86%. The 6.5% discrepancy is mainly due to the conduction loss of the switches and mismatch between the calculated output resistance and actual output resistance. In the model developed based on the SSL condition (Fig. 3), switches were assumed ideal and the associated conduction loss was neglected. However, as explained in Section IV-A, in the transistor-level implementation, the switches are designed to balance between the gate-driving loss and the settling time requirement. This means that the resistances of the switches lead to incomplete setting, as the input current waveform (shown in blue) in Fig. 18 suggests. The incomplete settling of the switches leads to a higher output resistance of the converter ( in Fig. 3) and increases the charge redistribution loss, degrading the power efficiency. The efficiency of the converter is simulated in a similar way for multiple input voltages between 0.8 V and 2.4 V at full

Fig. 20. Simulated and theoretical efficiency of the converter.

load current. The efficiency results are presented in Fig. 20, exhibiting discrepancy of 5.5% to 13.2% between the theoretical and simulated values. Similar to the aforementioned case with , the discrepancy between calculated efficiency and simulated efficiency is due to switch resistance and incomplete settling. The peak efficiency occurs around because the gain setting at this input voltage is one. In this configuration only two switches are involved in charge transfer from the input to output, minimizing the and switching loss of the converter. V. CONCLUSION This paper described a custom closed-loop reconfigurable switched-capacitor converter for sub-mW applications. In the proposed topology, the series-parallel architecture is chosen because it can generate multiple step-up and step-down voltage gain ratios. The required number of gain settings and thus the number of flying capacitors are selected based on the output voltage regulation requirements. Using an averaged-switched model for the converter, the steady-state behavior, loss terms, and efficiency are formulated. The efficiency and regulation equations guided us to a practical control algorithm for the converter where the switching frequency is linearly dependent on the load current. This simplified control algorithm leads to a near optimal operation in terms of efficiency.

VAISBAND et al.: A CLOSED-LOOP RECONFIGURABLE SWITCHED-CAPACITOR DC-DC CONVERTER

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Inna Vaisband (S'12) received the B.Sc. degree in computer engineering and the M.Sc. degree in electrical engineering from the Technion-Israel Institute of Technology, Haifa, Israel, in 2006 and 2009, respectively. She is currently working toward the Ph.D. degree in electrical engineering from the University of Rochester, Rochester, NY, USA, under the supervision of Prof. E. G. Friedman. Between 2003 and 2009, she held a variety of software and hardware R&D positions at Tower Semiconductor Ltd., G-Connect Ltd., and IBM Ltd., all in Israel, and a Visiting Researcher Position at Stanford University, CA, USA, in 2012. Her current research interests include the analysis and design of high performance integrated circuits, analog design, and on-chip power delivery and management.

Mahmoud Saadat (S'09) received the B.Sc. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 2007, and the M.Sc. and degree in electrical engineering from Stanford University in 2009. He is currently pursuing his Ph.D. in electrical engineering at Stanford University, Stanford, CA, USA, in the field of power management integrated circuits for energy harvesting systems. From 2008 to 2012, he was with Intersil, Milpitas, CA, USA, and led the design of high efficiency DC-DC converter and white LED driver ICs for consumer electronics applications. He also held internship positions in power management groups at Qualcomm and Nest Labs prior to joining Stanford for his Ph.D.

Boris Murmann (S'99–M'03–SM'09) received the Dipl.-Ing. (FH) degree in communications engineering from Fachhochschule Dieburg, Dieburg, Germany, in 1994, the M.S. degree in electrical engineering from Santa Clara University, Santa Clara, CA, USA, in 1999, and the Ph.D. degree in electrical engineering from the University of California, Berkeley, CA, USA, in 2003. From 1994 to 1997, he was with Neutron Mikrolektronik GmbH, Hanau, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. Since 2004, he has been with the Department of Electrical Engineering, Stanford University, Stanford, CA, USA, where he currently serves as an Associate Professor. His research interests include the area of mixed-signal integrated-circuit design, with special emphasis on data converters and sensor interfaces. Dr. Murmann was a co-recipient of the Best Student Paper Award at the VLSI Circuits Symposium in 2008 and a recipient of the Best Invited Paper Award at the IEEE Custom Integrated Circuits Conference (CICC). In 2009, he received the Agilent Early Career Professor Award. He currently serves as an Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS, the Data Converter Subcommittee Chair of the IEEE International Solid-State Circuits Conference (ISSCC) and as a program committee member of the European Solid-State Circuits Conference (ESSCIRC). He is an elected AdCom member of the IEEE Solid-State Circuits Society.