A comparison between three proposed bridgeless Cuk rectifiers and ...

IEEE ICSET 2010 6-9 Dec 2010, Kandy, Sri Lanka

A Comparison between Three Proposed Bridgeless Cuk Rectifiers and Conventional Topology for Power Factor Correction 1

Abbas A. Fardoun1, Esam H. Ismail2, Ahmad J. Sabzali2, and Mustafa A. Al-Saffar2

2 Electrical Engineering Department Electrical Engineering Department University of United Arab Emirates College of Technological Studies P.O. Box 17555, Al-Ain, UAE P.O. Box 35007, Al-Shaab, Kuwait 36051 [email protected], [email protected], [email protected], [email protected]

Abstract – Three new bridgeless single phase ac-dc power factor correction (PFC) rectifiers based on Cuk topology are proposed. The absence of an input diode bridge and the presence of only two semiconductor switches in the current flowing path during each switching cycle result in less conduction losses and an improved thermal management compared to the conventional Cuk PFC converter. The proposed topologies are designed to work in discontinuous conduction mode (DCM) to achieve almost unity power factor and low total harmonic distortion (THD) of input current. The DCM operation gives additional advantages such as: zerocurrent turn-on in the power switches, zero-current turn-off in the output diode, and reduces the complexity of the control circuitry. Performance comparisons between the proposed and conventional Cuk PFC rectifiers are performed based on circuit simulation. Experimental results for a 150W/48Vdc at 100 Vrms line voltage to evaluate the performance of the proposed bridgeless PFC rectifier are provided. I.

Fig. 1. Conventional Cuk PFC rectifiers.

obtained as well as cost savings. Recently, several bridgeless PFC rectifiers have been introduced to improve the rectifier power density and/or reduced noise emissions via soft switching techniques or coupled magnetic topologies [1]-[4]. On the other hand, the bridgeless boost rectifier has the same major practical drawbacks as the conventional boost converter such as: the dc output voltage is higher than the peak input voltage, lack of galvanic isolation, and high startup in-rush currents. Therefore, for low-output voltage applications such as telecommunication or computer industry, an additional converter or an isolation transformer is required to step down the voltage. To overcome these drawbacks, several bridgeless topologies which are suitable for step-up/down applications have been recently introduced in [5]-[7]. However, the proposed topology in [5] still suffers from having three semiconductors in the current conduction path during each switching cycle. In [6], a bridgeless PFC rectifier based on Sepic topology is presented. However, similar to the boost converter, the Sepic converter has the disadvantage of discontinuous output current resulting in a relatively high output ripple. A bridgeless Buck PFC rectifier was recently proposed in [8] for step-down applications. However, in Buck PFC converter, the input line current cannot follow the input voltage around the zero crossings of the input line voltage. This, in turn, will result in an increased total harmonic distortion (THD) and a reduced power factor [9].

INTRODUCTION

Power supplies with active power factor correction (PFC) techniques are becoming necessary for many types of electronic equipment to meet harmonic regulations and standards, such as the IEC 61000-3-2. Most of the PFC rectifiers utilize boost converter at their front end. However, classical PFC scheme has lower efficiency due to significant losses in the diode bridge. Consider for example the conventional Cuk rectifier as shown in Fig. 1, the current flows through two rectifier bridge diodes and the power switch (Q) during the switch on-time, and through two rectifier bridge diodes and the output diode (Do) during the switch off-time. Thus, during each switching cycle the current flows through three power semiconductor switches. As a result, a significant conduction loss caused by the forward voltage drop across the bridge diode is generated and begins to degrade the converter performance, especially at low line input and high power applications. In an effort to maximize the power supply efficiency, considerable research efforts have been directed towards the development of efficient bridgeless PFC circuit topologies. A popular approach is to design PFC circuits where the number of semiconductors generating losses is reduced by essentially eliminating the full-bridge input diode rectifier (also known as a bridgeless PFC rectifier). A bridgeless PFC rectifier allows the current to flow through a minimum number of switching devices compared to the conventional PFC rectifier. Accordingly, the converter conduction losses can be significantly reduced and high efficiency can be

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II.

PROPOSED BRIDGELESS CUK PFC RECTIFIERS

This paper proposes three types of bridgeless Cuk PFC rectifiers with low conduction losses, as shown in Fig. 2. Similar to the Sepic converter, the Cuk converter offers several advantages in PFC applications, such as easy implementation of transformer isolation, natural protection against inrush current occurring at start-up or overload

1

2(a) and 2(c) show that one rail of the output voltage bus is always connected to the input ac line through the slowrecovery diodes Dp and Dn or directly as in the case of the topology of Fig. 2(b). Thus, the proposed topologies do not suffer from the high common-mode EMI noise emission problem and has common-mode EMI performance similar to conventional topologies. Consequently, the proposed topologies appear to be promising candidates for commercial PFC products. The proposed bridgeless rectifiers of Fig. 2 utilize two power switches (Q1 and Q2). However, the two power switches can be driven by the same control signal, which significantly simplifies the control circuitry. Compared to the conventional Cuk topology, the structure of the proposed topologies utilizes one additional inductor which is often described as a disadvantage in terms of size and cost. However, a better thermal performance can be achieved with the two inductors compared to a single inductor. In this connection it is worth mentioning that the three inductors in the proposed topologies can be coupled on the same magnetic core allowing considerable size and cost reduction. Additionally, the 'near zero-ripple-current' condition at the input or output port of the rectifier can be achieved without compromising performance. III.

PRINCIPLE OF OPERATION AND THEORETICAL ANALYSIS

A. Principle Of Operation Due to limited space, only the proposed bridgeless Type-3 Cuk rectifier of Fig. 2(c) will be considered in this study. The analysis assumes that the converter is operating at steady-state in addition to the following assumptions: a) pure sinusoidal input voltage, b) ideal lossless components, and c) all capacitors are large enough such that the voltage across them can be considered constant. Referring to Fig. 5(a), during the positive half-line cycle, the first dc-dc Cuk circuit, L1-Q1-C1-Lo1-Do1, is active through diode Dp, which connects the input ac source to the output. During the negative half-line cycle, Fig. 5(b), the second dc-dc Cuk

Fig. 2. Proposed bridgeless Cuk PFC rectifiers. (a) Type-1. (b) Type-2 (c) Type-3.

current, lower input current ripple, and less electromagnetic interference (EMI) associated with the DCM topology [10]. Moreover, unlike the Sepic converter, the Cuk converter has both continuous input and output current with low current ripple. Thus, for applications which require low ripple current at the input and output ports of the converter, the Cuk converter seems to be a potential candidate in the basic converter topologies. The proposed topologies in Fig. 2 are formed by connecting two dc-dc Cuk converters, one for each half-line period of the input voltage. It should be mentioned here that the topology of Fig. 2(a) was listed in [7] but not discussed in efficiency point of view. The operational circuits during the positive and negative half-line period for the proposed bridgeless Cuk rectifiers of Figs. 2(a), 2(b), and 2(c) are shown in Figs. 3, 4, and 5 respectively. Note that, by referring to Figs. 3, 4, and 5, there are one or two semiconductor(s) in the current flowing path; hence, the current stresses in the active and passive switches are further reduced, and the circuit efficiency is improved compared to the conventional Cuk rectifier. In the case of the conventional Cuk rectifier, the current stresses through the active and passive switches are high, which may result in high conduction and high switching losses. In addition, Fig.

Fig. 3. Equivalent circuits for the Type-1 rectifier. (a) During positive half-line period. (b) During negative half-line period of the input voltage.

2

several advantages can be gained. These advantages include: natural near-unity power factor, the power switches are turned-on at zero current, and the output diodes (Do1 and Do2) are turned-off at zero current. Thus, the loss due to the turn-on switching losses and the reverse recovery of the output diodes are considerably reduced. The average voltage across capacitor C1 during the positive half cycle can be expressed as,

  vac (t)  Vo vC1 (t)   V  o

0t

T 2

T tT 2

(1)

Similar to conventional Cuk converter, the circuit operation in DCM can be divided into three distinct operating stages during one switching period Ts. The circuit operation during a switching period Ts in a positive half-line period, Fig. 5(a), can be briefly described as follows: Stage 1[t0, t1], when switch Q1 is turned-on, diode Dp is forward biased by the inductor current iL1. As a result, diode Dn is reversed biased by the input voltage. The output diode Do1 is reversed biased by the reverse voltage (vac + Vo), while Do2 is reversed biased by the output voltage Vo. In this stage, the current through inductors L1 and Lo1 increase linearly with the input voltage, while the current through L2 is zero, because the voltage across C2 is constant. The inductor currents of L1 and Lo1 during this stage are given by, diLn vac (2)  n  1, o1 dt Ln


Accordingly, the active switch Q1 peak current can be determined and it is given by, V (3) IQ1,pk  m D1TS Le where Vm is the peak amplitude of the input voltage vac, D1 is the switch duty-cycle, Ts is the switching period, and Le is the parallel combination of inductors L1 and Lo1 Stage 2[t1, t2], This stage starts when the switch Q1 is turned-off, diode Do1 is turned-on simultaneously providing a path for inductor currents iL1 and iLo1. Diode Dp remains conducting to provide a path for iL1 and diode Do2 remains reverse-biased during this interval. This interval ends when iDo1 reaches zero and Do1 becomes reverse-biased. Note that diode Do1 is switched off at zero current. Similarly, the inductor currents of L1 and Lo1 during this stage can be represented as, V di Ln (4)  o n  1, o1 dt Le Stage 3[t2, t3], during this interval only diode Dp conducts to provide a path for iL1. Accordingly, the inductors in the circuit behave as current sources, which keep the currents constant. The capacitor C1 is being charged by the sum of the currents through L1 and Lo1. The period ends at the start of the next switching cycle. Fig. 6 shows theoretical DCM waveforms over one switching cycle during the positive half of the input voltage.


circuit, L2-Q2-C2-Lo2-Do2, is active through diode Dn, which connects the input ac source to the output. Thus, due to the symmetry of the circuit, it is sufficient to analyze the circuit during the positive half-period of the input voltage. Moreover, the operation of the proposed rectifiers of Fig. 2 will be described assuming that the three inductors are operating in DCM. By operating the rectifier in DCM,

3

Evaluating (6) by using (7) and applying the power balance between the input–output ports, the desired input-to-output voltage conversion ratio M is M

RL 2R e

Vo  Vm

(8)

where the quantity Re is defined as the emulated input resistance of the converter, and it is given by

Re 

2 Le D12 TS

(9)

It shall be noted that the voltage gain in (8) is also valid for the other two topologies. However, the effective inductance (Le) varies from one topology to another. C. Boundaries Between CCM and DCM Referring to the diode Do1 current waveform in Fig. 6, the DCM operation mode requires that the sum of the duty cycle and the normalized switch-off time length be less than one, i.e., (10) D2  1  D1 Substituting (5) into (10) and using (8) and (9), the following condition for DCM is obtained:

K e  K e crit 

Ke 

By applying inductor-volt second across L1 and L1o, the length of the period of the second stage can be expressed as, D (5) D 2  1 sin t M

TL /2

2 TL

TL /2

 0

v ac (t) i ac (t)

TS

dt

(11)

2

2 Le

(12)

R L TS

It is clear from (11) that the value of Ke-crit depends on the line angle (ωt). Hence, the minimum and maximum values of Ke-crit is

where  is the line angular frequency, and M is the voltage conversion ratio (M = Vo / Vm). Since diode Dp continuously conducts throughout the entire switching period, the voltage across C2 is clamped by the output voltage Vo. It also shall be noted that during the positive half of the input voltage, the body diode of switch Q2 is also turned on. As a result, the current through inductor L2 slowly increases. This slow increase of the current can be neglected over a switching cycle; hence, the voltage across L2 can be considered to be zero over a switching cycle. B. Voltage Conversion Ratio M The voltage conversion ratio M in terms of converter parameters can be obtained by applying power balance principle. The average input power can be expressed as, 

2  M  sin(t) 

where the dimensionless parameter Ke is defined as

Fig. 6. Theoretical DCM waveforms during one switching period Ts for the converter of Fig. 5(a).

Pin (t)

1

K ecrit min 

1 2  M  1

2

and K ecrit  max 

1 2 M2

(13)

respectively. Therefore, for values of Ke < Ke_crit_min, the converter always operates in DCM, and it operates in CCM for values of Ke > Ke_crit_max. However, for values of Ke_crit_min < Ke < Ke_crit_max, the converter operates in both modes: CCM near the peak value of the input line voltage, and DCM near the zero crossing of the input line voltage. IV.

COMPARISON STUDY BETWEEN THE PROPOSED AND CONVENTIONAL CUK CONVERTERS

The proposed topologies are compared with respect to their component count, efficiency, driver circuitry complexity, total harmonic distortion (THD) and voltage gain range. To ensure a fair comparison, the inductance values in all topologies are selected such that Ke = 0.9 Kcrit at an operating point of output power of 300W. Moreover, an equivalent series resistor (ESR) of 20 m and 12 mΩ is placed in series with all the inductors and capacitors, respectively. Furthermore, Pspice actual semiconductor models have been used to simulate the switches. Table I shows the details of the components used in the simulation. The simulated efficiency presented in Fig. 7, includes conduction and switching losses of the semiconductor

(6)

where the notation <  > T represents the average value over the interval T. Note that the input current in the positive half of the line cycle is the same as the inductor current L1. From Fig. 6, it can be shown that the average input current in one switching cycle is given by v (t) (7) i ac (t) T  i L1 (t) T  ac D12 TS S S 2 Le

4

97 96

% Efficiency

2

Type 3 rectifier Type 1 rectifier Conv. Cuk rectifier

1.5

95 94

1

93

% THD

devices, inductors’ copper losses, capacitor ESR losses, as well as gate drive losses. Table II presents a comparison between topologies of interest. It shall be noted that Type-2 has the lowest number of semiconductors in the current conduction path. However, it has disadvantages of floating switch and a step-up voltage gain greater than 2. The floating switch requires a more complex driver circuitry and typically causes higher electromagnetic emissions. The gain range is limited by the blocking voltage of Do2 during the positive half of the input line signal similar to the topology discussed in [6]. This disadvantage can be minimized by implementing input/output galvanic isolation; however, components with higher blocking voltage capability are needed. Type-1 also has the advantage of a lower component count, but a higher current peak. Whereas, Type3 has higher component count, but lower stresses. In conclusion, the converter of choice is application dependent. It is evident from Fig. 7 that the efficiency of Type-3 topology is higher than that of the conventional PFC Cuk rectifier for the provided output power levels. It should be mentioned here that the discrepancies in efficiencies between Type-3 and conventional Cuk PFC rectifiers becomes more pronounced as the power level increases. In this case, it is preferred to operate the converter in the continuous conduction mode (CCM) region instead of DCM. Fig. 7 also shows input current THD as a function of output power. It is evident from Fig. 7 that both the proposed and the conventional Cuk rectifier exhibit extremely low THD (< 1% for Pout > 100 W) when they are designed to operate in DCM. Note that, by referring to Fig. 7, the THD of the converters under study become independent of the output power for power level greater than 100 W.

0.5 92

vac = 120 Vrms, Vo = 48 V, fs = 50 kHz

91 0

50

100

150

200

0

250

300

Output Power [W] Fig. 7. Simulated efficiency (solid lines) and THD (dashed lines) of conventional PFC Cuk, Type-1, and Type-3 rectifiers operating in DCM. TABLE I COMPONENTS USED IN SIMULATION Input inductor(s) L1 and L2

1 mH

Output inductor(s) Lo1 and Lo2

22 H

Energy transfer capacitor(s) C1 and C2

1 F 12000 F

Filter capacitors Co Active switch(es) Q1 and Q2

IRFB4332PBF: 250 V, 60 A with RDS-ON = 29 m

Output diodes Do1 and Do2

STTH1003SB: 300 V, 10 A, with VF = 0.9 V STTH2R02Q: 200 V, 2 A, with VF = 0.7 V

Input diodes Dp and Dn

TABLE II COMPARISON BETWEEN CONVENTIONAL AND BRIDGELESS CUK RECTIFIERS IN DCM MODE Item

V. SIMULATION AND EXPERIMENTAL RESULTS The Type-3 converter of Fig. 2(c) has been simulated using PSPICE for the following input and output data specifications: vac = 100 Vrms, Vo = 48 V, Pout = 150 W, and fs = 50 kHz. The circuit components used in simulation are the same as those in Table I. Fig. 8 shows the simulated voltage and current waveforms at full load condition. It can be observed from Fig. 8(a) that the input line current is in phase with the input voltage. Fig. 8(b) shows the current through the slow diodes Dp and Dn. Fig. 8(c) shows the inductors’ currents waveforms over one-line period. Whereas, the switching waveforms of the inductors’ currents at peak input voltage are illustrated in Fig. 8(d), which correctly demonstrate the DCM operating mode. The active switches current and the intermediate capacitors voltages waveforms are depicted in Fig. 8(e) and 8(f), respectively. A prototype of Type-3 converter has been built to validate the theoretical results, as well as the simulation previously described. The circuit parameters were all the same as those for simulation. The input voltage and current are shown in Fig. 9(a). Fig. 9(b) presents the currents through diodes Dp and Dn. It shall be noted that the current through Dp goes to zero before the end of the positive cycle

Diode Switch Current conduction path when SW on

Conv. Cuk

4 slow + 1 fast 2 slow + 3 fast

Peak switch current

5

Type-2

Type-3

2 fast

2 slow + 2 fast

1

2

2

2

2 slow diodes and 1 switch

1 slow diode, and 1 switch with series diode

1 body diode and 1 switch

1 slow diode and 1 switch

2 diodes (1 slow and 1 fast)

1 fast diode

2 diodes (1 slow and 1 fast)

1 slow diode

____

1 slow diode

Current conduction 3 diodes (2 slow and 1 fast) path when SW off Current conduction path in DCM

Type-1

2 slow diodes

8 / Ke Le  L1 / /Lo

8 / Ke

8 / ke

Le  L1 / /L 2 / /Lo Le  L1 / /L

8 / Ke Le  L1 / /Lo1

Component count

10

11

11

13

Gain range

Step-up/down

Step-up/down

Only step-up

Step-up/down

Integrated magnetic

One core for 2 One core for 3 One core inductors inductors for 3 inductors

Driver circuit complexity

1 non-floating

2 non-floating 1 floating + 1 nonfloating

2 cores for 4 inductors 2 non-floating

of the line. This occurs because the body diode of Q2 provides an additional path to the current. Fig. 9(c) illustrates switching waveforms of the inductors’ currents near peak input voltage. Finally, Fig. 9(d) shows the voltage across capacitor vC1 and vC2. A very good agreement can be seen between simulation and experimental results. The measured efficiency is about 93.2% at full rated load. CONCLUSION

VI.

(b)

Three single-phase ac-dc bridgeless rectifiers based on Cuk topology are presented and discussed in this paper. The validity and performance of the proposed topologies are verified by simulation and experimental results. Due to the lower conduction and switching losses, the proposed topologies can further improve the conversion efficiency when compared with the conventional Cuk PFC rectifier. Namely, to maintain the same efficiency, the proposed circuits can operate with a higher switching frequency. Thus, additional reduction in the size of PFC inductor and EMI filter could be achieved. The proposed bridgeless topologies can improve the efficiency by approximately 1.4% compared to the conventional PFC Cuk rectifier. The performance of one of the proposed topologies was verified on a 150-W experimental prototype. The measured efficiency and THD of the converter at 100 Vrms line and full-load are approximately 93.2% and 1.2%, respectively. Experimental results are observed to be in good agreement with simulation results.

(c)

ACKNOWLEDGMENT

[Volt], [Ampere]

This work was supported in part by the United Arab Emirates University Research Affairs under Research Grant Contract # 1568-07-01-10, 2009-2010. 10

4

-10 475

iac 480

-4 505 475

500

4A

0A

0A

iLo1/15

iLo2/15

(c)

time [ms]

[Volt], [Ampere]

490

500

490

-3A 485

iL1

iLo1/15

iLo2

485.04

485.06

vC1

2 vac

Y. Jang and M. Jovanovic, “A Bridgeless PFC Boost Rectifier with Optimized magnetic Utilization,” IEEE Trans. on Power Electron., vol. 24, no. 1, pp. 85-93, Jan. 2009.

[4]

L. Huber, Y. Jang and M. Jovanovic, “Performance Evaluation of Bridgless PFC Boost Rectifiers,” IEEE Trans. on Power Electron., vol. 23, no. 3, pp. 1381-1390, May 2008.

[5]

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[6]

E. H. Ismail, “Bridgeless SEPIC Rectifier With Unity Power Factor and Reduced Conduction Losses,” IEEE Trans. on Ind. Electron., vol. 56, no. 4, pp. 1147-1157 April 2009.

[7]

A. Sabzali, E. H. Ismail, M. Al-Saffar and A. Fardoun, “A New Bidgless PFC Sepic and Cuk Rectifiers With low Conduction and Switching Losses,” 8th International Conference on Power Electronics & Drives Systems, PEDS 2009, November 2009, pp550556.

[8]

Y. Jang and M. M. Jovanović, “Bridgeless Buck PFC Rectifier,” in Proc. IEEE Applied Power Electronics Conf., 2010, pp. 23-29.

[9]

J. M. Alonso, M. A. Dalla Costa, and C. Ordizl, “Integrated BuckFlyback Converter as a High-Power-Factor Off-Line Power Supply,” IEEE Trans. on Ind. Electron., vol. 55, no. 3, pp. 1090-110, March 2008.

vC2

iQ2 490

time [ms]

(e)

[3]

0V

iQ1 480

G. Moschopoulos and P. Kain, “A Novel Single-Phase Soft-Switched Rectifier With Unity power Factor and Minimal Component Count,” IEEE Trans. on Ind. Electron., vol. 51, no. 3, pp. 566-575, June 2004.

time [ms]

300V

0

[2]

505

iL2 485.02

vac/4

-40 475

500

time [ms]

(d)

40

W. Choi, J. Kwon, E. kim J. Lee and B. Kwon, “Bridgeless Boost Rectifier with Low Conduction Losses and Reduced Diode ReverseRecovery Problems,” IEEE Trans. on Ind. Electron., vol. 54, no. 2, pp. 769-780, April 2007.

3A

iL2

-4A 480

480

(b)

iL1

[1] iDn

iDp 490

(a)

REFERENCES

0

time [ms]

Fig. 9. Experimental waveforms for the converter of Fig. 2(c) in DCM. (vac = 100 Vrms, Vo = 48 V, Pout = 150 W)

vac/50

vac/20 0

(d)

500

-300V 475 505

(f)

480

490

500

505

time [ms]

Fig. 8 Simulated waveforms for Type-3 rectifier of Fig. 2(c) in DCM. (vac = 100 Vrms, Vo = 48 V, Pout = 150 W)

[10] M. Brkovic and S. Cuk, “Input current shaper using Cuk converter,” in Proc. Int. Telecom. Energy Conf., 1992, pp. 532–539.

(a)

6