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Abstract - In this paper we present a vision of the sequence of three embedded systems design courses being taught for computer engineering technology ...
A Comprehensive Embedded Systems Design Course and Laboratory Antonio F Mondragon-Torres and Jeanne W Christman Department of Electrical Computer and Telecommunications Engineering Technology Rochester Institute of Technology Rochester, NY, USA [email protected]. [email protected] Abstract - In this paper we present a vision of the sequence of three embedded systems design courses being taught for computer engineering technology students. The focus of these courses is to prepare strong students in both digital hardware design as well as embedded software design. The courses have been evolving from traditional delivery of the content to a highly interactive hands-on industry-like experience where students are allowed to balance tradeoffs between hardware and software, and to design from idea to final implementation. The sequence progresses around examples of everyday objects as simple as an electric toothbrush, to smartphones and tablets, to airplanes and military devices. Being so pervasive, emerging embedded applications are used as examples and students are asked to explore further to find what skills, hardware and software, are required to build these applications. In the present review, a glimpse of the core ideas around these three courses and how can they be implemented to engage students in this vast field is given. Keywords-Component; Embedded Systems; FPGA; HDL; Agile; Capstone Course;Senior Design.

I.

INTRODUCTION

Embedded Systems education is a very challenging task as it includes electronics, logic circuits, computer design, software engineering, high level and assembly language and more. However, as embedded systems are now part of almost every product used in our daily lives, the need for competent embedded systems designers is growing. The breadth of embedded systems applications allows students to find their niche within the field. Internet connected applications, mechatronics, healthcare, and gaming are just a few of the areas where an embedded engineer can work. Preparing students to design the next generation of consumer and industrial applications is the focus of a three course capstone sequence in Embedded Systems Design (ESD) required for the Computer Engineering Technology (CpET) degree offered by the Electrical, Computer and Telecommunications Engineering Technology Department at the Rochester Institute of Technology (RIT). This unique degree bridges the gap between Computer Science and Electrical Engineering Technology (EET). Students in this program start with a solid foundation in EET, taking all of the circuits, electronics and hardware design courses. They also take high-level and assembly language programming as well as elective courses from RIT’s Computer Science department. Their education concludes with a three course ESD Sequence. Graduates

from this program have an in-depth knowledge not just of hardware (HW) and software (SW) design, but also on co-design. Similar to students in most university CpET departments, RIT’s students take required courses in embedded microcontroller programming and also in HW development using a Hardware Description Language (HDL) targeted for a Field Programmable Gate Array (FPGA) during their first three years. With the knowledge gained from those courses as a basis, the ESD classes provide an intensive laboratory and project based learning experience where students are able to approach system design from both the HW and SW perspective. While traditional lectures are occasionally employed to introduce concepts and theories, the emphasis is placed on hands-on learning. II.

EMBEDDED SYSTEMS DESIGN I

ESD-I is structured as a computer organization course. The approach is to cover more deeply the topics introduced in previous microcontroller, digital design and HDL courses as well as to introduce more advanced concepts. In this course, the design and customization of microcontroller systems is targeted. The advantages and disadvantages of soft-core vs. hard-core processors have previously been debated [1] and in this course students are exposed to both. Following a traditional computer organization outline, the course covers the basic structure of computers, instruction set architecture (ISA), basic input/output, software, pipelining, input/output organization and memory subsystems. The basic processing unit topic is covered in depth in the first laboratory by tasking the students to design their own processor in a HDL. The students are provided with specifications on the datapath and control units, and a very limited ISA. To test the HW processor just designed, students are asked to program in assembly language, manually translate the code into machine language and run it both in simulation and on the actual FPGA board. Spanning two weeks, the main objective of this laboratory is to allow students to recall digital design concepts and understand concepts on microcontrollers that were not covered by the prerequisite courses and will be the base of the course. The next laboratories are based on: instantiating a soft-core reduced instruction set computer (RISC) (Altera Nios-II), SW programming in both assembly and C language, interfacing HW components using an HDL language, polling and interrupts, instantiation and accessing embedded memory, bus

interfacing, communications, and arbitration, and platform serial asynchronous and synchronous communications. What is novel in this course is that at the same time the students are learning the required concepts, a series of team homework assignments are introduced that build upon those concepts and culminate with a group level activity. This activity, known as a plug-fest, is commonly used in industry for different manufacturers get together to test compatibility to a known standard. During this activity, students must successfully interface their platform to other teams’ platforms by following a protocol created specifically for the course. The homework assignments that lead to the final serial communications laboratory exercise make use of NXP’s mbed rapid prototyping microcontroller. This platform has strong community support, an online compiler, is very easy to interface on a breadboard, has high performance and can be programmed in standard C/C++. In completing the team homework assignments, students are introduced to real applications by covering concepts at a high level of abstraction. Topics such as LCD control, pulse width modulation, servo motor control, RS-232 asynchronous serial communications, basic cryptography, ultrasonic sensors, and inter-integrated circuit (I2C) synchronous serial communications are investigated. Building on all of the above skills, the students create a sonar-like application that detects intruders, displays the angle and position at where they were detected, gives a bar-graph representation of the proximity, stops the scanning process, and sounds an alert. The final laboratory is for students to be able to follow a protocol to enable communication between the soft-core FPGA platform that they have been working on individually in laboratory exercises and the mbed. Students are given a description of the protocol and their responsibility is to separately code a Master/Slave system using both platforms. Each team designs one master and one slave platform that communicate with each other. Once the individual teams have platforms that can communicate, they then have to demonstrate that they are also capable of communicating with other platforms utilizing the same protocol. This is achieved at the aforementioned plug-fest. For each successful connection, the team members receive an extra point and for each peripheral controlled on a slave device (e.g. I2C, ultrasonic sensor, servo) they receive additional points. Success rates were higher than 80% as students are engaged in this activity and are driven to succeed. Even though the course has a moderate to high load with traditional assignments, the extra team projects are well received and boost the morale of the class. The experience of working together as a whole group to accomplish a single outcome in which everybody participates, exchanges their ideas and gets bonus points, is both motivating and rewarding for the students. III.

EMBEDDED SYSTEMS DESIGN II

The focus of Embedded Systems Design II is the development of custom Intellectual Property (IP) blocks

to interface with a variety of peripherals and the creation of custom instructions for hardware acceleration. As this course is intensive in hardware development, only one platform, the Altera DE2 board, is utilized. The instructional methodology for this class is primarily a studio environment wherein each student is seated at a workstation with their own development board, allowing for immediate implementation of concepts. The first concept for system improvement that is investigated is Direct Memory Access (DMA). Even though DMA IP cores are readily available, students write their own in Hardware Description Language. There are many reasons to have students create their own IP cores despite the fact that the internet provides them with an unlimited supply of cores created by other designers. First, in the interest of training well-rounded embedded systems design engineers, a balanced approach has to be taken to provide students with both hardware and software development skills. Some students may choose to become hardware development engineers. Those who want to focus on embedded software still need to understand the hardware development process as well as do more with the hardware than just instantiate provided cores into the system. Students may have to someday modify or customize off-the-shelf components for their own system to improve performance and/or reduce resource utilization. Finally, in this day and age of unlimited information available on the internet, students need constant reminding that, just because it’s available, does not mean it is correct. Students are encouraged to create their own library of cores from this course to be reused in the subsequent class or in their own projects. In the DMA exercise, students create a DMA controller optimized to transfer data between two specific memory devices in their system. The DMA is placed on the processor bus and controls it for a burst transfer. Students then measure the amount of time necessary to transfer different amounts of data through the processor and then through the DMA. Hardware acceleration is another system performance improvement topic covered in depth in this course. The final exercise in the hardware acceleration unit, image rotation, has been previously described in [2]. In this experiment, students create one hardware module that uses the CORDIC algorithm to calculate sine and cosine and another hardware module to implement the image rotation calculations. In the software program handling the rotation, operations are offloaded to these two accelerators and execution time is measured. The same software program is run with all calculations being performed in the processor. Measurements are taken to quantify the performance improvement, but in this case, there is such a marked improvement by using hardware, one can verify it visually. Students find this exercise to be beneficial to their understanding of concurrent operation in hardware versus sequential operation in software.

They also appreciate that, by using the hardcore multipliers on the FPGA, a ten-fold performance improvement can be realized without a significant increase in hardware used. To provide vertical integration with the ESD I course, students create a pulse width modulator/servo motor controller and an I2C controller in hardware. These exercises provide them with the opportunity to design custom hardware to communicate with an external component and meet another component’s timing specifications. The servo motor controller exercise introduces custom component creation and off-board hardware control. These concepts are explored further with the creation of an I2C controller. This controller must perform a single-byte write, a single-byte read and a multi-byte read with an off-the-shelf accelerometer. Unlike lower level classes where pertinent data is taken from the component data sheet and provided to the students, in this exercise the students must analyze the data sheet to be able to create the controller and embedded software to direct their controller to read from and write to the accelerometer. In lieu of a laboratory report for the I2C controller, students write a data sheet/user guide for their core. This data sheet is saved with the core VHDL code and placed in the student’s library of components. In an integrating exercise, the two controller cores are implemented in one system so that the accelerometer can be used to control the servo motor. This is accomplished in the program code executing in the soft core processor. The accelerometer position is read in through the I2C controller, the atan() C function is used to calculate the angle and finally the angle is sent to the servo motor controller. As a further integration exercise, atan can be calculated using the CORDIC algorithm and implemented as a hardware accelerator. IV.

EMBEDDED SYSTEMS DESIGN III

The last course in this sequence is equivalent to a senior or capstone design course. A non-conventional approach is taken in which the students work as a team to create an innovative open-ended project targeted to a particular market segment or market need. The lecture portion of the course is dedicated to introducing the students to project management (PM), version control, good design methodologies, team collaboration, presentation skills, design reuse, innovation, entrepreneurship, and product ideation. The laboratory section is used for progress update meetings, retrospectives and to discuss possible design solutions. The following is a list of some of the characteristics of this capstone course realization Non-Conventional Approach: In the majority of senior capstone project courses, a traditional approach to PM and product development is taken, while in this course the teams are structured like small start-up companies whereby the students create an innovative

product that has differentiation to commercially available products and targets a specific market segment. Different outside companies have been invited to participate in the projects as “Product Owners” and help to specify, shape and collaborate during the development. Another unique aspect is IP reuse and collaboration across teams working on different projects. Lastly, Agile PM techniques are applied. Application of these techniques allows the students to experiment and mature their ideas and thus increases creativity and innovation. Innovation: Over the last few years, RIT has launched a university-wide effort towards innovation and entrepreneurship and has encouraged faculty to incorporate those themes into their coursework. In this course global competition and first to market constraints as well as product differentiation are discussed. Team Work: Students are encouraged to collaborate within and across teams. The only constraint imposed on is that all outside assistance be cited. Projects from all previous offerings of the class are made available for code and IP reutilization. In cases where students modify code or documentation done by previous teams, they must comment on the changes made and make both documentation and code available for future generations. Open Ended: The project goals are open ended, meaning that there is an initial vision of what the product will be, but the product is allowed to change direction at every “sprint” (equivalent to a “milestone” in traditional PM) based on feedback from the team and the product owners. At the end of each sprint, the product should be functional to a certain degree. This approach allows students the flexibility to redefine the design or correct if they have underestimated the scope of a task. Target Market: Since today’s market is very dynamic, those who come first with an innovation are likely to remain the leaders. Students are encouraged to think of a particular market that could benefit from their product instead of targeting it for the masses, which may be difficult to achieve. Part of the product definition phase is for students to find a particular problem to be solved and attack it in an innovative way. New Open Source Platform (OSP): Students benefit from working on open source platforms since these can be assimilated easily and they can start contributing to the development in a very natural and efficient form. If a company offers an OSP and allows global development, students can start participating immediately to its development and maturity. There are countless OSPs that are generating a tsunami in ESD e.g. Arduino, mbed and BeagleBoard communities. Industrial Experience: Some may disagree with the concept of open ended projects, arguing that it enables students to choose projects that are not very demanding. However, as students in this course are nearing graduation and actively pursuing full time employment, an emphasis on getting the best project achievable is given. Students

are encouraged to develop professional projects that can be used to promote themselves while looking for a job. In today’s job market, it is very important for students to be able to push their resume to the top of the pile, by proving to employers that they are capable of producing high quality, independent and focused products. One to One Interaction with Engineers: Another outcome of the course is improving students’ communication skills and their ability to express ideas clearly and concisely. While each project may be determined by the students’ initiative, it could also solve a particular problem proposed by the “Product Owner” which may be internal (professor) or external (engineer at a company). It is very important that students interact among themselves and, if possible, with external engineers. This provides opportunities for the students to learn how to communicate and express their technical ideas in an effective manner. Students are reminded that a company is a very dynamic environment and the engineers that are sponsoring their project are very busy and need to be presented with succinct information and clear requests. Over the evaluation period presented in this paper we have seen a continuous improvement in all three courses. There have been periods of disruption when a new faculty teaches a course or when there is a change in the software tools which is a normal process of any course. Fig. 1 presents a plot of student evaluation data for three survey questions 1) How much you learned 2) Motivation and 3) Overall rating of the course. It can be observed that all three are positive and increasing at a rate from 12% to 16% which is interpreted as a measure of student engagement. Winter 20122 shows a decay in motivation but one possible reason could be that 8 out of 10 students had already accepted jobs and were only taking the course as a requisite and not to get skills for job hunting. In Fig. 2 a boxplot of the statistical data is shown. What is interesting in this plot is that, in addition to the increasing trend in student’s engagement the spread can be observed. Motivation is the only measure that seems not to be consistent.

Fig. 2. ESD III student boxplot summary of statistical data

V.

CONCLUSIONS

We have presented a three course series that prepares students to ESD. The first course is tailored for a computer organization and embedded systems introduction. Team collaboration and an active learning process are fundamental to engaging students. The second course builds on the first one, but rather than using a high level of abstraction, the students learn the real effort it takes to implement some of the functions previously used and learn the importance of HW-SW partitioning by balancing the compromise between performance and flexibility. The third course leads to an open ended project where students are free to apply the knowledge obtained through the program by coming up with a unique idea and making it a reality under the rigor of deadlines and prioritizing the tasks that add value to their product. By looking at the student’s evaluation of instruction for ESD-III we are confident that the students are engaged in and learning from the project design experience. This experience prepares them for industry where it is required that engineers make things happen in the right amount of time due to global competition. In this fast-paced, internet society it is important to be the first to hit the market and maintain a competitive advantage with robust products that are being developed through an agile framework. We are now preparing the connected engineers that will make these products and services. REFERENCES

Fig. 1. ESD III student evaluation ranking.

[1]

A. F. Mondragon-Torres and J. Christman, "Hard Core vs. Soft Core: A Debate," in 2012 ASEE Annual Conference & Exposition, San Antonio, TX, 2012.

[2]

J. Christman and E. Alley, "A Hands-on Approach to Demonstrating Hardware/Software," in ASEE 2011 Annual Conference & Exposition, Vancouver, BC, 2011.

[3]

A. F. Mondragon-Torres, A. Kozitsky, C. Bundick, E. Mc Kenna Jr., E. Alley, M. Lloyd, P. Stanley, and R. Lane, "Work in Progress: An Agile Embedded Systems Capstone Course," presented at the 2011 Frontiers in Education, Rapid City, SD 2011.

[4]

A. F. Mondragon-Torres, T. Hawley, A. Lee, and R. Masicci, "Agile Embedded Systems Design Capstone Course: The MAVRK Experience," in Congreso Argentino de Systemas Embebidos (CASE) 2012, Buenos Aires, Argentina, 2012.