A Cost efficient LDPC decoder for DVB-S2 Van Ying, Dan Bo, Shuangqu Huang, Bo Xiang, Yun Chen * ,Xiaoyang Zeng *
Abstract - Based on the Min-Sum algorithm, this paper proposes an LDPC decoder integrating the TDMP schedule, which could achieve low complexity as well as good performance. The LDPC decoder is for DVB-S2, which includes 11 kinds of code rates with a block size of 64800. Based on SMIC 0.13/lm standard CMOS process, the LDPC decoder has an estimation area of 14mm2, a throughput of 135Mbps with a frequency of105MHz and maximum iteration number of30, which shows advantage over previous DVB-S2 LDPC decoders}. Index Terms schedule
LDPC coeds, DVB-S2, min-sum, TDMP
I. INTRODUCTION
LDPC codes are originally proposed by Gallager in his 1960 doctoral dissertation [1], and they were not used for many years because at that time the technology was not mature for their practical implementation. In the mid-1990's, LDPC codes were resurrected with the contribution of Mackay and Neal [2]. The remarkable error correction performance and low implementation complexity of LDPC codes led to their recent inclusion in broadcasting systems, such as next generation digital video broadcasting via satellite (DVB-S2) [3], and have been optional FEC techniques in networks, such as Wireless-LAN (802.11n) [4] and Wireless-MAN (IEEE 802.16e) [5], etc. LDPC are linear block codes defined by a sparse parity check matrix. The total number of ones in each row and column is ultra smaller in comparison with the total elements of all rows and columns. The parity check matrix can be viewed as a bipartite graph with two kinds of nodes: checknodes corresponding to the rows and variable-nodes corresponding to the columns of the parity check matrix, as shown in Fig 1.
1 This work was supported by the funding of the State Key Lab of ASIC & system under Grant No.MS20080202. Yan Ying is with the State Key Lab. of ASIC and System, Department of Microelectronics, Fudan University, shanghai, China (e-mail:
[email protected]). Dan Bao is with the State Key Lab. of ASIC and System, Department of Microelectronics, Fudan University, shanghai, China (e-mail:
[email protected]) Shuangqu Huang is with the State Key Lab. of ASIC and System, Department of Microelectronics, Fudan University, shanghai, China (e-mail:
[email protected]). Bo Xiang is with the State Key Lab. of ASIC and System, Department of Microelectronics, Fudan University, shanghai, China (e-mail:
[email protected]). Xiaoyang Zeng is with the State Key Lab. of ASIC and System, Department of Microelectronics, Fudan University, shanghai, China (e-mail:
[email protected]). Yun Chen is with the State Key Lab. of ASIC and System, Department of Microelectronics, Fudan University, shanghai, China (e-mail:
[email protected]).
978-1-4244-3870-9/09/$25.00 ©2009 IEEE
Variable nodes
Check nodes
Fig. 1. H (8,2,4) parity check matrix and Tanner graph
The Digital Video Broadcasting via Satellite, Second Generation (DVB-S2) protocol [3] has been developed and standardized as an evolution of the Digital Video Broadcasting via Satellite (DVB-S) for European satellite broadcasting by the European Telecommunications Standards Institute (ETSI). DVB-S2 retains the robust operational features of DVBS while introducing new features that promise to improve performance and efficiency of broadcast links, such as additional modulations, dynamic operating modes, and advanced Forward Error Correction (FEC) schemes. The DVB-S2 standard changes the FEC algorithm from CC (convolutional codes) and RS (Reed-Solomon) codes in the DVB system to LDPC(Low-density party-check) and BCH codes, and because of this change, the prominent performance stand near the Shannon limit from 0.7dB to 1.2 dB. In this paper, we present a DVB-S2 compliant LDPC decoder architecture which combines the TDMP schedule. This design improves usage of area and achieves good error correction performance and high throughput. The rest of the paper is organized as follows. Section II briefs the simplified LDPC decoding algorithms, i.e, the MinSum algorithm, which implements message update. Section III presents the TDMP schedule. Section N describes The LDPC architecture, while in Section V the numerical simulation and implementation results are analyzed. Finally, Section VI concludes the paper. II. MIN-SUM DECODING ALGORITHM
Before the algorithm description, there are some notations: I, is the channel LLR (logarithmic likelihood ratio) value and can be obtained depending on the channel (AWGN); Lvc(k) is the prior message sent by variable-node v to its connected check-node c in the kth time iteration; Rev(k) is the extrinsic information passed from check-node c to its connected variable-node v in the kth time iteration; N(c) is the set of variable-nodes connected to the checknode c; M(v) is the set of check-nodes connected to the variablenode v; "\"is the exclusion symbol; "sgn(x)"is the symbol of computing the sign of x; S,(k) is the posteriori probabilities of variable-node v in the 1007
kth time iteration; c,(k)is the sign of posteriori probabilities; 1] is the correction factor; The Min-Sum algorithm is an efficient decoding algorithm for LDPC codes; it can reduce memory occupation compared with other algorithm, so especially suitable for the DVB-S2 standard which has long LDPC block size. The decoding process is an iterative process. Decoding of LDPC codes goes iteratively by exchanging messages between the variable-nodes and check-nodes, to improve the reliability of the received bits. During each iteration, the check-nodes receive messages from variable-nodes and then pass the updated values back to the variable-nodes. Decoding process will stop if all the parity check equations are satisfied or the preset number of iteration has been reached. The final decision on a bit is taken at the end of the decoding process, by computing the sign of a posteriori probabilities. The decoding process consists of the following six steps: Step one: Initialization Initialize each variable-nodes v to the log-likelihood ratio of the corresponding received bit.
=t,
L~~)
(1)
Step two: extrinsic message updating
I1
= 1] x
R;':,)
neN(c)\v
sgn(L~:-l))x min IL~:-l)1
Step three: the prior message updating = ~ R(k) - R(k) + I
L(k) ~
~ meM(v)
(2)
neN(c)\v
~
mv
v
(3)
Step four: calculate the posteriori probabilities
=
S(k) v
J)(k) + I
~
L..J
.L'mv
v
(4)
meM(v)
Step five: get hard decision C(k) _
v
-
I {0
L(S(k))
