A Current-Induced Channel Organic Thin-Film Transistor - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 1, JANUARY 2016

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A Current-Induced Channel Organic Thin-Film Transistor A. Gangwar and B. Mazhari

Abstract— An organic thin-film transistor structure is proposed in which a channel is created through formation of an electric dipole layer at the semiconductor–insulator interface. The dipole is composed of mobile carriers, electrons, and holes and results from the modification of gate insulator to allow controlled amounts of gate current to flow in the ON-state. 2-D device simulations are used to show that the proposed structure offers the potential for obtaining significantly higher channel charge and current without requiring higher voltages. It is also shown that these advantages come while maintaining OFF -current and unity gain frequency comparable with conventional transistors. Index Terms— Electric dipole (ED), transistor (OTFT), unity gain frequency.

organic

thin-film

I. I NTRODUCTION

O

RGANIC thin-film transistors (OTFTs) are being developed for a wide range of innovative applications due to the potential advantages of low-cost fabrication using roll-toroll printing techniques on flexible substrates [1]. Among the characteristics of OTFT, a sufficiently large channel current at low-operating voltage is required to address many of the applications. Field-effect mobility in organic semiconductors is generally low and increases with channel charge [2] due to increased filling of interface states. As a result, in many OTFTs reported in the past, adequate mobility could only be attained at impractically large operating voltages because of the use of thick dielectric layers with low dielectric constant [1]–[3]. With improvement in these last two dielectric parameters, operating voltage has been significantly reduced in recent years [1], [4]–[9]. However, thin dielectric thickness is difficult if not impossible to obtain through mass printing techniques and alternative means for obtaining low-voltage operation are required. In a conventional field-effect transistor, for a constant gate voltage, a larger charge in the channel can only be induced by increasing the gate capacitance. For a constant Manuscript received February 18, 2015; revised October 20, 2015; accepted November 4, 2015. Date of publication December 7, 2015; date of current version December 24, 2015. The review of this paper was arranged by Editor D. J. Gundlach. A. Gangwar is with the Samtel Centre for Display Technologies, Electrical Engineering Department, IIT Kanpur, Kanpur 208016, India (e-mail: [email protected]). B. Mazhari is with the National Centre for Flexible Electronics, Electrical Engineering Department, IIT Kanpur, Kanpur 208016, India (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2015.2499384

dielectric constant, this requires the dielectric thickness to be scaled. As the dielectric thickness is reduced, the gate metal with negative charge gets progressively closer to the channel containing positively charged holes for a p-type transistor. In the limit, the separation between positive and negative charges becomes negligible resulting in an electric dipole (ED). Although extremely large gate capacitance and channel charge are obtained, the requirement of negligible insulator thickness makes realization of the concept impractical. However, transistors with nonzero dielectric thickness have been reported where the channel is still induced through creation of an ED layer composed of ions on one side and mobile charge carriers in the channel on the other side [7]–[9]. Although very high capacitance and low-voltage operation is obtained, the drawback of these devices is that the operating speed is very low since they require movement of ions to operate [7]–[9]. In this paper, we propose an alternative transistor design where the ED layer is induced using only electrons and holes thereby avoiding the limitations of slower switching speed. It is shown that under appropriate conditions, large channel charge can be obtained but the use of mobile carriers instead of ions results in recombination and gate current as well. The gate current, however, is inherent to the operation and source of the dipole, so that the proposed device is called a current-induced channel transistor (CICT) to contrast it with devices where channel is created through the field-effect principle. 2-D device simulations using ATLAS are used to illustrate the device operation and its performance. The rest of this paper is organized in three parts. Section II describes the basic principle of operation for the proposed transistor structure. In Section III, simulation results verifying the working of CICT and illustrating the effect of various parameters on its performance are discussed. Important conclusions are included in Section IV. II. CICT: BASIC P RINCIPLE Fig. 1(a) shows a schematic of a two-terminal MIS-like structure with a hole conducting active semiconductor layer hole transport layer (HTL) and gate insulator replaced by an electron transport layer (ETL). The active and ETL layers are chosen such that the mobility of holes in HTL (μ p H ) and electrons in ETL (μn E ) is much larger than the oppositely charged carriers, and large electron and hole barriers (E e and E p ) exist at their interface, as shown in Fig. 1(b). Furthermore, hole mobility in the active layer, which is HTL, is assumed to be much larger than electron mobility in the ETL layer. The gate metal is chosen such that electrons

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Fig. 1. (a) Two terminal CICC (current induced channel capacitor) structure. (b) Energy band diagram. (c) Various processes at organic/organic interface. (d) CICT structure.

can be efficiently injected into ETL and similarly the opposite electrode (source/drain) contact is chosen such that holes can be efficiently injected into the active layer. Upon the application of negative gate voltage, electrons are injected into the ETL and accumulate at the interface due to the existence of a large energy barrier. These electrons attract holes to the opposite side of the interface thereby creating an ED layer, as shown in Fig. 1(a). The electrons and holes continue to accumulate until the injected electron current is balanced by recombination at the interface and steady-state condition is reached. One approach for modeling recombination at an interface is through the use of the concept of recombination velocity. As an example, this approach has been used to model backflow of carriers from the organic semiconductor into the metal, and recombination velocity of the order of ∼1 cm/s is estimated for a carrier mobility of 10−5 cm2 V−1 s−1 [10]. However, it is difficult to extrapolate this approach to organic– organic interface due to the existence of large interfacial barriers, which prevents simple backflow of carriers. Recombination at organic–organic interface is mediated by several processes, including exciton/exciplex formation/dissociation and geminate/nongeminate recombination along with trapping and detrapping in the presence of traps [Fig. 1(c)] [11]–[13]. Crossing of interface by the charges and their subsequent recombination on the same molecule (exciton recombination) dominates for low energy barriers at the interface, while for high energy barriers, electrons from ETL and holes from HTL recombine directly without crossing the barrier (exciplex recombination) [11]. For the purpose of modeling and simulation, it is convenient to lump the effects of different processes into an effective carrier lifetime τr , experimental values of which have been measured for several material systems. By employing a material system with low interface recombination or high value of τr , very large accumulation of carriers at the interface can be created and the accumulated charge in the active layer can be used to realize a transistor, as shown in Fig. 1(d) [14]. The channel accumulation charge in CICT (Q ch,C ) can be related to the gate current density (Jg ) through the expression Q ch,C = c1 × Jg × τr + Q o

(1)

where c1 is a proportionality constant, and inclusion of current independent Q 0 term allows a more general expression for channel charge which is also valid for the case where gate current is zero and the charge is induced through the fieldeffect principle. When the first term in (1) is dominant and majority of the channel charge is induced through the gate current, the device is appropriately called a CICT. The ETL with electron accumulation at the two ends (the contact and the interface) resembles an electron-only single-layer organic semiconductor device in which current can be bulk transport (drift and diffusion) limited or interface recombination limited. For low carrier mobility and significant exciplex recombination, current is expected to be bulk limited and can be modeled through the well-known Mott–Gurney law for space charge limited current [15] (VGS − Vbi)2 9 (2) Jg ∼ = × ε s × μn E × 8 d3 where εs and d are the dielectric constant and the thickness of ETL, respectively. Vbi is the built-in voltage associated with the system due to differences in work functions of gate and source electrodes. It is assumed that the materials are chosen such that μn E is much smaller as compared with μ p H , so that the applied gate voltage drops primarily across ETL for p-channel transistor. Equations (1) and (2) can be used to relate channel charge to gate voltage in a CICT device εs Q ch,C ∝ (VGS − Vbi )2 × 3 × (μn E × τr ). (3) d Equation (3) shows that the crucial parameter that decides the magnitude of accumulated charge is the product μn E × τr . Although the proposed concept of a CICT is general and can be realized with any suitable material system, organic semiconductors are particularly attractive due to the availability of large number of organic semiconducting materials with highly asymmetric carrier mobilities, wide range of electron affinity, energy gaps, and absence of requirement of lattice matching due to their amorphous or polycrystalline nature. Although it is easy to obtain a higher mobility-lifetime product by simply choosing an ETL material with large mobility, this approach also results in large gate current making it unattractive. The alternative approach is to use a material system that offers high interface recombination lifetime. Although charge accumulation at organic–organic interface in OLEDs [16] has been reported but with very short effective carrier lifetimes in the range of few nanoseconds to hundreds of nanoseconds [12], [17]–[19]. Since OLEDs are designed to ensure very high recombination of carriers, these material systems are likely to be in general unsuitable for the present concept. However, in other material systems, much higher lifetimes have been reported. As an example, transient absorption spectroscopy of films of blend of MDMO-PPV with 1(3-methoxycarbonyl)propyl-1-phenyl-(6,6)-C61, MDMO-PPV with functionalised fullerene 1-(3-methoxycarbonyl)-propyl1-phenyl-(6,6)C61, and CuPc with perylene-3, 4, 9, 10tetracarboxylic dianhydride has indicated lifetimes in the range of 10 μs due to trapping and detrapping of carriers which made recombination diffusion limited [13], [20]–[22]. In the hostguest material system, ADT-TS-F/ADT-TES-CN, photocurrent

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decay measurements have shown photocurrent decay times in milliseconds range due to the trapping of electrons by the guest, enabling free movement of holes in the host [23]. These reports highlight that a wide range of effective carrier lifetimes are possible and for a p-channel transistor, the trapping of electrons in ETL near the interface can be effectively utilized to increase τr to a significantly high value suitable for realizing the CICT principle. III. R ESULTS AND D ISCUSSION To illustrate the concept of CICT and evaluate its performance relative to the conventional OTFT, two-terminal capacitors and three terminal transistor structures were simulated using organic device module of ATLAS 2-D device simulation package. This device simulator simultaneously solves the poison’s equation, carrier continuity equation, and drift-diffusion current equations to obtain device characteristics [24]. Silvaco allows different recombination models such as bimolecular or monomolecular to be included but they require electrons and holes to be present in the same location to recombine. It does not allow exciplex like recombination, where carriers may be located on two different material systems. In the presence of high energy barriers, Silvaco would predict very low recombination. To avoid this shortcoming and to provide more freedom in modeling interface recombination, a thin layer of 1 nm thickness was inserted between the ETL and the active layer such that lowest occupied molecular orbital (LUMO) and highest occupied molecular orbital (HOMO) are the same as that of ETL and active layer, respectively. This allows electrons from ETL to recombine with holes in HTL without crossing the energy barriers. In this thin interfacial layer, recombination was introduced with effective carrier lifetime of τr , whose value was varied. Electron and hole barriers at the HTL/ETL interface were taken as 0.8 eV by taking HOMO = 5 eV and LUMO = 2.9 eV for active layer and HOMO = 5.8 and LUMO = 3.7 eV for ETL and kept constant until specified. These energy values represent typical organic materials such as HTL material pentacene (HOMO = 5 eV and LUMO = 2.9 eV) [25] and ETL materials such as buckminsterfullerene (C60: HOMO = 6.2 eV and LUMO = 4.5 eV) [26] or α, ω-disubstituted-quaterthiophenes with perfluorohexyl (DFH-4T: HOMO = 6.2 eV and LUMO = 3.3 eV) [27], or N,N -Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C8: HOMO = 6.3 eV and LUMO = 4.3 eV) [28], and N,N0-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13: HOMO = 5.4 eV and LUMO = 3.4 eV) [29]. A multiple-trap-release model for mobility is implemented by using an exponentially distributed interface trap density at the semiconductor/insulator interface [24], [30] given by the expression EV − E HD exp (4) gd (E) = k · TCD k · TCD where gd (E) is the donorlike valence band density of state of trap, E is the energy of trap, and E V is the energy corresponding to the valence band. Effective hole mobility in the linear region (VSD = 0.1 V) varied from 0.4 cm2 V−1 s−1

Fig. 2. I –V characteristics of CICC for μn E and 10−8 cm2 V−1 s−1 for τr = 1, 10, and 100 μs.

=

10−4 , 10−6 ,

Fig. 3. (a) Variation of gate current (IG ) in CICC with ETL thickness, d. (b) Variation of channel charge (Q C H,C ) in CICC with ETL thickness, d. (c) Ratio of charge concentrations in CICC (Q C H,C ) and OFEC (Q C H,O ) with gate current, IG for τr = 1, 10, and 100 μs. (d) Ratio of Q CH,C and Q CH,O with μn E × τr .

at VSG = 2 V to 0.65 cm2 V−1 s−1 at VSG = 5 V for H D = 1012 cm−2 and TCD = 1000 K. A. Two-Terminal Capacitor Characteristics Two-terminal current-induced channel capacitor (CICC) and a conventional organic metal–insulator capacitor were simulated with active and ETL/insulator layer thicknesses of 100 and 150 nm, respectively. Gate current in CICC is important since it is the source of channel charge. In order to study gate current and validate use of (2), simulations were carried out for different μn E and variable τr spanning orders of magnitude. Fig. 2 shows that for voltages larger than built-in voltage, the gate current is insensitive to lifetime, and variation of current with voltage is close to quadratic as suggested by (2). Fig. 3(a) shows that the dependence of current on the inverse of ETL thickness also follows (2) for CICC. Since channel is created due to current rather than voltage, the dependence of channel charge on ETL thickness (d) is expected to be different from the linear dependence on inverse of insulator thickness exhibited by conventional organic fieldeffect capacitors as predicted by (3). Fig. 3(b) shows the simulation results for two different μn E values keeping τr = 10 μs and d varied from 50 to 250 nm for V A = 5 V. For low μn E , current is very small and the behavior of CICC is similar to that of organic field-effect capacitor due to the dominance of Q 0 . However, for the case where CIC effect is

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Fig. 4. Output and transfer characteristics μn E = 10−4 cm2 V−1 s−1 for τr = 1, 10, and 100 μs.


of

CICT

for

strong, the dependence is markedly different. A linear fit to the simulated characteristics on the double log plot indicates variation as 1/d2.7 , which is close to 3 predicted by simple Mott–Gurney law (3). A significantly higher dependence on the inverse of insulator or ETL thickness can be taken as an indicator of the presence of the CIC effect. These results also suggest that the CICT structure would benefit more from the scaling of dielectric thickness as compared with the conventional TFT. The variation of accumulation layer charge (normalized by channel charge in an MIS device) with gate current (IG ) is shown in Fig. 3(c) for a constant gate voltage of 5 V. Different values of gate current were obtained by varying the electron mobility in ETL layer. It can be seen that for very low gate current, charge is constant and results from field-effect principle but becomes linear with current when it attains significant values as predicted by (1). Fig. 3(d) shows the charge curves obtained for different mobilities and lifetimes overlap when plotted against mobility–lifetime product as described by (3). Fig. 3(d) provides a guideline for choosing suitable materials for implementing the proposed CIC device (capacitor/transistor). As an example, to obtain an enhancement in channel charge by one order, a μn E× τr of 10−10 (cm2 V−1 ) is required. Assuming μn E of 10−5 cm2 V−1 s−1 (which is easily realizable in organic systems), the requirement for recombination lifetime is τr = 10 μs. B. Basic Transistor Characteristics The performance of transistors was evaluated by simulating transistors with a channel length of 10 μm, keeping all the parameters same as Section III-A. A much higher drain current can be obtained with CICT (Figs. 4 and 5) as compared with the conventional OTFT (12 μA/mm at VSD = VSG = 5 V). Fig. 4 shows the output and transfer characteristics of CICT for μn E = 10−4 cm2 V−1 s−1 and τr = 1, 10, and 100 μs. All devices exhibit well saturated transistor characteristics and the magnitude of current is higher in devices with higher τr consistent with (3). Low values of τr result in high recombination at the interface and significant gate current which cause distortion in characteristics at lower drain voltages. It is important to note

Fig. 5. Output and transfer characteristics of CICT for μn E = 10−3 , 10−4 , and 10−5 cm2 V−1 s−1 for τr = 10 μs.

Fig. 6. (a) IG of CICT as a function of μn E for different values of τr . (b) Ratio of drain to gate current (current gain) of CICT as a function of μn E for different values of τr .

that the gate current flows only when the HTL/ETL junction is forward biased, and thus, the characteristics in saturation mode remain unaffected since drain–gate junction is reverse biased. Fig. 5 shows the impact of ETL mobility on the output and transfer characteristics of CICT for τr = 10 μs. A reduction in μn E reduces gate current which leads to less charge accumulation and channel current. As μn E decreases, the CICT characteristics approach that of the conventional TFT due to the dominance of Q 0 given in (3). Gate current, which is the driver for CICT, increases with the increase in ETL mobility but is independent of τr [Fig. 6(a)]. Current gain, defined as the ratio of drain and gate current, is shown for different values of μn E and τr in Fig. 6(b). A smaller μn E and larger τr are required to obtain a higher current gain. For a current gain of 30 or more with a material system having a charge carrier lifetime of 10 μs, the electron mobility in ETL of 10−5 cm2 V−1 s−1 or less is required. It should be noted here that mobility in organic materials can be varied by orders of magnitude by changing the deposition conditions [31]. As pointed out earlier, even though there is gate current, the drain current remains unaffected when drain voltage is equal or larger than the applied gate voltage. As a result, OFF -current is unaffected by the gate current and ON – OFF current ratio remains large. The presence of significant energy barrier at HTL/ETL interface is an essential requirement for the operation of CICT. Interface dominates bulk processes for high energy barriers, and hence, μn E and τr govern the magnitude of channel accumulation charge. For low energy barriers at the interface,

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Fig. 7. Frequency responses of CICT (μn E = 10−4 cm2 V−1 s−1 and τr = 10 μs) and conventional OTFT.

bulk recombination dominates [11] leading to reduction in the output current from 700 to 457 μA/mm when hole energy barrier is reduced from 0.4 to 0.2 eV. C. Frequency and Transient Response There are several ways of evaluating the frequency response of a transistor, the simplest of which is the unity gain frequency. Fig. 7 compares this parameter for a CICT device with that of a conventional TFT with identical parameters. Both devices show comparable unity gain frequencies since in both cases, it is limited by channel transit time, τ p = L 2 /(μ p H × VSD ). In a CICT structure, in addition to hole transit time in the channel, there is an additional electron transit time, 2 /(μ τn = dETL n E × VSG ), that needs to be considered as well. Assuming that the entire gate voltage drops in ETL (since its mobility is much smaller) and VGS = VDS , the ratio of the two transit times is given by the expression τ p (channel) L2 μn E = 2 × . τn (ETL) dETL μ p H

(5)

For frequency response to be not limited by ETL transit time, the necessary condition is (μ p H /μn E ) (L 2 /d 2 ). Unity gain frequency is a small signal parameter measured under sinusoidal excitation and is more relevant for analog applications. For digital circuits, the static and transient response of a digital inverter is more meaningful. Fig. 8(a) shows a simple digital inverter with resistive load [32] which was simulated. However, the simulation of circuit simultaneously with device simulation is computationally very intensive and failed to converge with interface defects. The results reported are thus for a constant channel mobility of μ p H = 0.5 cm2 V−1 s−1 used for both OTFT and CICT without any defects. Circuit simulation with a compact model for a transistor [33]–[35] is a preferred approach but this is beyond the current scope of this paper. For the CICT, μn E = 10−4 cm2 V−1 s−1 and τr = 10 μs was assumed and rest of the parameters were the same for both devices, as described in Section III-A. Both transistors are assumed to have a gate width of 1 mm and a supply voltage of 5 V was taken. For the conventional OTFT, a load resistor of 1.85 M yielded a voltage transfer characteristic [Fig. 8(b)] with an inverter threshold voltage of 2.5 V, and maximum voltage gain of around 3.1. High and low noise margins are 0.15 and 1.69 V, respectively. For the CICT device, inverter transfer characteristics with a threshold voltage of 2.5 V and high and low noise margins of 0.4 and 1.59 V, respectively, were obtained using a smaller load resistance of 70 k due to higher channel current [Fig. 8(b)].

Fig. 8. (a) Digital inverter circuit. (b) Transfer characteristics of inverters designed with CICT and conventional OTFT. (c) Propagation delays of inverters for different load capacitors. (d) Output of five-stage ring oscillator made by inverters designed with CICT (μn E = 10−4 cm2 V−1 s−1 and τr = 10 μs), CICT (μn E = 10−4 cm2 V−1 s−1 and τr = 50 μs), and μ p H = 0.5 cm2 V−1 s−1 .

Fig. 8(c) compares propagation delays, high to low (τPHL ) and low to high (τPLH ) [32], for the inverters designed with conventional OTFT and CICT loaded at the output with different load capacitors (C L ). Consider first the intrinsic delays where capacitive load is either zero or low. In this case, low-to-high delays are comparable, while for high-tolow transition, inverter with CICT has higher delay compared with the conventional OTFT. The reason for this difference is differences in switching CICT ON and OFF. To completely switch a CICT ON, electrons have to traverse across ETL and accumulate at the interface and this process takes time depending on ETL mobility. However, during the initial period when electrons have not traversed across ETL yet, the field-effect principle creates a partial channel just like in a conventional TFT. As electrons travel across ETL and accumulate, the channel gets progressively stronger. Thus, both OTFT and CICT switch ON at comparable times. On the other hand, to switch OFF a CICT, the large accumulated charge has to be removed via transport across ETL and recombination, resulting in larger delays than in the conventional transistor. Fig. 8(c) shows that when capacitive loads become significant, CICT performs better because delays get limited by charge/discharge of load capacitance and CICT has higher current capability. To illustrate that the logic circuits can be built using CICT and that one CICT device can drive another similar device, a five-stage ring oscillator was simulated using device-circuit mixed mode simulation. Fig. 8(d) shows a typical output voltage where oscillation frequency of 5 kHz is obtained for τr = 10 μs and μn E = 10−4 cm2 V−1 s−1 . A fivefold increase in τr (50 μs), while maintaining the mobility constant, reduces the oscillation frequency almost fivefold to 1.3 kHz,

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highlighting the tradeoff between intrinsic speed and current driving capability. IV. C ONCLUSION In summary, a new transistor structure is proposed where the channel is created not due to electrostatic field but induced by the gate current which leads to the formation of an ED layer composed of mobile holes and electrons. The dipole is created by modifying the insulator to allow small amounts of gate current to flow through it resulting in large accumulation of charge to occur. As an example, it is shown that for mobility–lifetime product larger than 10−10 (cm2 V−1 ), channel charge more than an order of magnitude compared with the conventional field-effect capacitor can be obtained. Alternatively, for the same channel charge and current, operating voltage can be lowered by almost a factor of 3. Although gate current is a drawback, it flows entirely through the source terminal, and drain current is unaffected by it. Subthreshold slopes and OFF -current remain comparable with the conventional OTFT. By appropriately choosing mobility of carriers, unity gain frequency of the proposed transistor can be made dependent largely on channel transit time and thus comparable with the conventional transistors. The promise of the proposed device structure can only be realized if suitable material systems with appropriate characteristics can be identified. The modest demands on material parameters and the wide freedom offered by organic semiconductors in terms of mobility, energy gaps, and so on suggest that a practical realization of the proposed concept should be feasible. R EFERENCES ˙ [1] M. J. Małachowski and J. Zmija, “Organic field-effect transistors,” Opto-Electron. Rev., vol. 18, no. 2, pp. 121–136, 2010. [2] C. Tanase, P. W. M. Blom, and D. M. de Leeuw, “Origin of the enhanced space-charge-limited current in poly( p-phenylene vinylene),” Phys. Rev. B, vol. 70, no. 19, pp. 193202-1–193202-4, 2004. [3] D. J. Gundlach, Y. Y. Lin, T. N. Jackson, S. F. Nelson, and D. G. Schlom, “Pentacene organic thin-film transistors-molecular ordering and mobility,” IEEE Electron Device Lett., vol. 18, no. 3, pp. 87–89, Mar. 1997. [4] W. Xu and S.-W. Rhee, “Organic field-effect transistors with cross-linked high-k cyanoethylated pullulan polymer as a gate insulator,” Organic Electron., vol. 11, no. 6, pp. 996–1004, 2010. [5] C. Y. Han, W. M. Tang, C. H. Leung, C. M. Che, and P. T. Lai, “Highperformance pentacene thin-film transistor with high-κ HfLaON as gate dielectric,” IEEE Electron Device Lett., vol. 34, no. 11, pp. 1397–1399, Nov. 2013. [6] P. Cosseddu, S. Lai, M. Barbaro, and A. Bonfiglio, “Ultra-low voltage, organic thin film transistors fabricated on plastic substrates by a highly reproducible process,” Appl. Phys. Lett., vol. 100, no. 9, p. 093305, 2012. [7] J. Sun, Q. Wan, A. Lu, and J. Jiang, “Low-voltage electric-double-layer paper transistors gated by microporous SiO2 processed at room temperature,” Appl. Phys. Lett., vol. 95, no. 22, pp. 222108-38–222108-41, pp. 222108-1–222108-3, 2009. [8] M. J. Panzer, C. R. Newman, and C. D. Frisbie, “Low-voltage operation of a pentacene field-effect transistor with a polymer electrolyte gate dielectric,” Appl. Phys. Lett., vol. 86, no. 10, pp. 103503-1–103503-3, 2005. [9] J. Jiang, J. Sun, B. Zhou, A. Lu, and Q. Wan, “Vertical low-voltage oxide transistors gated by microporous SiO2 /LiCl composite solid electrolyte with enhanced electric-double-layer capacitance,” Appl. Phys. Lett., vol. 97, no. 5, pp. 052104-1–052104-3, 2010. [10] J. C. Scott and G. G. Malliaras, “Charge injection and recombination at the metal–organic interface,” Chem. Phys. Lett., vol. 299, no. 2, pp. 115–119, Jan. 1999. [11] I. Juri´c, I. Batisti´c, and E. Tutiš, “Recombination at heterojunctions in disordered organic media: Modeling and numerical simulations,” Phys. Rev. B, vol. 77, no. 16, pp. 165304-1–165304-13, 2008.

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