modulation in the digital domain some of these errors are alleviated. In this paper several different filter structures suitable for digital I/Q demodulation are ...
A Digital Down Converter for a Wideband Radar Receiver Henrik Ohlsson and Lars Wanhammar Department of Electrical Engineering, Linköping University SE-581 83 Linköping, Sweden email: {henriko, larsw}@isy.liu.se
Abstract In a conventional radar receiver errors are introduced due to mismatch between the ADCs and gain and phase mismatch in the I/Q demodulation. By performing the I/Q demodulation in the digital domain some of these errors are alleviated. In this paper several different filter structures suitable for digital I/Q demodulation are evaluated. Three different structures for such a digital down converter has been considered and their implementation properties has been examined. A solution combining an FIR filter with a wave digital filter is found to be the most efficient solution.
avoided. However, this ADC works at twice the sample rate of the ADCs for the conventional structure, This makes the ADC a critical component. The requirements on the digital filters are severe with respect to power consumption and throughput when the sample rate is high. LO2
RF
1.1
I
LP
ADC
Q
LO2
Introduction
The increased performance of analog-to-digital converters (ADCs) allows the digital signal processing to be moved closer to the antenna in transmitters and receivers. An example of a task suitable for digital signal processing is the I/Q demodulation in a radar receiver. Such a radar receiver is considered in this paper. The radar receiver considered in this paper is to be used in an array antenna radar system and it is developed in cooperation between FOI and Linköping University. A receiver based on the same concept has previously been designed and implemented at FOI in Linköping [1].
ADC
IF LO1
1
LP
Figure 1: Conventional receiver structure.
1.2
Considered Receiver Structure
The digital I/Q demodulation result in a receiver structure with a RF part with only one mixer stage. This mixer down converts the signal to IF. The signal is then bandpass sampled by the ADC at IF and the I/Q demodulation is performed in the digital domain [2]. Such receiver structure is shown in Figure 2. The RF and IF blocks in the figure consists of amplifiers and filters.
Motivation
In conventional radar receivers the I/Q demodulation is performed in the analog domain, as shown in Figure 1. The mixers for the I and Q channel works at the same frequency, LO2, but with a phase difference of 90 degrees between them. The two channels should have matched gains between them as well. If these two requirements is not fulfilled for all frequencies within the radar bandwidth the dynamic range of the receiver is reduced. Also, false targets may appear due to phase and gain mismatch. Another drawback with the conventional receiver is that two ADCs, one in each channel, is required. Mismatch between these ADCs will reduce the receiver performance further. By performing the I/Q demodulation in the digital domain these mixers are not needed and phase and gain mismatch between the channels can be avoided. Also only one ADC is needed. Thus, the errors due to ADC mismatch are
RF
IF
ADC
DDC
I Q
LO
Figure 2: Receiver structure with digital I/Q demodulation. The input signal to the receiver is in the range 8-12 GHz. The IF is 360 MHz and the sample frequency of the ADC is 160 MHz. After the I/Q demodulation the sample frequency is 40 MHz with a signal bandwidth of 36 MHz in each channel.
1.3
Software Receiver Model
A software model of the receiver structure has been developed in cooperation between Saab Bofors Dynamics, Eric-
sson Microwave, FOI, and Linköping University [3]. The purpose with the model is to evaluate the performance of the receiver as well as for identification of possible design trade-offs between the RF part, the ADC, and the digital filters. For the evaluation of the receiver a chirp pulse generator has been implemented in MATLAB and incooperated in the model [4]. The chirp pulse is a typical radar signal which is used in high resolution radars. The receiver model has been implemented using the Agilent tool ADS. For the RF part ADS components has been used while the ADC and the digital filters are modelled in MATLAB.
2
The Digital Down Converter
The digital down converter (DDC) considered here is based on a Hilbert transform for I/Q demodulation [5]. The quadrature component is obtained by applying a Hilbert transform on the input signal. This corresponds to a frequency shift of π/2 [6] [7]. The inphase component is obtained by delaying the input signal. This delay is matched to the delay of the Hilbert transform. In this stage a decimation of the signal sample frequency with a factor two is performed as well. For the frequency shift of the signal to baseband a highpass filter and a modulator is used. This includes a decimation of the sample rate with a further factor of two. The structure of the considered DDC is shown in Figure 3. A DDC using FIR filters has previously been implemented in full custom layout, but with more relaxed requirements [8] [9].
Since LWDFs are recursive structures there is a bound on the maximal sample frequency [11]. This bound is given by Ni 1 f s, max = ----------- = min ------ T min i Ti
where fs,max is the maximal sample rate, Tmin is the iteration period bound, Ni is the number of delay elements in loop i, and Ti is the total latency in loop i. The loop yielding fs,max is called the critical loop. By increasing the maximal sample rate for an algorithm the power consumption can be reduced since any excess speed can be traded for reduced power consumption through power supply voltage scaling [12]. When implementing interpolators and decimators with factors of two bireciprocal LWDFs, or half-band filters, are useful. Such filters are anti-symmetric around π/2 and has a reduced arithmetic complexity compared to LWDFs since every second adaptor coefficient is zero. A bireciprocal LWDF can be implemented using first-order allpass sections only. Such a filter section is shown in Figure 4 with the critical loop indicated. The sample rate bound for the first-order allpass section is 1 1 (2) f s, max = ----------- = ----------------------------------T min 2T add + T mult where Tadd is the latency of an addition and Tmult is the latency of the multiplication.
T
T
even
Delay
HP
2
a0
I a0
x(m) odd
Hilbert
HP
2
Q
x(n) y(n)
x(n)
Figure 3: Structure of the DDC.
Figure 4: A first order allpass section.
An important issue for the DDC implementation is the power consumption. In a multiple antenna radar system a large number of antennas and receivers are integrated in a small space. To avoid problems due to heat dissipation components with low power consumption should be used.
3
2.1
Lattice Wave Digital Filters
Lattice wave digital filters (LWDFs) is a class of digital filters that have several advantages compared to FIR filters [10]. For narrow transition band specifications the arithmetic complexity for a LWDF is reduced compared to an FIR filter meeting the same specification. Also, the group delay for a LWDF is lower than for a corresponding FIR filter. However, LWDFs can only be realised with approximately linear phase as opposed to FIR filters which can be designed with exact linear phase. Also, LWDFs are regular structures which makes them suitable for VLSI implementation.
(1)
y(n)
Design of the DDC
Three different approaches for realization of the DDC has been considered [13]. The first case uses FIR filters for both stages. For the second case an FIR is considered for the Hilbert transform and a bireciprocal LWDF is used for the highpass filter. Finally, for the third case, bireciprocal LWDFs is considered for both stages. For all three cases the data word length is 12 bit. The timing requirements differ between the Hilbert transform and the highpass filter. The former has a sample frequency of 80 MHz while the sample frequency for the later is 40 MHz.
3.1
FIR-FIR Solution
For the first case, using two FIR filters, we require a sixteenth-order filter for the Hilbert transform. The higpass filter is a 66:th-order filter. To obtain an efficient imple-
mentation of these filters they has been designed for a minimal number of nonzero bits in the coefficients using the method presented in [14].
3.2
FIR-WDF Solution
For the second case the highpass filter is implemented with an eleventh-order bireciprocal LWDF instead of an FIR filter. The Hilbert transform is implemented using the same FIR filter as in the first case. The coefficients for the bireciprocal LWDF has been rounded to 11 bit to meet the specification.
3.3
Case
Area (µm2)
FIR-FIR
442896
FIR-WDF
331337
WDF-WDF
395562
Table 3: Area results from logic synthesis.
WDF-WDF Solution
For the third case bireciprocal LWDFs are used for both filter stages. The Hilbert transform require a seventh-order filter and the highpass filter is the same as for the second case. The coefficients for the Hilbert transform has been rounded to 9 bit to meet the specification.
Case
fsHil,max (MHz)
fsHP,max (MHz)
FIR-FIR
128
81
FIR-WDF
128
75
WDF-WDF
86
75
Table 4: Timing results from logic synthesis.
4
Evaluation of the DDC
An estimation of the arithmetic complexity of the three solutions can be obtained by comparing the number of arithmetic operations required. Such comparison is shown in Table 1. These measures are, however, not good estimates of the resources needed for a fixed, algorithm-specific implementation of the filters. A more accurate estimation is possible if the hardware requirements for each multiplication is considered as well. Then the total number of adders needed can be computed. To do this we need to consider the algorithms used for the filters as well as the architecture to be used for the implementation. The WDFs are implemented by an isomorphic mapping of the structures to bit-parallel, carry save arithmetic [15] [16]. The FIR filters are linear phase filters and are implemented using the direct form algorithm. The multiplications in the FIR filter is merged to one adder tree and mapped to carry save adders. Case
Multiplications
Additions
FIR - FIR
41
73
FIR - WDF
15
39
WDF - WDF
13
41
Table 1: Arithmetic operations required. Case
CSA
CPA
Memory elements
FIR-FIR
84
39
108
FIR-WDF
102
15
30
WDF-WDF
122
13
13
Table 2: Hardware components required.
The result of the comparison when the architecture is considered is shown in Table 2, where CSA stands for carry-save adders and CPA stands for carry propagation adders. As can be seen the case with two FIR filters requires many memory elements as well as a large number of CPAs. On the other hand the realizations which includes LWDFs requires a larger amount of carry save adders. However, the complexity of a CSA is always the same, or lower than for a CPA. Thus, to evaluate the complexity of the different realizations, implementations of all three cases should be considered.
5
DDC Implementation
The three different solutions has been implemented in structural VHDL. The filters has been mapped to a 0.18 µm CMOS process from STMicroelectronics using the Synopsys tool Design Compiler. In Table 3 the area requirement for the three solutions after the logical synthesis is shown. Table 4 shows the maximal sample frequency for the three cases using a power supply voltage of 1.55 V. As can be seen the maximal sample frequency for the FIR filters and the WDF highpass filter is significantly larger than the required sample frequency. Thus, the power supply voltage may be scaled to reduce the power consumption for these two cases. The result from the logic synthesis is that the FIRWDF case is the most area efficient solution with an area of about 75% of the area for the worst case, the FIR-FIR solution. Also, all three solutions meets the timing requirements. However, the WDF-WDF does not have as large margin for power supply voltage scaling as the two other cases. Thus, the results from the logic synthesis is that the FIR-WDF solution is the most efficient for implementation. However, it is possible to improve the maximum sample frequency of the WDF and thereby reduce the power consumption further. This can be done by arithmetic transformations of the algorithm [17] [18] [19]. For a bitparal-
lel, carry save arithmetic implementation the maximal sample frequency can be increased by 20% to 30%, depending on the number of nonzero bits in the coefficients. This is at the expense of a small increase of the area required for the transformed allpass section.
6
Conclusions
In this paper we discuss the implementation of a digital down converter for a radar receiver. The purpose with the digital down converter is to remove errors due to phase and gain mismatch in the I/Q demodulation as well as mismatch between the ADCs. By performing the I/Q demodulation in the digital domain some of these errors are alleviated. We propose three different filter structures and compare their implementation properties. The results from the logic synthesis give that the FIR-WDF case is the most efficient for implementation.
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