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Abstract—A family of “Two-Switch Boosting Switched-. Capacitor Converters (TBSC)” is introduced, which distinguishes itself from the prior arts by symmetrically ...
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 10, OCTOBER 2015

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A Family of Two-Switch Boosting Switched-Capacitor Converters Bin Wu, Student Member, IEEE, Shouxiang Li, Student Member, IEEE, Keyue Ma Smedley, Fellow, IEEE, and Sigmond Singer, Member, IEEE

Abstract—A family of “Two-Switch Boosting SwitchedCapacitor Converters (TBSC)” is introduced, which distinguishes itself from the prior arts by symmetrically interleaved operation, reduced output ripple, low yet even voltage stress on components, and systematic expandability. Along with the topologies, a modeling method is formulated, which provokes the converter regulation method through duty cycle and frequency adjustment. In addition, the paper also provides guidance for circuit components and parameter selection. A 1-kW 3X TBSC was built to demonstrate the converter feasibility, regulation capability via duty cycle and frequency, which achieved a peak efficiency of 97.5% at the rated power. Index Terms—Frequency modulation, interleaved, modeling, switched-capacitor, two-switch boosting switched-capacitor converters (TBSC).

I. INTRODUCTION WITCHED capacitor (SC) converter is an important branch of power electronics converters which is composed of capacitors and switches without the participation of inductors/transformers. It potentially has lower electromagnetic interference, lighter weight, lower cost, higher energy density, and the potential for full integration [1]. However, there are some intrinsic features related to SC converters as well as challenges in developing SC converters need to be recognized. First of all, the efficiency of SC converter is closely related to voltage gain and circuit structure [2], [3]. Thus, when a voltage gain requirement and load range are given, it is essential to pair it with a proper topology and circuit parameters in order to achieve high efficiency. Additionally, pulsating input current and weak regulation capability are some of the weaknesses to overcome before SC converter can be widely adopted. It is desirable to develop SC converters with simple circuit structure, minimized pulsating input current, small output voltage ripple, good regulation capability, and scalability for power and gain. Great efforts have been reported in the research community. Many research institutions such as IBM, Intel, and UC Berkeley have realized chip level-integrated SC converters in [4]–[8]. [8]

S

Manuscript received July 19, 2014; revised October 3, 2014; accepted November 12, 2014. Date of publication December 2, 2014; date of current version May 22, 2015. This work was supported by BSF under Grant 2011507. Recommended for publication by Associate Editor M. Ferdowsi. B. Wu, S. Li, and K. Ma Smedley are with the Department of Electrical Engineering and Computer Science, University of California, Irvine, CA 92617 USA (e-mail: [email protected]; [email protected]; smedley@ uci.edu). S. Singer is with the School of Electrical Engineering, Tel Aviv University, Tel Aviv 69978, Israel (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2014.2375311

compared several fully integrated SC converters and reported a converter with efficiency of 86% and power density of 4.4 W/m2 . Some partial-integrated SC converters with flying capacitors off the chip were also reported. [9] reported a peak efficiency of 97% of partial-integrated SC converter with voltage gain of 2/3 which converted voltage from 1.83 to 1.2 V by employing external flying capacitors of 1 μF. Extensive study has been presented in journals or conference proceedings aiming to reduce the input pulsating current and output voltage ripple. Some interleaved buck type and boost type SC converter structures were proposed using PWM control for this purpose [10]–[12]. These approaches require a large number of components leading to increased volume and cost. Some modifications were proposed in paper [13] that provides better suppression of the input spike by using quasi-switched control instead of PWM control. It controls the switch as a current source to regulate the output voltage, resulting in smoother input current but a more complicate control circuit and narrower regulation range. Another approach was proposed in [14] using adaptive mixed on-time and switching frequency control with four similar SC subcircuits and interleaved them by 90 ° to realize smooth input current. But variable switching frequency and complicated circuit structure brought difficulty in component selection and increased cost. Some control strategies were reported to tackle the weak regulation capability, which is caused by the rush current during power delivery stage between the source and a capacitor or between two capacitors. This rush current changes the voltage of capacitors in a very short period, which is difficult to detect and control in one switching cycle. The study reported in [15] investigated the essence of SC converter based on several traditional topologies and provided a general regulation solution based on SSL and FSL output impedance. Generally, three dominant regulation strategies were widely reported in the past literatures. In chip level, frequency modulation, ranging from several MHz to several hundreds of MHz, was reported in [16] and [17]. For power level ranging from several watts to tens of watts, PWM regulation strategy seems dominant [18]. Another method seen in the literature is the on-resistance control method. The quasiswitched control mentioned earlier belongs to this type. This paper will present a general way to derive a detailed circuit model and reveal the relationship of circuit parameters with voltage ratio, which uncovers the multidimensional regulation property quantitatively. Although SC converters are initially intended for low power applications targeting full integration in CMOS level, researchers have found it also suitable for handling high power

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conversions, such as energy storage system or front end dc–dc converter in renewable systems [19], [20]. [19] reported a unregulated 1-kW SC dc–dc converter for 42-V automobile system with a peak efficiency of 98%. But the topology has a high component voltage stress (VS) and strong pulsating current. In order to suppress pulsating current, [21] uses the stray inductance in circuit to increase the power to 55 kW. [22] and [23] proposed some new SC converters based on resonance concept by utilizing stray inductance or physical air core inductor and careful selection of switching frequency. This method realized ZVS in some conditions. However, it is difficult to make stray inductance of all the traces the same for all charging and discharging loops. Moreover, the value of flying capacitors may change with time, which will alter the resonant frequency. To cope with the uncertainty of the value of stray inductance, [23] proposed to use air core to secure predictable resonance. Furthermore, an additional buck-boost converter is incorporated into the resonant switch capacitor converter to achieve output voltage regulation. In [24], a two stage central source two-level dc–dc module was presented, which differentiated itself from the traditional ladder converter [25], [26] by moving the source form bottom to center, aimed at bidirectional power control in battery system of hybrid vehicles. Due to its power bidirectional capability, four power switches were still needed with only voltage gain of two. Besides, the circuit model was not given and no regulation was performed. Inspired by the study reported in the aforementioned papers, a “Two-Switch Boosting Switched-Capacitor Converter (TBSC) Family” for unidirectional power conversion is proposed in this paper, with detailed evolution procedure starting from a doubleswitch core. It inherits some of the advantages of traditional ladder converter, but the proposed circuit provides lower cost, simpler control, lower output voltage ripple, symmetrical properties. Along with the topologies, duty cycle and frequency regulation are provoked through proposed model. The proposed TBSC family characterizes itself by following aspects: 1) symmetrical structure with automatic interleaving operation based on only two active switches; 2) uncommon ground between input and output; 3) capability of pulse width modulation and frequency modulation for output voltage; 4) comparatively low voltage rating of all components; 5) flexible gain extension for different gain applications. II. PROPOSED TBSC FAMILY AND OPERATION A. Proposed TBSC Family and Operation The proposed TBSC family contains n members, where n = 1, 2, 3 . . .. The first member is the 1X TBSC as shown in Fig. 1(a). It is merely a two-switch three-terminal network with terminal 0, 1, and 1’; nevertheless, it is the core to build the entire TBSC family. For all TBSC members, terminal 1-1’ is defined as the low side, while terminal n-n’, high side. In order to obtain the second member in the TBSC family, a pair of n = 2 gain-extension networks, the top one with terminals 0, 1, and 2 and the bottom one with terminals 0’, 1’, and 2’ as shown in figure Fig. 2 are added to the 1X TBSC as

Fig. 1. Proposed TBSC family (a) 1X THBC (b) 2X THBC (c) 3X THBC (d) 4X THBC.

Fig. 2.

Gain-extension network (n = 2, 4, 6 . . .) (a) Top (b) Bottom.

Fig. 3.

Gain-extension network (n = 3, 5, 7 . . .) (a) Top (b) Bottom.

shown in Fig. 1(a). By connecting the matching terminals of the gain-extension network and the 1X TBSC, the 2X TBSC is derived as shown in Fig. 1(b). The voltage at the high side of the 2X TBSC configurations is double of that of the low side under the case of no load and idea components (ideal condition), by operating the two switches S1 and S2 in an interleaved manner. Further, by adding a pair of n = 3 gain-extension networks as shown in Fig. 3 to the 2X TBSC in a similar fashion, the 3X TBSC can be derived as shown in Fig. 1(c). The new configuration triples the low-side voltage by operating the two active switches S1 and S2 in an interleaved manner under ideal condition. To synthesize the 4X TBSC topology, a pair of n = 4 gainextension networks in Fig. 2 are added to the 3X TBSC topology in a similar fashion. Thus, a new member with 4X gain is derived as shown in Fig. 1(d). This process can continue indefinitely to obtain a TBSC with an ideal gain of arbitrary positive digital number n, by applying gain-extension network. In general, in order to obtain nX TBSC, a pair of three-terminal gain-extension networks, the top one with terminals n – 2, n – 1, and n and the bottom one with terminals (n – 2)’, (n – 1)’, and n’, as shown in Figs. 2 or 3, are added to the (n – 1)X TBSC. By connecting the matching

WU et al.: FAMILY OF TWO-SWITCH BOOSTING SWITCHED-CAPACITOR CONVERTERS

Fig. 4.

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Topology of 2X TBSC. Fig. 6.

Fig. 5. Operation states of 2X TBSC. (a) State 1 [0, dTs]. (b) State 2 [dTs, Ts/2] and State 4 [(d+1/2)Ts, Ts]. (c) State 3 [Ts/2, (d+1/2)Ts]. (d) Key waveforms.

terminals of the gain-extension network to the (n – 1)X TBSC, the nX TBSC configuration is derived. The voltage at the high side is n times of the low-side voltage (applied to terminal 1 and 1’) by operating the two active switches S1 and S2 in an interleaved manner under an ideal condition. Due to the symmetrical interleaved configuration of the circuit, the output voltage ripple is reduced. Additionally, all components voltage rating is set by low side voltage. In this paper, 2X TBSC and 3X TBSC are illustrated as example, and experimental results of 3X TBSC converters are given. B. Operation of 2X TBSC With PWM Control A simple voltage doubler as second member of TBSC family is shown in Fig. 4, with source and load connected. Note that output filter capacitor is not necessary due to serial connection of C1a and C1b . The switch S1 and S2 will be controlled by interleaved PWM signal described by two top waveforms shown as Fig. 5(d). The “dead-time” which indicates the time period when both switches are OFF is controlled intentionally to

Topology of 3X TBSC.

modulate the output voltage. Therefore, four operation states will be observed during a period shown as Fig. 5. 1) State 1 [0, dTs]: Switch S1 is turned ON during [0, dTs] while the duty cycle d is within the range of [0, 0.5]. When S1 is ON, the energy from input source will partially charge C1b though D1b and partially provide the load current directly [see Fig. 5(a)]. The output voltage equals to the sum of capacitor voltage Vc1a and Vc1b . 2) State 2 [dTs, Ts/2]: When S1 and S2 are both OFF, it comes to state 2 shown as Fig. 5(b). Both diodes D1a and D2a become reversed biased and only capacitor C1a and C1b are connected in series to charge the load. Input current Iin becomes zero at this state. 3) State 3 [Ts/2, dTs+Ts/2]: At this state, switch S2 is ON while S1 is kept OFF, shown as Fig. 5(c).The energy from input source will be partially delivered to load and partially used to charge capacitor C1a . 4) State 4 [dTs+Ts/2, Ts]: This state repeats state 2. By interleaved operation of S1 and S2 , the input current ripple has the frequency twice of the switching frequency. Moreover, based on the automatic interleaved structure, the output voltage ripple is smaller due the ripple cancellation of capacitors C1a and C1b . Key waveforms are shown in Fig. 5(d). C. Operation of 3X TBSC With PWM Control The 3X TBSC converter, shown as Fig. 6, is more complicated compared with 2X TBSC as it contains coupled switchedcapacitor loops. These coupled loops, formed by sourcecapacitor pair and capacitor–capacitor pair, realize charge redistribution by sharing a common circuit path. The 3X TBSC converter has following unique properties: First, it can serve as a voltage tripler under an ideal condition. In real case, where components loss exists and load is nonzero, a duty ratio closer to 0.5 can achieve higher gain and higher conversion efficiency. Second, the input source is cascading with two flying capacitors C2a and C2b to build up the output voltage. These two flying capacitors C2a and C2b exhibit interleaved voltage ripples, which alleviate each other. Therefore, the output voltage ripple of proposed topology is expected to be smaller, yielding a smaller output filter capacitor or even skip.

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TABLE I COMPONENTS NUMBER COMPARISON Topology

Gain under ideal condition

Flying capacitors

Switches

Diodes

2 3 n 2 3 4

2 4 2(n–1) 2 4 8

2 2 2 4 8 14

2 4 2(n–1) 4 6 8

Proposed 2X TBSC Proposed 3X TBSC Proposed nX TBSC Paper [27] Paper [12] Paper [28]

TABLE II COMPONENTS STRESS COMPARISON Topology

Fig. 7. Operation states of 3X TBSC. (a) State 1 [0, dTs]. (b) State 2 [dTs, Ts/2] and State 4 [(d+1/2)Ts, Ts]. (c) State 3 [Ts/2, (d+1/2)Ts]. (d) Key waveforms.

Third, the input source will keep delivering current to load even both switches are turned OFF, shown in figure Fig. 7(b). This property, however, is different from 2X TBSC. It means for the whole period, the power source will keep on sending out energy. Detailed operation modes and waveforms are explained as following: 1) State 1 [0, dTs]: When S1 is ON, as shown in Fig. 7(a), the input source will charge the flying capacitor C1b . At the same time, it cascades with C2a and C2b to build up the output voltage. The flying capacitor C2a is charged by C1a at the same state and C1a is also delivering power to load. 2) State 2 [dTs, Ts/2]: When both switches are OFF, the input source will be connected with C2a and C2b in series to power the load together. Thus, input current Iin equals to the load current at this state, shown as Fig. 7(b). 3) State 3 [Ts/2, dTs+Ts/2]: In Fig. 7(c), when S2 is turned ON while S1 is OFF, the input source starts to charge C1a which was releasing its energy in state 1. Thus, C1a can keep charge balance in one switching period. Meanwhile, it is in series with C2a and C2b to power the load. C2b is charged by C1b at the same time. 4) State 4 [dTs+Ts/2, Ts]: This state repeats state 2, given as Fig. 7(b). D. Component Count and Stress Analysis The proposed family of SC converter not only has small output ripple, but also low cost. The component count comparison for proposed topologies and previous works is given as Table I.

Gain

Flying Switches capacitors VS VS VS

Proposed 2X TBSC

2

Vin

Vin

Proposed 3X TBSC

3

Vin

Vin

Proposed nX TBSC

n

Vin

Vin

Paper [27]

2

Vin

Vin

Paper [12]

3

Vin

Vin

Paper [28]

4

Vin

Vin

Switches CS (rms)

Io u t √ d 2I o u t √ d (n − 1)I o u t √ d 0.5I o u t √ d 0.5I o u t √ d 0.5I o u t √ d

Diodes VS

Vin Vin Vin Vin Vin Vin

Diodes CS (rms)

Io u t √ d Io u t √ d Io u t √ d 0.5I o u t √ d 0.5I o u t √ d 0.5I o u t √ d

According to the table, the proposed topologies greatly minimize the number of semiconductor components while maintaining interleaving benefits and regulation capability. Thus, the cost can be reduced and volume shrunk. Assuming the input voltage at low side is Vin and the load current is Iout , the components voltage stress (VS) and current stress (CS) are given in Table II, in comparison with previous works. Here, average current during on state of semiconductor components is used to calculate RMS current for CS estimation. Based on the comparison outlined in Tables I and II, taking the proposed 3X TBSC as an example, it has the same number of capacitors as the converter proposed in [12], but has six semiconductor components (switches and diodes) compared with 14. Although the component CS of proposed converter is higher, a smaller converter size can still be expected because the VS is the same and fewer driving circuits and control circuits are required for the proposed topology. III. MODELING OF PROPOSED SWITCHEDCAPACITOR CONVERTER In the past, the voltage gain of switched-capacitor converter were derived from the state-space averaging method [12], [18], [28]. The final voltage gain equation will reflect the effects from load, equivalent serial resistance (ESR) of flying capacitors, onresistance of switches and duty ratio on circuit voltage gain. This is accurate enough for control design of PWM modulation strategy. [14] derived the gain equation of SC converter

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described by waveform Vc1b in Fig. 5(d). By applying the KVL to the circuit, the following equation can be obtained:   dVc1b (t) Vin = Iout + C (Ron + rd ) dt dVc1b (t) + Vc1b + Vd . (1) dt According to the boundary condition Vc1b (0) = Vc1bm in , the following result is derived: + rC

s − ( r + R od nT + r

Vc1b m ax = (Vc1b m in − Vm )e

d )C

+ Vm

(2)

where Vm = Vin − Vd − Iout (Ron + rd ). Due to interleaving configuration, C1a and C1b have the same voltage ripple amplitude but opposite phase. As a result, the output voltage can be approximated Vout = Vc1b m ax + Vc1b m in .

Fig. 8. Equivalent circuits in different states for 2X SC converter. (a) State 1 [0, dTs]. (b) State 2 [dTs, Ts/2] and State 4 [(d+1/2)Ts, Ts]. (c) State 3 [Ts/2, (d+1/2)Ts]. (d) State 4 [(d+1/2)Ts, Ts].

(3)

In Fig. 8(c), (d), and (e), C1b is discharged with current Iout , causing its voltage decreasing from Vc1bm ax to Vc1bm in . According to charge balance principal, the following equation can be obtained: C(Vc1b m ax − Vc1b m in ) = Iout (1 − d)Ts .

dependent on switching frequency although did not pursue frequency modulation. In this section, a modeling procedure based on transient calculation and charge balance is applied to 2X TBSC and 3X TBSC to derive the voltage gain. The model is able to predict the effect as outlined in previous papers. In addition, the flying capacitance and switching frequency impacts on output voltage is clearly identified. In order to facilitate the calculation and derive concise result, some assumptions are made: The load current Iout is assumed to be constant which equals to Vout /RL . The reason to model the load as a current source is based on two unique properties of the proposed structure. The output voltage is constant and a resistor is connected to it, which consumes nearly a constant current. The other reason is that the symmetrical structure and interleaved PWM control lead the converter to operate with very small output ripple condition. The current source approximation facilitates the charge calculation during modeling procedure. The flying capacitors are assumed to have the same capacitance C. Film capacitors are adopted with small ESR r. Also, S1 and S2 have the same on-resistance Ron . All diodes are modeled as voltage source Vd in series with a resistor rd . Some simplifications are adopted based on following assumptions: rd  RL , Ron  RL , Vd  Vin , r  Ron . A. Modeling of 2X TBSC Converter 1) Derivation of Voltage Gain: The subcircuits in Fig. 5 are simplified to their equivalent circuits, shown in Fig. 8 for calculation purpose. Fig. 8(a) shows the equivalent circuit of state one, which is the only time that capacitor C1b gets charged during one switching period. Therefore, its voltage rises from Vc1bm in to Vc1bm ax , as

Based on (2)–(4) and noting that Iout = of 2X TBSC can be derived

Vo u t RL

(4)

, the voltage gain

Vout 2RL C(1 − e− R C ) = dTs Vin (1 − d)Ts + RL C + [(1 − d)Ts − RL C]e− R C dTs

(5)

where R = Ron + rd + r. According to (5), if RL → ∞, the gain of 2X TBSC will reach its ideal condition result Vout = 2. (6) lim R L →∞ Vin 2) Input Current Spike Analysis: Based on (2)–(4), the minimum voltage of C1b can be derived Vc1b m in =

−(1 − d)Ts + CRL Vout . 2CRL

(7)

The transient input current can be expressed as following during [0, dTs ]: Iin (t) =

(Vm −Vc1bm in ) − C ( R o n +t r + r ) d e + Iout (Ron + rd + r)

(8)

where Vm = Vin − Vd − Iout (Ron + rd ). Based on (7) and (8), the input current spike can be obtained as Vin − Vd Ispike = Iin (0) = Ron + rd + r −

CRL − (1 − d)Ts − 2Cr Vout . 2CRL (Ron + rd + r)

(9)

According to (9), input current spike is dependent on many circuit and control parameters. However, based on (5), increasing frequency leads to higher Vo . Thus, under the condition CRL > (1 − d) Ts + 2Cr which is satisfied easily, higher frequency leads to smaller input current spike.

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Fig. 9.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 10, OCTOBER 2015

Waveforms of ΔV c 1 a , ΔV c 1 b , ΔV o u t under d = 0.25.

Fig. 12.

Fig. 10.

Waveforms of ΔV c 1 a , ΔV c 1 b , ΔV o u t under d = 0.5.

Fig. 11. Equivalent circuits in different modes for 3X TBSC converter. (a) State 1 [0, dTs]. (b) State 2 [dTs, Ts/2] and State 4 [(d+1/2)Ts, Ts]. (c) State 3 [Ts/2, (d+1/2)Ts].

3) Output Voltage Ripple Analysis: The voltage ripple of capacitors C1a , C1b and Vout are described under different duty cycles in Figs. 9 and 10. Base on the equivalent circuits shown in Fig. 8 and corresponding waveform in Fig. 9, the quantitative expression of output voltage ripple magnitude can be given as following:   Iout (1 − d)Ts + Iout 12 − d Ts ΔVout = C Iout 12 Ts (1 − 2d)Ts = (10) C C When the duty cycle d is less than 0.5, partial cancelation is achieved. But if the duty cycle reaches its maximum value 0.5, full cancelation can be obtained, which means zero output voltage ripple can be derived, as shown in Fig. 10. −

B. Modeling of 3X TBSC Converter The similar modeling method of 2X TBSC converter can be applied to 3X TBSC converter. The equivalent circuit of operation states in Fig. 7 is given as Fig. 11. However, the 3X TBSC converter has coupled charging loops as mentioned before, which can increase the difficulty to derive voltage gain. For instance, in Fig. 11(a), C2a and C1b are charged at the same time within loop 1 and loop 2, respectively, which share the

Loop decoupling procedure.

switch of S1 . Solving the differential equations without loop decoupling will make the calculation complicated. Therefore, a loop decoupling technique is developed. 1) Loop Decoupling Technique: Fig. 12 shows the loop decoupling procedure of two coupled loops in the subcircuit of Fig. 11(a). In Fig. 12(a), the current i1 and i2 equals to the current flowing though diode D2a and D1b , respectively, which have the same average current of iout . Therefore, i1 can be approximated the same as i2 . The loop current i1 will cause extra voltage drop i1 Ron along loop 2, thus a corresponding current control voltage source is installed in the decoupled loop 2 as shown in Fig. 12(b). Due to the equality of i1 and i2 , the current control voltage source can be further involved to resistor Ron . The final decoupled loops are shown as Fig. 12(c). With the decoupled loops, the circuit transient calculation equations can be derived much more convenient. 2) Voltage Gain Derivation: In Fig. 11(c), loop 1 and loop 2 can be decoupled the same way as shown in Fig. 12. C1a is charged from Vc1am in to Vc1am ax through loop 1. Solving the differential equation based on its decoupled loop, the following equation is derived: Vc1a m ax = Vin + e− R 1 C (Vc1a m in − Vin + Vd ) − Vd dTs

(11)

where R1 = 2Ron + rd + r. Assume C2a is charged from C2am in to C2am ax in Fig. 11(a) within loop 2. Solving the differential equation based on decoupled loop, the following equation can be derived: (m − n) (m + n)e− R 2 C Iout dTs − + (12) 2C 4 4 where m = 2Vd − 2Vc1a m ax (rd + 2Ron )Iout , n = 2Vc2am in , R2 = 2Ron + rd + 2r. Since all the electrical charge delivered to load will be first stored in C1a during each switching period, the following equation can be derived: 2dT s

Vc2a m ax = −

(Vc1a m ax − Vc1a m in )C = Iout Ts

(13)

As the voltage of C2a decreases from V2am ax to V2am in during state 2, 3 and 4, the following equation is obtained: (Vc2a m ax − Vc2a m in )C = Iout (1 − d)Ts

(14)

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Meanwhile,Vc2b has the same voltage ripple configuration as Vc2a but opposite phase. Thus, the output voltage can be approximated as following: Vout = Vc2a m ax + Vc2a m in + Vin

(15)

In this paper, film capacitors are adopted. ESR is small compared with Ron . In order to make the final voltage gain more concise, the following approximation of general loop resistance R is given: R = R1 = R2 = rd + 2Ron + r

(16)

Based on (11)–(16), the final voltage gain equation can be derived, as shown at the bottom of the page. Based on (17), switching period Ts and duty cycle d can be used to regulate the voltage gain.Besides, loop resistance R, flying capacitance C, load RL , will also impact the final voltage gain, which is critical to achieve high system efficiency. Unlike the boost converter, this converter can work under no load condition. When RL → ∞, the following result can be got:   2dT s 3CRL 1 − e− R C Vout   =3 = lim (18) 2dT s R L →∞ Vin CRL 1 − e− R C 3) Input Current Spike Analysis: According to Fig. 12(c), during [0,dTs ], the input current can be expressed as Vin − Vc1b m in − Vd − 2 R o n +t r + r d + I e Ii n (t) = out 2Ron + rd + r

(19)

Based on equations from (11)–(16) and circuit symmetry, the minimal voltage of C1b is simplified as following: Vcb m in = Vca m in = Vin −

1 Ts Vout CRL 1 − e− dRTCs

(20)

Therefore, the input spike can be derived based on (19) and (20)   Ts Vout 1 Vd + + 1 (21) Ispike = − R RC 1 − e− dRTCs RL It can be seen that the input current spike is dependent on switching frequency, loop resistance (Ron , ESR, rd ), flying capacitance and load. 4) Output Ripple Analysis: For 3X TBSC, the output voltage ripple is determined by the voltage ripple of capacitor C2a and C2b , who have the same ripple cancelation mechanism as 2X TBSC. The output ripple magnitude is the same as describe in (10). Therefore, full ripple cancelation is also achieved at duty cycle of 0.5 for 3X TBSC. C. Circuit Parameter Analysis In order to investigate the influence of control parameters and circuit parameters, the voltage gain as function of C, R, f, d, are

Fig. 13.

Parameters effect of voltage gain of 3X TBSC converter.

TABLE III DEFAULT VALUES OF PARAMETERS C (μF) 100

R (Ω)

fs (Hz)

d

0.15

10k

0.45

plotted in Fig. 13, based on (17). Their default values are shown as Table III. Fig. 13(a) indicates larger capacitance leads to higher voltage gain and higher efficiency as confirmed by many other papers. This is because large capacitance leads to smaller voltage difference between two interacting capacitors in each cycle and the efficiency of power delivery between capacitors is determined by the voltage difference. Fig. 13(b) reveals a larger loop resistance degrades the voltage gain, which means the efficiency will drop. This statement is under the condition when output voltage is not regulated. In reality, larger loop resistance will reduce the power deliver capability of circuit, thus the maximum gain will be limited. Therefore, maximum efficiency will be lowered. Fig. 13(c) shows that frequency can be used to regulate the output voltage because higher frequency leads to higher voltage gain. However, the frequency regulation is evident in low frequency range while in higher frequency range, the regulation curve tends to be flat based on the given condition of other parameters. Higher frequency tends to result in higher voltage gain. Therefore, increasing frequency can increase efficiency. This statement is made when ESL is not considered. Fig. 13(d) shows that duty cycle can be used to regulate the output voltage, known as PWM control strategy. The voltage gain will rise with the increase of duty cycle. When the output voltage is left unregulated, increasing the duty cycle will lead to higher system conversion efficiency.

  2dT s 3CRL 1 − e− R C

Vout = 2dT s dTs Vin −(CRL + dTs − 3Ts + RC)e− R C + 2Ts e− R C + RC + CRL − dTs + 3Ts

(17)

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TABLE IV PARAMETERS OF THE EXPERIMENTAL PROTOTYPE Component

Model

Number

Parameter

MOSFETs Diodes

FQA40N25 STTH2002C

2 4

Flying Capacitors

Film capacitor(C2AE)

4

R o n = 70 mΩ V d = 0.78 V, rd ≈ 10 mΩ 100 μF, E S R = 2.6 mΩ (10 kHz,70 °C)

TABLE V PARAMETER CONTROL FOR TESTING Switching Frequency (Hz) 1k 4k 10 k

Duty cycle d

Load (Ω)

Vi n (V)

0.025;0.05; 0.1;0.45 0.025;0.05; 0.1;0.45 0.025;0.05; 0.1;0.45

160

40

The introduced modeling method can be used for parameters tradeoff. For other converters among the proposed step-up SC converter family, the voltage gain of nX TBSC converter can also be derived using similar modeling method. However, a general voltage gain expression has not been derived. High order TBSC loop decoupling is much more complex, which is out of the scope of this paper. IV. EXPERIMENTAL VERIFICATION To confirm the feasibility of proposed TBSC topology and the property of frequency modulation and duty cycle modulation, a 3X TBSC prototype was built as an example design. The components are listed in Table IV. AVR microcontroller Tiny 24 from Atmel corporation is used to generate the two channel-interleaved PWM signals to drive the switches. The dead time is deliberately controlled to modify the duty cycle. In order to investigate the modulation property of 3X TBSC converters, the input voltage is fixed at 40 V to make sure that the input current spike will not exceed component current rating with various switching frequency operation conditions. The modulation capability of duty cycle and frequency on voltage gain of 3X TBSC is tested. The test conditions are given as Table V. A. Duty Cycle and Frequency Modulation Effect The waveforms of Vg s , Vin , Vout and Iin are given in Fig. 14 under various frequency and duty cycle conditions. Note that the soft current rising edge becomes more noticeable when the frequency goes up to 10 kHz. This soft current rising is due to the coupling of two charging loops, which is neglected during modeling procedure for simplicity. Therefore, the model result is more accurate under low frequency condition. The experimental curve of duty cycle modulation and frequency modulation is compared with model prediction in Figs. 15 and 16. In Fig. 15, it can be seen that when the duty cycle increases, the output voltage is increasing. The modulation effect is strong under low duty cycle condition. When the duty cycle is smaller,

the voltage gain is far below the idea condition voltage gain, which indicates low conversion efficiency. The loss is dissipated within the circuit in the form of switching loss or conduction loss. For example, Fig. 14(c) shows duty cycle at 0.05 under 1-kHz switching frequency. The input current is chopped compared with smoother dropping in figures (a) d = 0.45 and (b) d = 0.1. It indicates the switches are turned OFF under high current condition which introduces larger conduction loss at d = 0.05. By comparing Fig. 14(d) and (f), it is found not only switching loss increases by decreasing duty cycle, but also conduction loss due to increased conduction current. Therefore, lower efficiency under low duty cycle case can be expected. The modeling results shown in Fig. 15 is slightly higher than the experimental results which may be caused by stray resistor and neglected element such as voltage drop of diode in final voltage gain equation. In Fig. 15(b), the comparison is made under 10 kHz condition and a little larger error appears which shows circuit parasitic parameters starts to show more significant effect with the increase of frequency. In frequency modulation testing case given in Fig. 16, the duty cycle is fixed at 0.45. High duty cycle is used here because with low duty cycle, increasing frequency will cause the turn on time to be extremely small, which may introduce high testing error due to parasitic parameters. Here, the frequency is changed from 1 to 10 kHz, while the load is fixed at 160 Ω. Fig. 16 shows that when the frequency increases, both model and experimental result show higher voltage gain. The modulation capability of frequency is thus confirmed. Under low frequency condition, lower voltage gain is obtained which means lower system efficiency. The loss will be dissipated mainly as conduction loss. Comparing Fig. 14(a) and (d) which show the cases of 1 and 4 kHz, much higher conduction current is found in the case of 1 kHz condition, coinciding with lower voltage gain at 1 kHz described as Fig. 16. B. High Efficient Design Consideration Efficiency under various frequency and duty cycle is also tested with Vin = 40 V. The curves are shown Fig. 17(a) and (b). Fig. 17(a) shows that when the other parameters are fixed, higher duty cycle leads to higher efficiency, which is similar to the voltage gain curve. Fig. 17(b) shows the efficiency will also increase by increasing the frequency. But the curve will become almost flat when the frequency reaches some point. The curves demonstrate that when the value of the flying capacitor is fixed, the switching frequency does not have to be very high to reach a good efficiency. In the low frequency range, e.g., less than 10 kHz, a high input voltage may cause a large input current spike, exceeding the component CS of designed prototype. On the other hand, under low input voltage condition, the system efficiency is not optimized due to parasitic parameters effect. When the input voltage increases, the frequency should increase to limit the current spike under an acceptable level. Therefore, two input voltage conditions 100 and 150 V are tested under

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Fig. 14. Waveforms of Vg s1 , Vin , Vo u t and I in . (a) f s = 1 k, d = 0.45. (b) f s = 1 k, d = 0.1. (c) f s = 1 k, d = 0.05. (d) f s = 4 k, d = 0.45. (e) f s = 4 k, d = 0.1. (f) f s = 4 k, d = 0.05. (g) f s = 10 k, d = 0.45. (h) f s = 10 k, d = 0.1. (i) f s = 10 k, d = 0.05.

Fig. 15. Comparison of duty cycle modulation between experiment and model under (a) 1 kHz, 4 kHz and (b) 10 kHz.

two groups of switching frequencies: 10, 16, 20 kHz and 16, 20, 30 kHz, respectively. The tested efficiency is plotted as dots in Fig. 18. The maximum efficiency of 97.5% is achieved under 150-V input voltage and 20-kHz switching frequency condition. Under the maximum efficiency condition, the key waveforms by simulation and experiment are presented in Fig. 19. Note that Iin1 here is not the input current but the input current plus the current of C2a , as depicted in Fig. 7. It further confirms the

Fig. 16. Comparison of frequency modulation between experiment and model under duty cycle of 0.45.

input current has soft current rising edge due to the coupling loop effect as no stay inductance is included in simulation case. C. Ripple Cancelation As stated previously, the TBSC family has small output voltage ripples. The reason is due to its natural interleaved operation, which makes the flying capacitors CX a and CX b exhibit interleaved voltage ripple. The ripple cancelation under duty cycle of 0.25 and 0.45 are given in Fig. 20(a) and (b). It can be seen when

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 10, OCTOBER 2015

Fig. 17. Relationship between duty cycle and frequency under fixed load. (a) Efficiency versus duty cycle. (b) Efficiency versus frequency. Fig. 19. Waveforms of Vg s1 , Vin , Vo u t and Iin 1 under f s = 20 kHz, d = 0.45. (a) Simulation result. (b) Experimental result.

V. EXTENSION OF TBSC FAMILY A. Bidirectional TBSC

Fig. 18. Relationship between frequency and efficiency with input voltage of 100 and 150 V.

the duty cycle is small, the output ripple is not full cancelled but still smaller compared with the ripple of each flying capacitor. When the duty cycle is controlled at 0.45, the ripple cancellation effect is much more significant. The ripple of flying capacitors also demonstrates that the load can be approximated as current source due to its linear voltage decrease phenomenon.

The nX TBSC topology can be modified to realize bidirectional power flow by replacing all the diodes with switches. For example, the nX TBSC has its bidirectional version as shown in figure Fig. 21. Either of the voltage sources VL and VH can be used as the input source. In Fig. 21, if a voltage source is connected at low side and load is connected at high side, only S1 and S2 are required to be trigged to deliver power from source to load. If the source is connected at high side and load at low side, S3, S5 . . . and S4, S6 . . . should be triggered separately by the interleaved PWM signal to deliver power from high side to low side. However, if both sides are connected with voltage sources, the group of S1, S3, S5, . . . and the group of S2, S4, S6, . . . should be triggered by interleaved PWM signals, respectively. The duty cycle and frequency can be used to control the direction of charging current. B. Buck-Mode (Step-Down) TBSC To derive the buck version of nX TBSC, the diodes in nX TBSC topology are replaced by switches while the switches by diodes. The power source is connected at high side and the

WU et al.: FAMILY OF TWO-SWITCH BOOSTING SWITCHED-CAPACITOR CONVERTERS

Fig. 20.

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Fig. 21.

Bidirectional extension of TBSC.

Fig. 22.

Buck-mode TBSC.

Experimental result of ripple cancelation. (a) d = 0.25. (b) d = 0.45.

load is connected at low side. The result is shown in Fig. 22. Generally, in a buck-mode nX TBSC, the switches with odd number as subscript are triggered by the pulses labeled S1 , while the ones with even number as subscript, by the pulses labeled S2 . as shown in the two top curves in Fig. 7(d). VI. CONCLUSION A family of TBSC is proposed. The interleaved operation yields small output voltage ripple, reduced components, as well as low/uniform VS for all components. It is most suitable for unregulation applications (with a duty ratio of 0.5), when the efficiency is most favorable with nX gain. It can also be controlled by PWM strategy to regulate the output voltage to near but below nX, then the efficiency may be compromised. A modeling method for the proposed converter is given and this method reveals more parameter effects on voltage gain compared with previously reported method. Guidelines in designing a higher efficiency and high power density TBSC converter are also discussed A prototype of 1-kW TBSC converter with peak efficiency of 97.5% was built, under the input voltage of 150 V and switching frequency of 20 kHz. The output is nearly 450 V. The experimental results demonstrate regulation capability of proposed TBSC converter by adjusting duty cycle and/or frequency. Good efficiency and low output voltage ripple can be achieved by increasing the duty cycle and frequency.

By replacing all the diodes with active switches, the TBSC family can be extended to perform bidirectional power flow operation. Furthermore, if all the diodes are replaced by active switches, and vice versa, the TBSC family can be extended for step-down operation. REFERENCES [1] A. Ioinovici, “Switched-capacitor power electronics circuits,” IEEE Circuits Syst. Mag., vol. 1, no. 3, pp. 37–42, Jul.–Sep. 2001. [2] C.-K. Cheung, S.-C. Tan, C. K. Tse, and A. Ioinovici, “On energy efficiency of switched-capacitor converters,” IEEE Trans. Power Electron., vol. 28, no. 2, pp. 862–876, Feb. 2013. [3] K. D. T. Ngo and R. Webster, “Steady-state analysis and design of a switched-capacitor DC-DC converter,” IEEE Trans. Aerosp. Electron. Syst., vol. 30, no. 1, pp. 92–101, Jan. 1994.

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[4] R. Jain, B. M. Geuskens, S. T. Kim, M. M. Khellah, J. Kulkarni, J. W. Tschanz, and V. De, “A 0.45–1 V fully-integrated distributed switched capacitor DC-DC converter with high density MIM capacitor in 22 nm tri-gate CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 917–927, Apr. 2014. [5] M. D. Seeman, S. R. Sanders, and J. M. Rabaey, “An ultra-low-power power management IC for energy-scavenged wireless sensor nodes,” in Proc. IEEE Power Electron. Spec. Conf., Jun. 2008, pp. 925–931. [6] V. W. Ng, M. D. Seeman, and S. R. Sanders, “High-efficiency, 12V-to1.5V DC-DC converter realized with switched-capacitor architecture,” in Proc. VLSI Circuits Symp., 2009, pp. 168–169. [7] V. Ng and S. Sanders, “A 92%-efficiency wide-input-voltage-range switched-capacitor DC-DC converter,” in Proc. IEEE Int. Solid-State Circuits Conf., 2012, pp. 282–284. [8] T. M. Andersen, F. Krismer, J. W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, M. Brandli, P. Buchmann, and P. A. Francese, “A 4.6W/mm2 power density 86% efficiency on-chip switched capacitor DCDC converter in 32 nm SOI CMOS,” in Proc. 28th Annu. IEEE Appl. Power Electron. Conf. Expo., 2013, pp. 692–699. [9] T. Santa, M. Auer, C. Sandner, and C. Lindholm, “Switched capacitor DC-DC converter in 65nm CMOS technology with a peak efficiency of 97%,” in Proc. IEEE Int. Symp. Circuits Syst., 2011, pp. 1351–1354. [10] G. Zhu, H. Wei, I. Batarseh, and C. Florida, “A new switched-capacitor DC-DC converter with improved line and load regulations,” in Proc. IEEE Int. Symp. Circuits Syst., 1999, pp. 234–237. [11] G. Y. Zhu and A. Ioinovici, “Implementing IC based designs for 3.3V supplies,” IEEE Circuits Devices Mag., vol. 11, no. 5, pp. 27–29, Sep. 1995. [12] A. Ioinovici, “Step-up DC power supply based on a switched-capacitor circuit,” IEEE Trans. Ind. Electron., vol. 42, no. 1, pp. 90–97, Feb. 1995. [13] H. Chung, B. O, and A. Ioinovici, “Switched-capacitor-based DC-to-DC converter with improved input current waveform,” in Proc. IEEE Int. Symp. Circuits Syst. Connecting World, 1996, pp. 541–544. [14] S.-C. Tan, S. Kiratipongvoot, S. Bronstein, A. Ioinovici, Y. M. Lai, and C. K. Tse, “Adaptive mixed on-time and switching frequency control of a system of interleaved switched-capacitor converters,” IEEE Trans. Power Electron., vol. 26, no. 2, pp. 364–380, Feb. 2011. [15] M. Seeman, “A design methodology for switched-capacitor DC-DC converters,” Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Univ. California, Berkeley, CA, USA, 2009. [16] L. Chang, R. K. Montoye, B. L. Ji, A. J. Weger, K. G. Stawiasz, and R. H. Dennard, “A fully-integrated switched-capacitor 2ࢼ1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2 ,” in Proc. Symp. VLSI Circuits, 2010, pp. 55–56. [17] D. Maksimovic and S. Dhar, “Switched-capacitor DC-DC converters for low-power on-chip applications,” in Proc. 30th Annu. IEEE Power Electron. Spec. Conf. Rec., 1999, pp. 54–59. [18] S. V. Cheong, S. H. Chung, and A. Ioinovici, “Development of power electronics converters based on switched-capacitor circuits,” in Proc. IEEE Int. Symp. Circuits Syst., 1992, pp. 1907–1910. [19] F. Zhang, L. Du, F. Z. Peng, and Z. Qian, “A new design method for high-power high-efficiency switched-capacitor DC–DC converters,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 832–840, Mar. 2008. [20] F. Z. Peng, “A magnetic-less DC-DC converter for dual voltage automotive systems,” in Proc. Conf. Rec. IEEE Ind. Appl. Conf., 2002, pp. 1303–1310. [21] F. Z. Peng and L. M. Tolbert, “Development of a 55 kW 3X dc-dc converter for HEV systems,” in Proc. IEEE Veh. Power Propulsion Conf., 2009, pp. 433–439. [22] K. Zou, M. J. Scott, and J. Wang, “A switched-capacitor voltage tripler with automatic interleaving capability,” IEEE Trans. Power Electron., vol. 27, no. 6, pp. 2857–2868, Jun. 2012. [23] W. Chen, A. Q. Huang, C. Li, G. Wang, and W. Gu, “Analysis and comparison of medium voltage high power DC/DC converters for offshore wind energy systems,” IEEE Trans. Power Electron., vol. 28, no. 4, pp. 2014–2023, Apr. 2013. [24] M. Shen, F. Z. Peng, and L. M. Tolbert, “Multilevel DC–DC power conversion system with multiple DC sources,” IEEE Trans. Power Electron., vol. 23, no. 1, pp. 420–426, Jan. 2008. [25] J. M. Henry and J. W. Kimball, “Practical performance analysis of complex switched-capacitor converters,” IEEE Trans. Power Electron., vol. 26, no. 1, pp. 127–136, Jan. 2011. [26] A. Lopez, R. Diez, G. Perilla, and D. Patino, “Analysis and comparison of three topologies of the ladder multilevel DC/DC converter,” IEEE Trans. Power Electron., vol. 27, no. 7, pp. 3119–3127, Jul. 2012.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 10, OCTOBER 2015

[27] A. Ioinovici, “Development of boost converter based on switchedcapacitor circuits,” in Proc. IEEE Int. Conf. Comput., Commun. Autom., 1993, pp. 522–525. [28] A. Ioinovici, “DC-to-DC converter with no magnetic elements and enhanced regulation,” IEEE Trans. Aerosp. Electron. Syst., vol. 33, no. 2, pp. 499–506, Apr. 1997. Bin Wu (S’14) was born in Zhejiang, China, in 1985. He received the B.S degree in electrical engineering from Zhejiang University, Hangzhou, China, in 2008, and the M.S. degree in power electronics from Xi’an Jiao Tong University, Xi’an, China, in 2011. He is currently working toward the Ph.D. degree in power electronics at the University of California, Irvine, CA, USA. His research interests include switched capacitor converter, modeling, high gain dc–dc converter, electrical vehicle and renewable energy integration. Shouxiang Li (S’14) received the B.S. degree in electrical engineering and automation from the Beijing Institute of Technology, Beijing, China, in 2011, and the M.S. degree in electrical engineering from the University of California, Irvine, CA, USA, in 2013. He is currently working toward the Ph.D. degree at the University of California, conducting his studies both in the Calit2 and the UCI Power Electronics Laboratory. From 2012–2013, he was an Intern in the PMU Group, Broadcom Corporation, Irvine. From 2013– 2014, he was a Research Assistant in the UCI Power Electronics Laboratory. His research interests include switched capacitor converters, high-gain dc–dc converters. Keyue Ma Smedley (S’87–M’90–SM’97–F’08) received the B.S. and M.S. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 1982 and 1985, respectively, and the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, CA, USA, in 1987 and 1991, respectively. She is currently a Professor in the Department of Electrical Engineering and Computer Science, University of California, Irvine, CA, USA, the Director of the UCI Power Electronics Laboratory, and a Cofounder of One-Cycle Control, Inc. Her research interests include high-efficiency dc–dc converters, high-fidelity class-D power amplifiers, single-phase and three-phase PFC rectifiers, active power filters, inverters, V/VAR control, energy storage system, and utility-scale fault current limiters. She is an Inventor of One-Cycle Control and the hexagram power converter. Her work has resulted in more than 160 technical publications, more than ten U.S./international patents, two start-up companies, and numerous commercial applications. Dr. Smedley is a Recipient of the UCI Innovation Award in 2005. Her work with One-Cycle Control, Inc., has won her the Department of the Army Achievement Award in the Pentagon in 2010. Sigmond Singer (M’80) received the B.Sc. and D.Sc. degrees from the Technion, Haifa, Israel, in 1967 and 1973, respectively. In 1978, he joined the Staff of the Faculty of Engineering, Tel Aviv University, Tel Aviv, Israel, where he is currently a Professor. Since 2000, he has been the Department Head of Interdisciplinary Studies. His research interests include general circuits and systems theory, power electronics and energy conversion. Dr. Singer was awarded the Best Paper of the Year Award in 1990 by the IEEE Circuits and Systems Society for the paper “Realization of Loss Free Resistive Elements.” He has been the Chairman of the Israeli Chapter of the IEEE since 2005.