A FIVE-LEVEL NPC BIDIRECTIONAL CONVERTER BASED ON MULTISTATE SWITCHING CELL OPERATING AS BOOST RECTIFIER João A. Ferreira Neto; Francisco J. B. Brito Jr.; Davi R. Joca; Marcos A. N. Nunes; René P. TorricoBascopé Energy Processing and Control Group – GPEC Electrical Engineering Department – DEE Federal University of Ceará – UFC Fortaleza-CE, Brazil
[email protected], {britojr, davijoca, marcos.nunes, rene}@dee.ufc.br Abstract – This paper presents a five-level NeutralPoint-Clamped (NPC) bidirectional converter based on multi-state switching cell (MSSC) operating as boost rectifier for power factor correction applications. Its main features are high power factor, reduced conduction losses, reduced weight and volume, and a bidirectional power flow between the ac and dc sides of the converter. The analysis employs the principle of interleaved converters, as it can be extended to a generic number of legs and high power levels. A theoretical analysis and experimental results from a 3 kW prototype are presented.
In this paper is presented the single-phase five-level NPCMSSC bidirectional converter operating as a boost rectifier with power factor correction as is shown in Figure 1. This way, the main purpose of this work is to verify the operation of the topology in rectifier mode, especially regarding to the power factor correction and efficiency.
Keywords – Bidirectional Converters, Interleaved Converters, Multi-State Switching Cell, Power Factor Correction. I. INTRODUCTION Several applications require a bidirectional power flow between the AC and DC sides, such as in Solid-State Transformers (SST) stages, electrical motors drives, Smart Grids (SG), AC and DC distributed power systems, electric vehicles chargers, electronics loads, and regenerative activepower compensators. Moreover, stringent limits are being established in order to control the current harmonics injected by power converters in the AC mains, and high power factor [1-5]. For high input voltages grids the Neutral-Point-Clamped (NPC) multilevel converters and floating capacitor converters are used to divide voltages on the semiconductors switches such as were studied in [6,7]. The Multi-State Switching Cell (MSSC) enables good current sharing between the semiconductors devices, reduced weight and volume of magnetic elements, and reduced switching and conduction losses [8,9]. This technique, which allows the parallel connection of switches, provides a power increase to be processed by the converter, becoming attractive for medium power applications [10]. The five-level NPC topology based on MSSC operating as inverter was presented in [11]. This converter allows a bidirectional power flow, i.e., can be suited for applications where power is fed back to the power supply. In [12] was presented a comparative analysis between the five-level NPC-MSSC converter and two similar topologies, the three-level classic NPC and the five-level interleaved NPC converters.
Fig. 1. Proposed single-phase five-level NPC-MSSC bidirectional converter operating as boost rectifier.
II. OPERATION OF THE NPC-MSSC BOOST RECTIFIER A. Circuit Description The single-phase five-level NPC-MSSC bidirectional converter operating as boost rectifier consists of one inductor (Lb), one autotransformer with two windings (N1 and N2), eight controlled switches (S1-S8), four clamping diodes (Dc1Dc4), and two capacitors (Co1 and Co2). The converter operates only in continuous conduction mode (CCM). The main switches S3 and S7 control the power drained of source during the positive half-cycle of the input voltage. The switches S1 and S5 are complementary to the main switches S3 and S7, respectively. Analogously, S2 and S6 are the main switches that control the power drained during the negative half-cycle of the input voltage, and the switches S4 and S8 are complementary to the main switches S2 and S6, respectively. B. Operation Modes The modulation strategy used for rectifier mode is identical to that adopted for the inverter [11]. In this strategy there are two modes of operation for each half-cycle of the input voltage, as seen in Figure 2. The operation modes are defined by the comparison between the input voltage and the output voltage. When the absolute value of the input voltage is less than a fourth one of
the output voltage, the converter operates in overlapping mode (OM). In this mode the duty cycle of the main switches is greater than 0.5. When the input voltage is greater than a fourth one of the output voltage, the converter operates in non-overlapping mode (NOM). In this mode the duty cycle of the main switches is less than 0.5.
Fig. 3. First stage for Overlapping Mode.
Fig. 2. Operation modes during one-cycle of the input voltage.
C. Operation Stages The operation stages of the bidirectional single-phase NPC-MSSC PWM rectifier for overlapping and nonoverlapping operation modes are described below. During the positive half cycle of the input voltage, the switches S2 and S6 are always on. 1) Overlapping Mode on positive half cycle First stage: When the switches S3 and S7 are turn-on, half the input current flows through the winding N1, the switch S3, and the diode Dc2, while the other half flows through the winding N2, the switch S7, and the diode Dc4. During this operation stage, shown in Figure 3, the power supplied by the voltage source V1(t) is stored in the boost inductor Lb, which its current increases in module and no energy is transferred to the load. Second stage: When the switch S3 is blocked, half the input current flows through the winding N1 and the intrinsic diodes of the switches S1 and S2, while the other half flows through the winding N2, the switch S7, and the diode Dc4. During this operation stage, shown in Figure 4, the voltage VAO is equal to Vo/4 which is higher than the value of the input voltage V1(t). Thus, the voltage polarity across the boost inductor is inverted and its current is decreased in module, with power transfer to the load from the source V1(t) as the part of the energy stored in the boost inductor. Third stage: This stage is similar to first stage for Overlapping Mode. Fourth stage: When the switch S7 is blocked, half the input current flows through the winding N2 and the intrinsic diodes of the switches S5 and S6, while the other half flows through the winding N1, the switch S3, and the diode Dc2. During this operation stage, shown in Figure 5, the voltage VAO is equal to Vo/4 which is higher than the value of the input voltage V1(t). Thus, the polarity of the voltage across the boost inductor is inverted and its current is decreased in module, with power transfer to the load from the source V1(t) as the part of the energy stored in the boost inductor. The main waveforms for overlapping operation mode of the converter are shown in Figure 6.
Fig. 4. Second stage for Overlapping Mode.
Fig. 5. Fourth stage for Overlapping Mode.
Fig. 6. Main waveforms for Overlapping Mode.
2) Non-Overlapping Mode on positive half cycle First stage: When the switch S3 is turn-off and the switch S7 is turn-on, half the input current flows through the winding N1 and the intrinsic diodes of the switches S1 and S2, while the other half flows through the winding N2, the switch S7, and the diode Dc4. During this operation stage, shown in Figure 7, the voltage VAO is equal to Vo/4 which is lower than the value of the input voltage V1(t). Thus, the polarity of the voltage across the boost inductor is positive and its current increases in module. A part of the energy supplied by the power source V1(t) is stored in the boost inductor Lb, while the other part is transferred to the load. Second stage: When the switches S3 and S7 are turn-off, half the input current flows through the winding N1 and the intrinsic diodes of the switches S1 and S2, while another half flows through the winding N2 and the intrinsic diodes of the switches S5 and S6. During this operation stage, shown in Figure 8, the voltage VAO is equal to Vo/2 which is higher than the value of the input voltage V1(t). Thus, the polarity of the voltage across the boost inductor is inverted and its current decreases in module, with power transfer to the load from the source V1(t) and part of the energy stored in the boost inductor. Third stage: When the switch S7 is turn-off and the switch S3 is turn-on, half the input current flows through the winding N2 and the intrinsic diodes of the switches S5 and S6, while the other half flows through the winding N1, the switch S3, and the diode Dc2. During this operation stage, shown in Figure 9, the voltage VAO is equal to Vo/4, which is lower than the value of the input voltage V1(t). Thus, the polarity of the voltage across the boost inductor is positive and its current increases in module. A part of the energy supplied by the power source V1(t) is stored in the boost inductor Lb, while the other part is transferred to the load. Fourth stage: This stage is similar to the second stage for NOM, as the same circuit equivalent and operating conditions are valid in this case. The main waveforms for non-overlapping operation mode of the converter are shown in Figure 10.
Fig. 8. Second stage for Non-Overlapping Mode.
Fig. 9. Third stage for Non-Overlapping Mode.
Fig. 10. Main waveforms for Non-Overlapping Mode.
Fig. 7. First stage for Non-Overlapping Mode.
D. Control Strategy Unlike the inverter mode, the control strategy used to correct the power factor and regulate the output voltage of the converter, operating as rectifier, is the technique of selfcontrol [13], which uses optimally the characteristics of the pulse width modulation (PWM) rectifiers. In this strategy, represented in Figure 11, a sample of the input current is used to generate the command pulses of the rectifier switches.
⎛α ⎞ θ 1 = sin −1 ⎜ ⎟ = 37.95 o
P S1
S5
Autotransformer
Dc1
+ V(t) 1 -
IL(t)
Dc3
+
Sample
Ro Vo
V’ o -
S6
S2 Lb
⎝4⎠
Co1
N1
A
O
N2
S3
Dc2
S7
Dc4
++
Co2
S4
Vo_REF
S8
Current Sensor
The output current is:
Io =
+
Voltage Compensator
Sample Gain Coplementary PWM Signal
X
+ Vtri1
S1
-
Lb =
0
PWM Signal
S3
0
PWM Signal
0
Vtri2
S2
-
0
Coplementary PWM Signal
0
S4 0
Coplementary PWM Signal
+ Vtri5
S5
-
0
PWM Signal
S7
0
0
PWM Signal
+ 0
Vtri6
S6
-
0
S8 PWM Comparator
Coplementary PWM Signal
0
Fig. 11. Self-control technique applied to the five-level NPCMSSC boost rectifier.
In the control strategy presented in Figure 11, the main switches S3 and S7 are commanded by a PWM signal and the switches S1 and S5 are commanded by a complementary PWM signal in the positive half-cycle of the input voltage. Analogously, the main switches S2 and S6 are commanded by a PWM signal and the switches S4 and S8 are commanded by a complementary PWM signal in the negative half-cycle of the input voltage. III. DESIGN PROCEDURE A. Design Specifications The design specifications of the bidirectional NPC-MSSC rectifier are listed in Table 1 and were used in the implementation of the experimental prototype. TABLE I Design specifications Parameter Rms value of the rated input voltage Grid frequency Input current ripple (10% of the input current) Switching frequency Rated output power Output voltage Output voltage ripple Expected theoretical efficiency
Value Vi = 115 V f = 60 Hz ΔILb = 3.84 A fsw = 20 kHz Po = 3 kW Vo = 400 V ΔVo = 10 V η = 96%
400 = 2.46 2 .115
Vo = 163 μH 32 ⋅ ΔI Lb ⋅ f sw
(4)
D. Autotransformer The maximum voltage across the windings is: V (7) VN 1 = o = 100 V 4 The rms and peak currents through the windings of the autotransformer are given by (8) and (9), respectively. 2 ⋅α ⋅ Io 2 ⋅ 2.46 ⋅ 7.5 (8) = = 13.6 A I N 1 _ rms = 2 ⋅η 2 ⋅ 0.96
I N 1 _ pk =
α ⋅ I o 2.46 ⋅ 7.5 = = 19.22 A 0.96 η
(9)
E. Main Switches The threshold voltage across one main switch is: V (10) VS 3 = o = 200 V 2 The average current, the rms current, and the peak current through the main switch are given by (11), (12), and (13), respectively. (2 ⋅ α − π ) ⋅ I o = (2 ⋅ 2.46 − π ) ⋅7.5 = 2.21 A (11) I S 3 _ avg = 2 ⋅ π ⋅η 2 ⋅ π ⋅ 0.96
Io α ⋅ (3 ⋅ π ⋅ α − 16 ) (12) ⋅ = 5.35 A 2 ⋅η 3 ⋅π α ⋅ I o 2.46 ⋅ 7.5 (13) I S 3 _ pk = = = 19.22 A η 0.96 The clamping diodes have the same voltage and current values that the main switches. I S 3 _ rms =
B. Preliminary Calculation Parameter α is the ratio between the output voltage and the peak input voltage and calculated as:
α=
(3)
To the project is adopted Lb = 180 µH. The rms and peak currents through the boost inductor are given by (5) and (6), respectively. 2 ⋅α ⋅ I o 2 ⋅ 2.46 ⋅ 7.5 (5) I Lb _ rms = = = 27.18 A η 0.96 2 ⋅ α ⋅ I o 2 ⋅ 2.46 ⋅ 7.5 (6) I Lb _ pk = = = 38 .44 A 0.96 η
0
+ Vref
Po 3000 = = 7.5 A Vo 400
C. Boost Inductor The boost inductance is given by:
N
KSamp
(2)
(1)
The angle that represents the transition between the overlapping and non-overlapping modes is:
F. Antiparallel Diodes The reverse voltage across one antiparallel diode is: V (14) VR _ AD = o = 200 V 2 The average current, the rms current, and the peak current through the antiparallel diode are given by (15), (16), and (17), respectively.
I AD _ avg =
Io 7.5 = = 3.9 A 2 ⋅η 2 ⋅ 0.96
(15)
I AD _ rms =
2 ⋅ Io
η
I AD _ pk =
⋅
α 2 ⋅ 7.5 2.46 = ⋅ = 7.98 A (16) 3 ⋅π 0.96 3 ⋅π
α ⋅ I o 2.46 ⋅7.5 = = 19.22 A 0.96 η
(17)
G. Filter Capacitors The capacitance value of Co1 and Co2 is defined by (18): Po 3000 (18) C ≥ = = 2 mF o
2 ⋅ π ⋅ f ⋅ Vo ⋅ ΔV o
2 ⋅ π ⋅ 60 ⋅ 400 ⋅ 10
The power stage elements are presented in Table II. TABLE II Power stage elements Parameter Boost inductor Autotransformer Switches S1 – S8 Diodes Dc1 – Dc4 Filter capacitors Load resistance
Value Lb = 180 µH NEE – 65/33/52 (Thornton - IP12) NL = 15 turns (80 x 26AWG) NEE – 65/33/52 (Thornton – IP12) N1 = N2 = 12 turns (40 x 26AWG) IRGP50B60PD1 30EPH06 Co1 = Co2 = 2.72 mF (4 x 680 µF/400 V) Ro = 53.33 Ω
(b) Po = 3 kW. Fig. 12. Input voltage (CH1) and input current (CH2) waveforms.
IV. EXPERIMENTAL RESULTS A laboratory prototype was implemented according to the parameters listed in Table I and to the components specified in Table II. Figure 12 shows the input voltage and input current waveforms for two values of the output power where the power factor correction can be observed. In Figure 13 are shown the harmonics spectra of the input voltage and input current for rated output power with their respective values of total harmonic distortion (THD). With the value of THD of the input current equal to 3.7% and the fundamental component lag angle equal to 3.9 degrees, the power factor is equal to 0.997. A curve with the power factor as function of output power is presented in Figure 14.
(a) Input voltage.
(b) Input current. Fig. 13. Harmonics spectra (Po = 3 kW).
(a) Po = 2 kW.
A detailed view of the total input current and the current through the winding N1 of the autotransformer is shown in Figure 15, in which it can be noted that the current ripple in each winding is half of the total input current ripple. The efficiency curve, obtained experimentally, for the five-level NPC-MSSC bidirectional converter operating as boost rectifier is presented in Figure 16, depending on the output power. It is found that the efficiency of the converter is approximately 95% for rated output power.
A design example was performed in which the main components of the converter have been sized. The control strategy used to correct the power factor and regulate the output voltage was the technique of self-control, which uses optimally the characteristics of the PWM rectifiers. Experimental results from a 3 kW prototype implemented in laboratory proved the power factor correction and a good efficiency of the topology.
Power factor (%)
99,9 99,7 99,5 99,3 99,1 98,9 98,7
REFERENCES
98,5 0,999
1,31
2,09 2,46 Output power (kW)
3,02
3,12
Fig. 14. Power factor curve as function of the output power.
Fig. 15. Detailed view of the total input current (CH3) and the current through the winding N1 (CH4) (ωt = π/2).
Fig. 16. Efficiency curve as function of the output power.
V. CONCLUSION This work presented the five-level Neutral-Point-Clamped (NPC) bidirectional converter based on Multi-State Switching Cell (MSSC) operating as a boost rectifier. Its main features are high power factor, reduced conduction losses, reduced weight and volume, and a bidirectional power flow between the ac and dc sides of the converter. The operation modes of the converter have been demonstrated in accordance with the duty cycle of the main switches. The operation stages have also been shown employing the principle of interleaved converters.
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