Vol. 34, No. 7
Journal of Semiconductors
July 2013
A fully integrated 3.5 GHz CMOS differential power amplifier driver Xu Xiaodong(许晓冬)1; 2 , Yang Haigang(杨海钢)1; , Gao Tongqiang(高同强)1 , and Zhang Hongfeng(张洪锋)1; 2 1 Institute
of Electronics, Chinese Academy of Sciences, Beijing 100190, China of Chinese Academy of Sciences, Beijing 100039, China
2 University
Abstract: A fully integrated CMOS differential power amplifier driver (PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements, a transmission line transformer is used as the output matching network. A differential inductance constitutes an inter-stage matching network. Meanwhile, an on chip balun realizes input matching as well as single-end to differential conversion. The PAD is fabricated in a 0.13 m RFCMOS process. The chip size is 1.1 1.1 mm2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB. Key words: CMOS PA; power amplifier driver; transformer; balun; WiMAX DOI: 10.1088/1674-4926/34/7/075006 EEACC: 1270E; 2570D
1. Introduction In recent years, fourth generation cellular standards (4G) have been developed as a promising candidate to provide high quality communication serves. World Interoperability for Microwave Access (WiMAX) as one of such standards adopts orthogonal frequency-division multiple-access (OFDMA) to enhance spectral efficiency. It has two frequency bands covering from 2.5 to 3.5 GHz. Nevertheless the employment of advanced modulation technology poses stringent requirements to PA designŒ1 . First, a higher output power is needed. Second, the complex modulation induces a high peak to average power ratio (PAPR) which in return requires a high linearity of PA. Last but not least, average efficiency improvement is difficult due to a relatively high power back off situation. With continuous scaling down of CMOS process nodes, more and more RF building blocks have been integrated on CMOS chipsŒ2; 3 . However, as the most power hungry component, PA and PAD are always prone to be employed with other mature technologies such as GaAs or SiGe. On one hand, reduction of supply voltage and breakdown voltage with a CMOS process makes high power generation a great challenge. On the other hand, the loss of CMOS substrate and the parasitic resistances of metal traces cause substantial loss both on passive and active devices. Although there exist some disadvantages of fabricating PA and PAD in a CMOS process, low cost and possibility of integration with analog and digital blocks make the CMOS process still a reasonable option for PA fabrication. Several efforts have been done to implement CMOS PA and PAD to fulfill WiMAX requirements. In Ref. [4] a single stage 90 nm CMOS PA integrated with a balun is reported having 18 dB gain and 32 dBm saturated power (Psat /. Furthermore, digital pre-distortion technology is used to enhance PA linearity. In Ref. [5], a two-stage transformer-based PA in
90 nm CMOS is designed with Psat of about 30.1 dBm and power gain of 28 dB. In this paper, a fully differential 3.5 GHz CMOS PAD with a transformer as the output matching network is presented. The design procedure of the two-stage CMOS PAD is described. The analysis of operating principle for the transformer is also given.
2. The architecture of PAD In this section general design considerations for the twostage CMOS PAD are presented. The complete topology of the proposed PAD is shown in Fig. 1. The pseudo-differential structure is adopted in both output stage and driver stage. It has several advantages in comparison with a single-ended structure. First, the output voltage swing can be doubled resulting in 6 dB improvement in output power, assuming the same output load. Second, a differential structure can suppress even order distortion effectively if symmetry of structure is well maintained. Last, it can reject common mode interference and noise well. When delivering saturated output power, output voltage swing may exceed five volts. Then a cascode structure is adopted, using thick gate transistor M7 and M8. Meanwhile a self-biased technologyŒ6 is taken to further improve reliability by avoiding breakdown issues. The driver stage is simply a common source configuration due to relatively low voltage swing and the need for high power gain. The driver-stage plays two roles. On one hand, it provides sufficient driving power to the output stage. On the other hand, it provides impedance matching to the input signal source. A differential inductance Ldiff , DC blocking capacitance Cb and parasitic capacitances form an inter-stage matching network to ensure maximum power transfer efficiency. It should be mentioned that transistor M3, M4 and M9 as well as an inverter constitute an effective
* Project supported by the National Natural Science Foundation of China (No. 61106025) and the National High Technology Research and Develop Program of China (No. 2012AA012301). † Corresponding author. Email:
[email protected] Received 19 December 2012, revised manuscript received 11 January 2013 © 2013 Chinese Institute of Electronics
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Fig. 2. Simplified model of a 1 : n transformer.
Eq. (1), where Qp and Qs are quality factors. Rp D
!Lp ; Qp
Rs D
!Ls : Qs
(1)
From Fig. 2, the efficiency of transformer can be written as D
Fig. 1. Fully schematic of the PAD circuit.
way to control the operation model of PAD. When Vctrl is connected to low voltage transistor M3 and M4 are shut down, the bias voltage of driver stage goes through transistor M9 which is turned on by high output voltage of inverter. On the other side, transistors M3 and M4 turn on with high voltage of Vctrl and pull down the gate voltage of M5 and M6 meanwhile transistor M9 is shut down to cut off the path through which the bias voltage of driver stage goes. The PAD can be shut down completely with this method and save power consumption in some circumstances. One big issue about PAD is its stability issue. In order to maintain stability over the whole operating frequency, a bypass RC networkŒ7 is adopted instead of a huge capacitance connected in series with resistance which may increase even mode impedance causing large voltage fluctuation at supply node.
3.1. Output matching network In this design, the transmission line transformer is utilized to perform output matching. The principle of the transformer used as the output matching network has been elaborated in Ref. [8]. Figure 2 shows a practical model of the transformer, where Rp and Rs are parasitic resistances of Lp and Ls due to limited quality factor. RL and CL represent resistive and capacitive loading effect. Parasitic resistances are expressed in
(2)
1 2 RL 1 1 C .!RL CL /2 ; D ˇ ˇ2 n ˇ Zs C j!kLp ˇ 1 ˇ ˇ RL C Rs C ˇ Rp 1 C .!Rp CL /2 j!kLp ˇ (3) where Zs is the secondary side impedance transformed to the primary side, as shown below.
Zs D
Rs C j!.1
k/Ls C
1 C RL j!CL
: (4) n2 It can be shown in Eq. (3) that efficiency of the transformer is a function of quality factor and inductance value of the primary and secondary inductances as well as capacitive load CL . Apparently for a certain turn ratio, there exist some optimum values for Lp , CL in terms of maximum efficiency and max D
3. Impedance matching network The most significant part of the CMOS PAD is the impedance matching network. In the output stage, the impedance matching network should be designed according to load-line theory due to the large non-linear behavior of the output transistor. In an inter-stage matching network, conjugate matching theory is taken because of the relatively small signal at the driver-stage output. In this section, a detailed description about these matching networks is presented.
Pload ; Pload C Pdiss
s
2 1C C2 Qp Qs k 2
1 1 Qp Qs k 2
1 1C Qp Qs k 2
:
(5) The relationship between efficiency and Lp , CL is shown in Fig. 3. Here we have assumed the turn ratio of transformer is 1 : 1, k equals to 0.8 and the quality factor of inductance is 10 which are reasonable for on chip inductance at GHz. From simulation results the optimum value of Lp is around 3 nH, CL is about 1 pF. The maximum efficiency of transformer is 80%. In addition if quality factor of on chip inductance can be improved by some special methods such as pattern shieldingŒ9 or silicon on insulator technology, the maximum can reach above 90%. Another characteristic of transformer is impedance conversion. From Fig. 2, Zin can be expressed as
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RL ; 1 C .RL !CL /2 1 CL0 D CL 1 C ; .RL !CL /2 RL0 D
(6)
(7)
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Fig. 3. The relationship between efficiency and Lp , CL of the transformer at 3.5 GHz.
Fig. 5. The relationship between E and Lp , CL of the transformer at 3.5 GHz.
Fig. 4. The relationship between Real(Zin ) and Lp , CL of the transformer at 3.5 GHz.
Fig. 6. The layout of 1 : 1 transformer.
AD
j!.1 k/Ls 1 !Ls RL0 C C C ; n2 n2 j!n2 CL0 Qs
Zin D
!Lp C j!.1 Qp
k/Lp C
j!Lp A : j!Lp C A
(8)
(9)
Equation (9) shows that Zin is also a function of Lp and CL , the relationship between Zin and Lp , CL is plotted in Fig. 4. In Ref. [10] the author proposed a parameter E which describes the ratio of RF power delivered to the conversion load Ptrans to power delivered to the original load for the same sinusoidal input voltage source and is called the power enhancement ratio. ED
50 Ptrans D r D : Pdirect real.Zin /
(10)
By using Eq. (10), the ability of power enhancement of the transformer can be evaluated. Figure 5 shows the results of E for 1 : 1 transformer. The maximum value of E can reach above 4 with Lp of 0.1 nH and CL of 0.3 pF. However, due to the lossy substrate of the CMOS process, the quality factor with a 0.1 nH inductance is very low and the maximum value of E can never be above 4. In this design the value of E is approach to 1.5 with Lp of 3 nH and CL of 300 fF.
Fig. 7. The simulation result of insertion loss.
According to the discussion above, a transmission line transformer is designed. The layout of transformerŒ11; 12 is shown in Fig. 6. The stack structure is adopted to increase coupling factor. The primary inductance is implemented with top metal and secondary inductance with metal 7 in 1P8M process. The width of the metal trace is set to 50 m to enhance current capability. ADS momentumŒ13 is used to simulate the insertion loss of this transformer and the result is shown in Fig. 7, it can be seen that the insertion loss is less than –1.35 dB after carefully selecting tune capacitances.
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Fig. 9. Chip microphotograph of the PAD. Fig. 8. The layout of differential inductance Ldiff .
3.2. Inter-stage matching network For inter-stage matching, a differential inductance is used. The layout is shown in Fig. 8. The adoption of differential inductance has several merits. First, its symmetric layout ensures lower even order distortion. Second, the center-tap of inductance can be treated as virtual ground so the biasing voltage can be added through this tap, simplifying the biasing network. Third, the area is much smaller than single-ended inductance at the same value. A top thick metal is used in the lateral structure to form inductance to improve quality factor. The simulation results show that this inductance has value about 1.35 nH and quality factor is above 10.
Fig. 10. Measured S parameter of the PAD.
4. Measurement results The PAD is fully implemented in an RF 0.13 m one-poly eight-metal (1P8M) CMOS process with a supply voltage of 2.5 V. The thick metal can increase the quality factor of a passive device dramatically. The chip microphotograph is shown in Fig. 9. The total area including pad is about 1.1 1.1 mm2 ; all of the matching network is integrated on chip. The small signal measurement is shown in Fig. 10, it can be seen that the peak of S21 is around 12 dB at 3.5 GHz. By tuning varactors at output matching network, the peak of S21 is around 3.5 GHz and shows good agreement with frequency selectivity. The input and output matching are better than –10 dB and –11 dB, respectively. Figure 11 shows large signal measurement with continuous wave at 3.5 GHz. The 1 dB output compression point is about 9 dBm and saturation power is above 11 dBm. The P1dB can be varied by about ˙1 dB through adjusting gate biasing voltage of output transistor. The power gain keeps flat till to compression point. The linearity of PAD is measured by two tones at 3.495 GHz, 3.505 GHz, respectively. The spectrum is shown in Fig. 12. The output interception point is about 14 dBm being calculated by
Fig. 11. Large signal measurement of PAD.
Pout;1d
Pout;IM3
C Pout;IM3 ; (11) 2 where Pout;1d is output power of fundamental tone, and Pout;IM3 is output power of inter-modulation tone. Nevertheless, asymmetry is observed and the discrepancy between two intermodulation tones is on the order of decibel. This can be ex-
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OIP3 D
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Xu Xiaodong et al. Table 1. Summary of comparison between this work and others.
Parameter Technology (m) Frequency (GHz) Supply voltage (V) Power gain (dB) OP @ 1 dB (dBm) PAE @ P1dB (%) On chip balun Fully integration Size (mm2 /
ASSCC06Œ15 0.18 2.4 1.8 9.2 7.8 — No No 0.348
MWCL09Œ16 0.18 2.5 1.8 11.8 5.5 21 No No —
JOSŒ17 0.13 1.95 3.3 13.2 12.7 13.6 Yes No 1.02
This work 0.13 3.5 2.5 12 10 22 Yes Yes 1.21
* Simulation result
5. Conclusion In this paper a fully integrated CMOS power amplifier driver is implemented in a 0.13 m RFCMOS process. A transmission line transformer is fabricated. The performance of the PAD is measured and P1dB is around 10 dBm. The OIP3 is also 14 dBm. The feasibility of the transformer based output matching network is proved effectively.
References Fig. 12. Two tones measurement of the PAD.
plained by AM-PM distortion，which is even worse when the transformer is not symmetric. From Ref. [14], the magnitude of upper IM3 and lower IM3 sidebands are:
IM3USB D
IM3LSB D
a
a1 ' sin cos !3U 2 4 a ' a3 1 C cos sin 3 sin !3U ; 4 2 3
a
cos 3 C
a1 ' sin cos !3L 2 4 a ' a3 1 cos C sin 3 sin !3L ; C 4 2 3
(12)
cos 3
(13)
where D !1 2 !2 is beat frequency of two tones and ' is phase shift between AM-AM and AM-PM distortion. Table 1 summarizes the comparison of measured performance of this work with other similar CMOS PADs. The work has comparable performance in terms of power gain, output 1 dB compression power and chip size with the supply voltage of 2.5 V. Meanwhile all matching network are integrated on chip without external components, which reduce complexity of test circuits in printed circuit board. The simulation results show that PAE of this work is around 22% at P1dB . However the measured PAE is lower than simulation due to the FIB process used to repair a layout error. The parasitic resistance of the FIB process can reduce PAE evidently. Nevertheless, the measurement results show that the transformer can be used as the output matching network with state of the art CMOS processes.
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