A Highly-Efficient BiCMOS Cascode Class-E Power Amplifier Using Both Envelope-Tracking and Transistor Resizing for LTELike Applications Yan Li, Ruili Wu, Jerry Lopez and Donald Y.C. Lie Dept of Electrical and Computer Engineering, Texas Tech University, Lubbock, TX, 79409, USA Abstract — This paper presents the design of a SiGe differential cascode power amplifier (PA) to perform the envelope-tracking (ET) along with transistor resizing for efficiency enhancement for the 16QAM LTE. A new parallel-circuit class-E PA model is developed to analyze and design the cascode PA. The analytic results are compared with SPICE simulation and measurement data to provide circuit design insights. Measurement shows the ET-based PA system reaches an overall power-addedefficiency (PAE) of 38% at its 1 dB compression point (P1dB) of 22 dBm for its high power mode. Additionally, at the low power mode, some of the transistor cells can be disabled by the integrated MOSFET switches, and the overall PAE is improved by 4-5% at ≥4 dB back-off from its P1dB. This ET-based cascode PA satisfies the LTE 16QAM linearity specs without needing predistortions. Index Terms — SiGe BiCMOS power amplifier (PA), envelope-tracking (ET), LTE, parallel-circuit class-E PA model, transistor resizing.

I. INTRODUCTION Broadband 3G/4G/WLAN wireless signals utilize highly spectral-efficient modulation schemes with inherent non-constant-envelope waveforms and high peak-to-average-ratios (PARs). Therefore, highly linear PAs with excellent PAE at their peak power levels are required. Furthermore, efficiency improvements at the low average power levels (i.e., the low-power mode) are desired to extend the battery lifetime of mobile devices, because the average power efficiency of the PA is dominated by a probability distribution function where most RF power transmission is concentrated at much lower power levels than the peak Pout. It is, therefore, critical to maximize the PAE at both peak average POUT and low average POUT regions while keeping the PA linear for these broadband wireless communications. To simultaneously satisfy these design considerations for monolithic RF PAs, several approaches have been proposed such as device size switching, parallel amplification, switchable power combiner, etc. [1]-[3]. In this work, we will apply the combination of the envelope-tracking (ET) technique and the transistor resizing method to a fully-monolithic

978-1-61284-166-3/11/$26.00 ©2011 IEEE

Fig. 1. The parallel-circuit class-E PA model developed for cascode PA design.

cascode SiGe RF PA. For low power mode operation, some power transistor cells will be disabled. The ET technique can successfully enhance the PA efficiency by supply modulation and help keeping it linear at its compression region [4]. Meanwhile, the transistor resizing method enhances the PA efficiency at its backoff region. The Long-Term-Evolution (LTE) 16QAM 5 MHz signal having a PAR of ~7.5 dB will be used to evaluate our ET-based PA design. The cascode configuration is adopted here to relieve the voltage stress on the power transistors. However, the power loss introduced by the common-base (CB) transistor needs to be minimized and design trade-offs studied. In this work, we will first use a newly developed parallelcircuit class-E PA model to aid our transistor size selection. This PA model considers the finite choke inductance and the on-resistance of the CB transistor. II. CASCODE POWER AMPLIFIER DESIGN A. Analysis of the Cascode PA Design In our cascode PA design, a high-fT low-BVCEO bipolar device is utilized as the common-emitter (CE) stage and a high-BVCEO low-fT bipolar device is used as the CB stage. The parallel-circuit class-E PA model was previously reported in [3] for CE PAs, considering a finite choke inductance L; however, we have extended and modified it to cover our cascode PA design. Fig. 1 shows our modified parallel-circuit class-E PA model. For model simplification, the CE transistor used here is

The next step is to theoretically determine the power loss at the CB transistor, where the current flowing through ron (i.e., Is in Fig. 1) needs to be obtained. Applying the KCL at the “VC” node in Fig. 1, two 2ndorder ordinary differential equations regarding to IL can be expressed by (1). Here, the load current IR is assumed as IR=I·sin(θ+φ).

Collector Efficiency (%)

50 Measurement

45

Sim. w/ R-C Model Sim. w/ SPICE

40 35 30 25 20 15 14

16 18 20 Output Power (dBm)

22

Fig. 2. Measurement vs. simulation results for collector efficiency of the cascode PA

Power Loss (%)

45

⎧ d 2 I L (o n ) d I L (o n ) + kq 2 + q 2 I L (o n ) ⎪ 2 d dθ θ ⎪ ⎪ = q 2V d c [1 − p sin (θ + ϕ ) ] / ro n , 0 ≤ θ < π ⎪ 2 ⎨ d I L (o ff) + q 2 I L (o ff) ⎪ 2 ⎪ dθ ⎪ p q 2V d c sin (θ + ϕ ), π ≤ θ ≤ 2π = − ⎪ r ⎩

(1)

where q 2 = 1/ ω 2CL, p = Iron / Vdc , k = ω L / ron . Besides, Vc, Ic, Is can be expressed as functions of IL.

40 35 30 25 20 15 0

1

2 3 4 5 6 CB/CE Emitter-Area Ratio

7

Fig. 3. Power loss of the CB transistor for class-E cascode PA design calculated using the model shown in Fig. 1

assumed as an ideal switch while a constant resistance ron represents the CB transistor during operation. The shunt parasitic capacitance is denoted as C, while ron and C are directly related with the size of the CB transistor. According to Fig. 1, the CB transistor introduces the power loss due to its ron. Making the CB transistor larger can lower the power loss through ron, but the increased intrinsic capacitance C may lead to the efficiency degradation in the meantime due to noneoptimized switching. Therefore, the size of the CB transistor needs to be carefully considered. We will take one example to validate our newly modified model for the cascode PA design. Assuming an ideal switch for the CE transistor, ron= 10 Ω and C=1.1 pF were obtained from S-parameter SPICE simulations. Simulations using this ron-C model for the CB transistor were compared with the SPICE simulated results using all device models from the foundry design kit. Both simulation results were also compared with the measurement data. Fig. 2 shows only a 2% higher collector efficiency prediction from the simple ron-C model, presenting an overall good alignment between simulation and measurement. Additionally, the 1 dB compression point (P1dB) obtained from the ron-C model is only 1 dB lower than the measurement results and the pure SPICE simulation data (not shown).

⎧ d 2IL ⎪VC (θ ) = Vdc − ω L (2) dθ 2 ⎪ dI L ⎪ 2 ⎨ I C (θ ) = −ω CL dθ ⎪ ⎪ I S (θ ) = VC (θ ) / ron , 0

I. INTRODUCTION Broadband 3G/4G/WLAN wireless signals utilize highly spectral-efficient modulation schemes with inherent non-constant-envelope waveforms and high peak-to-average-ratios (PARs). Therefore, highly linear PAs with excellent PAE at their peak power levels are required. Furthermore, efficiency improvements at the low average power levels (i.e., the low-power mode) are desired to extend the battery lifetime of mobile devices, because the average power efficiency of the PA is dominated by a probability distribution function where most RF power transmission is concentrated at much lower power levels than the peak Pout. It is, therefore, critical to maximize the PAE at both peak average POUT and low average POUT regions while keeping the PA linear for these broadband wireless communications. To simultaneously satisfy these design considerations for monolithic RF PAs, several approaches have been proposed such as device size switching, parallel amplification, switchable power combiner, etc. [1]-[3]. In this work, we will apply the combination of the envelope-tracking (ET) technique and the transistor resizing method to a fully-monolithic

978-1-61284-166-3/11/$26.00 ©2011 IEEE

Fig. 1. The parallel-circuit class-E PA model developed for cascode PA design.

cascode SiGe RF PA. For low power mode operation, some power transistor cells will be disabled. The ET technique can successfully enhance the PA efficiency by supply modulation and help keeping it linear at its compression region [4]. Meanwhile, the transistor resizing method enhances the PA efficiency at its backoff region. The Long-Term-Evolution (LTE) 16QAM 5 MHz signal having a PAR of ~7.5 dB will be used to evaluate our ET-based PA design. The cascode configuration is adopted here to relieve the voltage stress on the power transistors. However, the power loss introduced by the common-base (CB) transistor needs to be minimized and design trade-offs studied. In this work, we will first use a newly developed parallelcircuit class-E PA model to aid our transistor size selection. This PA model considers the finite choke inductance and the on-resistance of the CB transistor. II. CASCODE POWER AMPLIFIER DESIGN A. Analysis of the Cascode PA Design In our cascode PA design, a high-fT low-BVCEO bipolar device is utilized as the common-emitter (CE) stage and a high-BVCEO low-fT bipolar device is used as the CB stage. The parallel-circuit class-E PA model was previously reported in [3] for CE PAs, considering a finite choke inductance L; however, we have extended and modified it to cover our cascode PA design. Fig. 1 shows our modified parallel-circuit class-E PA model. For model simplification, the CE transistor used here is

The next step is to theoretically determine the power loss at the CB transistor, where the current flowing through ron (i.e., Is in Fig. 1) needs to be obtained. Applying the KCL at the “VC” node in Fig. 1, two 2ndorder ordinary differential equations regarding to IL can be expressed by (1). Here, the load current IR is assumed as IR=I·sin(θ+φ).

Collector Efficiency (%)

50 Measurement

45

Sim. w/ R-C Model Sim. w/ SPICE

40 35 30 25 20 15 14

16 18 20 Output Power (dBm)

22

Fig. 2. Measurement vs. simulation results for collector efficiency of the cascode PA

Power Loss (%)

45

⎧ d 2 I L (o n ) d I L (o n ) + kq 2 + q 2 I L (o n ) ⎪ 2 d dθ θ ⎪ ⎪ = q 2V d c [1 − p sin (θ + ϕ ) ] / ro n , 0 ≤ θ < π ⎪ 2 ⎨ d I L (o ff) + q 2 I L (o ff) ⎪ 2 ⎪ dθ ⎪ p q 2V d c sin (θ + ϕ ), π ≤ θ ≤ 2π = − ⎪ r ⎩

(1)

where q 2 = 1/ ω 2CL, p = Iron / Vdc , k = ω L / ron . Besides, Vc, Ic, Is can be expressed as functions of IL.

40 35 30 25 20 15 0

1

2 3 4 5 6 CB/CE Emitter-Area Ratio

7

Fig. 3. Power loss of the CB transistor for class-E cascode PA design calculated using the model shown in Fig. 1

assumed as an ideal switch while a constant resistance ron represents the CB transistor during operation. The shunt parasitic capacitance is denoted as C, while ron and C are directly related with the size of the CB transistor. According to Fig. 1, the CB transistor introduces the power loss due to its ron. Making the CB transistor larger can lower the power loss through ron, but the increased intrinsic capacitance C may lead to the efficiency degradation in the meantime due to noneoptimized switching. Therefore, the size of the CB transistor needs to be carefully considered. We will take one example to validate our newly modified model for the cascode PA design. Assuming an ideal switch for the CE transistor, ron= 10 Ω and C=1.1 pF were obtained from S-parameter SPICE simulations. Simulations using this ron-C model for the CB transistor were compared with the SPICE simulated results using all device models from the foundry design kit. Both simulation results were also compared with the measurement data. Fig. 2 shows only a 2% higher collector efficiency prediction from the simple ron-C model, presenting an overall good alignment between simulation and measurement. Additionally, the 1 dB compression point (P1dB) obtained from the ron-C model is only 1 dB lower than the measurement results and the pure SPICE simulation data (not shown).

⎧ d 2IL ⎪VC (θ ) = Vdc − ω L (2) dθ 2 ⎪ dI L ⎪ 2 ⎨ I C (θ ) = −ω CL dθ ⎪ ⎪ I S (θ ) = VC (θ ) / ron , 0