A Hybrid Modular Multilevel Voltage Source Converter ... - IEEE Xplore

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 49, NO. 4, JULY/AUGUST 2013

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A Hybrid Modular Multilevel Voltage Source Converter for HVDC Power Transmission Ralph Feldman, Matteo Tomasini, Emmanuel Amankwah, Jon C. Clare, Senior Member, IEEE, Patrick W. Wheeler, Member, IEEE, David R. Trainer, and Robert S. Whitehouse

Abstract—HVDC transmission systems are becoming increasingly popular when compared to conventional ac transmission. HVDC voltage source converters (VSCs) can offer advantages over traditional HVDC current source converter topologies, and as such, it is expected that HVDC VSCs will be further exploited with the growth of HVDC transmission. This paper presents a novel modular multilevel converter hybrid VSC intended for the HVDC market. The concept of the converter operation is described based on steady-state ac–dc power balance. Techniques for dynamic voltage control, enabling the active and reactive powers exchanged with the grid to be controlled, are introduced. Simulation results further illustrate the theory of operation of the converter and confirm the viability of the proposed control approaches. Detailed predictions of the semiconductor losses confirm the potential to achieve very high efficiencies with this topology. Experimental results are provided to validate the presented converter operation. Index Terms—Converters, HVDC converters, HVDC transmission, HVDC transmission control, multilevel systems.

N OMENCLATURE x X x x

Instantaneous value of a generic variable. RMS value of x. Peak value of x. Average value of x. I. I NTRODUCTION

T

HERE IS currently a great deal of interest in developing insulated gate bipolar transistor (IGBT)-based voltage source converter (VSC) equipment for HVDC power transmission. Such systems can have advantages over the wellknown thyristor-based line-commutated conversion methods, including improved ac-side power quality performance without

Manuscript received April 25, 2012; revised September 10, 2012; accepted October 2, 2012. Date of publication April 12, 2013; date of current version July 15, 2013. Paper 2010-IPCC-336.R1, presented at the 2010 IET International Conference on Power Electronics, Machines and Drives, Brighton, U.K., April 19–21, and approved for publication in the IEEE T RANSACTIONS ON I NDUSTRY A PPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. R. Feldman, M. Tomasini, E. Amankwah, J. C. Clare, and P. W. Wheeler are with The University of Nottingham, Nottingham, NG7 2RD, U.K. (e-mail: [email protected]; [email protected]; emmanuel. [email protected]; [email protected]; pat.wheeler@ nottingham.ac.uk). D. R. Trainer and R. S. Whitehouse are with Alstom Grid, Stafford, ST17 4LX, U.K. (e-mail: [email protected]; robert.whitehouse@ alstom.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIA.2013.2257636

the need for very large harmonic filters, ability to exchange both leading and lagging reactive powers with the connected ac network, unipolar dc cable voltage, ability to feed into a dead load, and smaller physical footprint [1], [2]. Additionally, VSC systems that are able to operate around a common dc grid voltage make multiterminal grids viable. Such grids are not practical when using line-commutated HVDC systems, where the dc-side voltage changes and reverses with power flow. For these reasons, it is anticipated that VSC systems will capture a significant share of future dc transmission schemes, particularly in the renewable energy sector. Today, VSC schemes utilizing hard-switched series strings of IGBTs operated in pulsewidth-modulation (PWM) mode are commercially available [3], [4]. In addition, modular multilevel converter (M 2 C) topologies are being commercially developed and are finding initial application [5]–[8]. This paper describes a novel hybrid VSC topology employing a hybrid combination of soft-switched H-bridge converters operating at fundamental frequency combined with M 2 C cells. The H-bridge converters are formed from series strings of IGBTs to provide the necessary voltage rating; soft switching of the H-bridge converters not only gives rise to low switching losses but also simplifies the design of the IGBT string. The M 2 C cells are arranged to provide a wave-shaping function but operate at only a fraction of the main line current and thus are of lower rating than alternative arrangements. II. C ONVERTER T OPOLOGY AND BASIC O PERATION Fig. 1 shows a hybrid M 2 C converter capable of bidirectional ac–dc power transmission [9]–[11]. Each phase of the converter comprises an H-bridge with an M 2 C chain-link converter connected in parallel with the H-bridge dc terminals. Fig. 2 shows the structure of the chain-link converters, illustrating how they are formed from series strings of cells. To achieve sufficient voltage rating, it is intended that each H-bridge limb is formed from a series string of IGBT devices. The three parallel chain-link/H-bridge converter arrangements are connected in series on the dc side of the circuit to feed the dc transmission line. In normal operation, the H-bridge converters are switched at the zero point of the voltage impressed upon them by the chain-link converters. If the chain-link converters are used to synthesize a rectified ac voltage repeating twice per cycle, then the H-bridge converters are switched at fundamental frequency such that the original nonrectified (or unfolded) waveforms are produced on the ac side.

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Fig. 1. Three-phase hybrid VSC topology.

proposed winding arrangement would allow the transformer to be implemented as three single-phase transformers, which eases shipment to the site and may minimize spare holding. These are important issues in high-power HVDC systems. III. C HAIN -L INK C ONVERTER O PERATION

Fig. 2. Chain-link cells cascaded to form chain-link converter.

The chain-link converters are operated with a 120◦ displacement between the phases, and hence, the summed dc-side voltage nominally contains harmonics only of order 6n since all other 2n harmonic frequencies cancel. Using the chain-link converters to perform a wave-shaping function allows the H-bridge IGBT strings, which are in the main conduction path, to be soft switched at a low frequency and near zero voltage. This reduces switching losses and significantly eases the need for complex dynamic voltage sharing of the series-connected devices, which is normally achieved using gate control and/or passive snubber components. In normal operation, the only devices that require hard switching are the chain-link IGBTs; these are placed outside of the main conduction path, further minimizing switching losses. The converter is interfaced to the ac network via a transformer. The transformer is arranged to provide the necessary isolation between the three H-bridge converters and to cancel triplen harmonics on the network side of the transformer. The

Each chain-link cell is operated by switching the IGBT modules such that the voltage produced by each cell is either 0 or e, where e is the capacitor voltage. It can be seen that the chain-link cell is capable of operating with bidirectional current. Cascading the chain-link cells in this manner enables the chain-link converters to produce arbitrary unipolar voltage waveforms, allowing the synthesis of the required rectified sinusoids. This can be achieved using any traditional multilevel modulation strategy [12], [13]. In steady-state operation, the real power exchanged with the combined chain-link converter cells is sufficient only to supply the losses, meaning that there is no net charging or discharging of the chain-link capacitors. To ensure that the charge is equally distributed between capacitors, some sort of balancing algorithm involving rotation in waveform position is required. We do not discuss that in any further detail since there are many previously reported balancing schemes for other converter topologies that can be applied or adapted [14]–[17]. In the simplest mode of operation, the chain-link converters are modulated to synthesize a rectified sinusoid at the desired ac-side fundamental frequency. The quality of the synthesized waveforms is determined by both the number of chain-link cells and the capacitor voltage balancing algorithm. It is assumed

FELDMAN et al.: HYBRID MODULAR MULTILEVEL VSC FOR HVDC POWER TRANSMISSION

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The mean value of the chain-link phase voltages v CL can be readily obtained as given in v CL = 2 vC /π.

(5)

In steady state, the mean composite chain-link voltage v DC must be equal to the local dc grid voltage VG . Consequently, the ratio of ac-side voltage to dc-side voltage is fixed according to the relationship in v DC = 6 vC /π = VG .

(6)

It is useful to define a modulation index for the converter; following the convention normally adopted for two-level VSCs, the modulation index M I is given by (7). From (6) and (7), it can be seen that the modulation index is fixed in this mode and is given by (8) M I = 2 vC /v DC MI = Fig. 3. Chain-link converter summed voltage vDC and phase voltages vCL .

that, for a high-power converter with many cells, the waveform quality is sufficiently good for switching effects to be ignored in the analysis of power flow. Referring to Fig. 1, the balanced set of three-phase voltages to be generated by the converter on the network side of the transformer is given by 1 a = vC sin(ωt) vC r

PAC

a vCL = vC |sin(ωt)| b = vC |sin(ωt − 2π/3)| vCL

Referring again to Fig. 1, the dc-link voltage vDC is equal to the sum of the chain-link converter phase voltages, as in (3). Fig. 3 provides example waveforms of the composite chain-link voltage vDC and the chain-link phase voltage vCL vDC =

a vCL

+

b vCL

+

c vCL .

(3)

The ac-side line currents are assumed to be sinusoidal with an arbitrary phase shift φ as given in iaC

= iC sin(ωt − φ)

= iC sin(ωt − 4π/3 − φ).

4

iC cos(φ).

(10)

Equations (9) and (10) have been formed assuming that there is no average power exchange with the chain links, and this can be proved by first forming an expression for the current in the H-bridges, iH , and in the chain-link cells, iCL . The current for the phase-a H-bridge (the other phases are the same with appropriate time shifts) is easily determined as 0 ≤ ωt ≤ π

iaH = − iaC = −iC sin(ωt − φ),

π ≤ ωt ≤ 2π.

(11)

The phase-a chain-link current for one half cycle (it is periodic at twice the supply frequency) can be determined as iaCL = iDC −iaH = iDC −iC sin(ωt − φ),

0 ≤ ωt ≤ π.

(12)

By integrating (12), the average power exchanged with the chain link is given by a P CL

=

π/ω ω

π

iDC − iC sin(ωt − φ) vC sin(ωt)dt

0

ibC = iC sin(ωt − 2π/3 − φ) icC

π

iaH = iaC = iC sin(ωt − φ), (2)

(9)

PDC

iDC =

(1)

If the H-bridge converters are zero voltage soft switched, as intended, then the voltages that the chain-link converters must synthesize are given by

= vC |sin(ωt − 4π/3)| .

(8)

3 vCiC cos(φ)/2 = 6iDC vC /π

1 b = vC sin(ωt − 2π/3) vC r

c vCL

2π ≈ 1.05. 6

The relationship between the ac-side and dc-side currents can be derived on the basis of power balance, assuming that there is no average power exchange with the chain-link converters and that the dc-side current is smooth. Equating powers yields (9). This can be further simplified to give the steady-state relationship between the converter current and the mean dc-link current, as shown in (10).

1 c = vC sin(ωt − 4π/3). vC r

(7)

a

(4)

⇒ P CL =

2 vC iDC iC cos(φ) − vC . π 2

(13)

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Applying (10) shows that this equates to zero as desired. Equation (12) also allows us to determine the average chainlink current given by a iCL

π/ω ω iC sin(ωt − φ)dt = iDC − π 0 a

2iC cos(φ) π

π 2 − = iC cos(φ) ≈ 0.15iC cos(φ) 4 π

8 = iDC 1 − 2 ≈ 0.19iDC . (14) π

⇒ iCL = iDC − a

⇒ iCL a

⇒ iCL

From (14), we can see that the average chain-link current is approximately 19% of the dc-side current and is never greater than approximately 11% of the rms ac line current. This is a desirable feature of the converter topology, as it shows that the wave-shaping component of the topology sits outside of the main power path, and thus, one can expect a reduction in switching losses.

abc Fig. 4. Chain-link converter summed voltage vCL and phase voltages vCL with third harmonic injection—α3 = 0.2.

Applying (16) to (15) yields ⎡ a vC = vC ⎣sin(ωt) +

IV. VOLTAGE C ONTROL M ETHODS The basic mode of operation introduced earlier serves to introduce the general concept of the converter topology, but for any practical application, voltage ratio control will be necessary, particularly, for example, to control reactive power exchange with the ac network. If the H-bridge converters are to remain zero voltage soft switched (i.e., no PWM), then ac voltage control can only be achieved by modifying the target ac-side voltages, including the addition of harmonics, such that the ratio between the rectified mean of the acside voltage and its fundamental component is altered. In the most general sense, each ac-side phase voltage can be modified by the addition of an infinite series of harmonics as in ∞

a a a αk sin (kωt + θk ) vC = vC sin(ωt) +

⎡

⎤

∞

αk sin(kωt)⎦

k=3,9,15,21...∞

b = vC ⎣sin(ωt − 2π/3) + vC

∞

⎤ αk sin(kωt)⎦

k=3,9,15,21...∞

⎡ c vC = vC ⎣sin(ωt − 4π/3) +

∞

⎤ αk sin(kωt)⎦ .

k=3,9,15,21...∞

(17) Equation (17) incorporates all the possible solutions for the ac target voltages that allow the line-frequency zero-voltage switching of the H-bridges, without the additional distortion of the line-to-line voltage. In the following section, the simplest form of voltage control using only third harmonic addition (k = 3) is analyzed.

k=2

b vC = vC sin(ωt − 2π/3) +

∞

b

A. Voltage Control Using Third Harmonic Addition Only

αkb sin kωt + θk

With the addition of a third harmonic component, the target ac voltages can now be written as in

k=2

c vC

= vC sin(ωt − 4π/3) +

∞

αkc

sin (kωt +

θkc )

.

(15)

k=2

b vC = vC [sin(ωt − 2π/3) + α3 sin(3ωt)]

Under the constraint that added components should cancel in the line-to-line voltage (i.e., be common mode) and, further, that the zero crossings of the composite waveform must coincide with the zero crossings of the fundamental, we can deduce that all the feasible solutions are characterized by αka = αkb = αkc = αk ,

θkabc = 0,

k = 3, 9, 15, 21 . . . ∞.

a = vC [sin(ωt) + α3 sin(3ωt)] vC

(16)

c vC = vC [sin(ωt − 4π/3) + α3 sin(3ωt)] .

(18)

The phase-a chain-link voltage is given by (19); similar expressions exist for the other phases. An example of the synthesized chain-link voltages can be seen in Fig. 4. a = vC |sin(ωt) + α3 sin(3ωt)| vCL

(19)


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Note that it is not possible for the chain-link converters to produce negative voltages nor is it possible for the H-bridges to accept them; hence, it is possible to show that α3 should be restricted to the range given in −1/3 ≤ α3 ≤ 1.

(20)

With the third harmonic addition, the mean value of the individual chain-link phase voltages is now given by v CL =

2 vC (1 + α3 /3). π

(21)

Hence, the mean composite chain-link voltage v DC which, in steady state, must be equal to the local dc grid voltage VG is given by v DC =

6 vC (1 + α3 /3) = VG . π

Fig. 5. vDC (normalized to v DC ).

(22)

From (6) and (22), it can be seen that third harmonic addition allows variation in the ac-side-voltage to dc-side-voltage ratio. Thus, by adjusting α3 , the magnitude of the ac-side voltage may be changed instantaneously, while the mean sum of the chainlink voltages, v DC , remains constant. Using the definition for the modulation index expressed in (8), the modulation index as a function of α3 can now be expressed as in MI =

2π . 6(1 + α3 /3)

(23)

Fig. 6. vDC /v DC rms ripple as function of α3 .

Applying (20) to (23) yields the modulation index range, given in 0.785 ≤ M I ≤ 1.178.

(24)

Since it is now possible to control the magnitude and phase of the ac-side voltage, any of the reported grid converter control methods (for example, using rotating reference frames) can be employed for the regulation of real and reactive power exchange with the ac network [18]–[20]. Note that the restricted range of the modulation index is easily adequate for grid interface control. The equation for ac–dc power balance is now modified as given in 3 vCiC cos(φ)/2 = 6iDC vC (1 + α3 /3)/π . PAC

(25)

PDC

V. C HAIN -L INK VOLTAGE R IPPLE AND DC-L INK C URRENT R IPPLE Using the previous assumptions that each chain-link converter is able to track its reference waveform perfectly and only third harmonic addition is used, the total chain-link voltage vDC , normalized to the mean chain-link voltage v DC , is given by (26). A plot of this waveform for four values of alpha is shown in Fig. 5. As expected, the composite chain-link voltage is periodic at six times the ac supply frequency π π vDC π . = 2 cos ωt − +α3 sin(3ωt) 0 ≤ t ≤ v DC 6 + 2α3 6 3ω (26)

Fig. 7. iDC peak-to-peak ripple as a percentage of the mean dc-link current iDC , LDC = 22.06 mH (1.1455 p.u.), and VG = 20 kV.

Fig. 6 shows a plot of the rms ripple in the normalized chainlink voltage, vDC /v DC , against α3 . It can be seen that, for values of α3 less than zero, it is possible for the injection of the third harmonic component to reduce the ripple, compared to the case without third harmonic injection. An expression for the dc-link current, split into its mean value and the ripple, is given by (27). The derivation of this equation assumes that the dc side is modeled using an inductor and an ideal voltage source to represent the local dc grid voltage. The percentage dc-link current ripple is plotted against α3 in Fig. 7, and the inductance has been chosen to give a worst case ripple of 20% at the extreme end of the voltage control range π VG π iDC = iDC + −2 sin ωt − Ldc (6 + 2α3 )ω 6 α3 α3 π + cos(3ωt) − 1 − +t 0≤t≤ . (27) 3 3 3ω

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Fig. 8. Peak chain-link phase voltage as a function of α3 , normalized to the peak converter voltage vc . Fig. 9. Range of normalized peak chain-link current, iCL / iC , as a function of α3 . The hashed area shows the required available operating range when no limit on DPF is applied.

VI. C HAIN -L INK C ELL R ATING Using (19) and the restrictions for α3 given by (20), the peak chain-link phase voltage is given by vCL = vC |sin(ρ) + α3 sin(3ρ)|

9 1 −1 ρ = cos − , 12 12α3 π ρ = , −1/3 ≤ α3 ≤ 1/9. 2

1/9 < α ≤ 1 (28)

In Fig. 8, the results of (28) are plotted. When low positive values of α3 are used, the required available chain-link voltage is reduced by the injection of a third harmonic component. This is akin to using a third harmonic component to increase the modulation index range in a standard three-phase VSC [12]. If it assumed that the available range of α3 is not limited such that the complete modulation index range given by (24) is available, then each chain-link phase must be capable of producing approximately 1.5 times the peak converter voltage vc . To make a comparison with an original M 2 C converter capable of operating up to the same maximum modulation index, each limb of the converter must be rated at 1.42 times the converter voltage. Taking into consideration that there are two limbs per phase in the M 2 C converter and assuming that the chain-link cells would be operated with equal nominal capacitor voltages, the ratio between the total required chainlink cells becomes 1.5/2.84. Thus, using this topology, the required number of capacitors would be reduced by almost a factor of two. It is not possible to extend this argument to the total number of semiconductors, as additional semiconductors are required in the H-bridge converters. In rating the chain-link cells, it is also necessary to know the peak current. If it assumed that LDC is sufficiently large that the ripple in the dc-link current can be disregarded in the calculation of the peak chain-link current, applying (25) to (12) yields (29). Applying the limits for ωt given in (29), the peak magnitude of the chain-link current, iCL , can be calculated using (30). This shows that the peak chain-link current magnitude is a function of both the displacement power factor (DPF) and α3 . It is interesting to note that, when the DPF is an integer multiple of ±π/2, then, the peak chain-link phase current is

independent of α3 and equal in magnitude to the peak converter current iC . Fig. 9 shows the normalized range of possible chainlink current as a function of α3 ; it is assumed that no limit is placed on the DPF. Global maximums and minimums occur at the extreme of the permitted range of α3 . The peak current magnitude has a global maximum of 1.33 iC which occurs when α3 is at its most negative, i.e., −1/3. Likewise, a global minimum of 0.59 iC occurs when α3 is at the most extreme of its range, i.e., 1.

3π a cos(φ) − sin(ωt − φ) , iCL = iC 12 + 4α3 iCL = iC

3π 12 + 4α3

0 ≤ ωt ≤ π

|cos(φ)| + |sin(φ)| .

(29) (30)

VII. C ONTROL S TRATEGY In order to develop a simulation model of the converter that could validate the basic concept, a simple control scheme has been implemented. On the ac side, a standard rotating reference frame (dq) positive sequence line current controller is used [18], [21], [22], which allows the real and reactive powers exchanged with the grid to be controlled according to input demands. The arrangement of the control is entirely standard and is depicted in Fig. 10. The output of the control scheme are the ac-side voltage magnitude Vc and instantaneous load angle δ. On the dc side, the dc transmission voltage is assumed to be fixed by another converter at the other end of the line (modeled here by an ideal voltage source). A cascaded control scheme has been implemented to achieve power balance. This consists of a slow outer control loop regulating the square of the capacitor voltages. This sets the reference for a faster inner control loop which controls the dc-link current. The control loops are illustrated in Figs. 11 and 12, respectively. As shown in Fig. 11, the capacitor voltage reference is squared and multiplied by the total number of chain-link cells in


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TABLE I S IMULATION PARAMETERS

Fig. 10. Decoupled

idq s

control scheme.

Fig. 11. Chain-link capacitor voltage control scheme generating dc-link cur∗ . rent reference Idc

Fig. 12. DC-link current Idc control scheme.

the converter; the resultant reference signal is thus proportional to the total energy stored in the capacitors. By regulating the total energy stored in the capacitors, via the measured capacitor voltages, the balance between the net dc power and the ac active power is maintained. Additionally, any net energy transferred to/from the capacitors, as a result of transient errors in ac–dc power balance, is corrected. As it is the total energy stored that is effectively controlled, it is necessary that a capacitor voltage balancing scheme is used to distribute the energy, and therefore the voltage, equally among the capacitors in each phase. That aspect is not discussed further here since techniques that can be used directly or adapted have been published for use with this and other topologies [14], [15]. A proportional–integral controller is used to give a demand for the total power to the ∗ . The dc power demand is calculated chain-link capacitors, PCL by adding the output of the PI controller to the ac power demand. Therefore, for a constant dc supply voltage, a dc-link current demand can be calculated. The control of the dc-link current is illustrated in Fig. 12. It can be seen that a PI controller is used to generate a demand for the chain-link voltage, from which the value of α3 can be computed. VIII. S IMULATION R ESULTS Simulation results have been obtained for a proposed lowpower demonstrator prototype, rated for 20 MW and 11 kV. All simulations have been performed using MATLAB in con-

junction with the PLECS Blockset for MATLAB. The nominal VSC operating point is chosen to maintain a charge on each chain-link cell capacitor corresponding to an average voltage of 1500 V; this is representative of the voltage limitations of suitable 3.3-kV IGBT modules, when headroom for fault scenarios and voltage ripple is considered. Table I lists the main parameters used for the simulation; nine chain-link cells per phase have been used. A relatively low number of cells has been used to simplify the simulation; in a real application, the number of cells used would likely be an order of magnitude higher, and waveform quality would be correspondingly improved. The control of the real and reactive powers has been implemented using a simple dq scheme with voltage control through triplen harmonic injection as described earlier. A carrier-based modulation strategy, adapted for the HVDC VSC, has been used to modulate the chain-link converters [13]. The switching frequency of the chain-link cells is approximately 100 Hz. A simple balancing algorithm has been used to balance the capacitor voltages [14]. For the purposes of modeling, the interface transformers are considered ideal, and a separate line interface reactor is included in each phase. Of course, in a practical application, some or all of the interface reactance would be provided by the transformer leakage inductance. A. Steady-State Simulation Results Initially, results for steady-state operation are presented demonstrating power being exported to the grid from the dc bus, while the unity displacement factor is maintained. Fig. 13 shows plots of the supply voltage vs , the converter voltage vC , and the line current is obtained through simulation. The converter voltages are measured from the network side terminals of the (ideal) transformer to the star point of the supply, illustrating that the fundamental waveform is well synthesized and the triplen harmonic is canceled. The line current drawn is 180◦ out of phase with the supply voltage, showing that the power is negative and the converter is rectifying into the dc grid. Furthermore, the line current is near sinusoidal with a low total harmonic distortion (THD), 3.3%, despite the relatively low number of cells simulated. In a practical VSC transmission scheme, the number of cells would be at least an order of magnitude higher and produce near-perfect sinusoidal waveforms. The upper plot of Fig. 14 shows negative dc-link current arising from the negative power demand. The lower plot shows the composite chain-link voltage. Both plots illustrate the sixtime supply frequency variation. The quality of the chain-link

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Fig. 15. Steady-state phase-a chain-link cell capacitor voltage operating at P = −20 MW and Q = 0 Mvar.

Fig. 13. Steady-state ac-side waveforms operating at P = −20 MW and Q = 0 Mvar.

Fig. 16.

Converter transient waveforms through P Q operating envelope.

clearly exists in the cell rotation scheme, between the capacitor energy distribution and the introduction of additional switching instances. B. Transient Simulation Results

Fig. 14. Steady-state dc-side waveforms operating at P = −20 MW and Q = 0 Mvar.

voltage waveform is limited by the discrete levels of chain-link cells. Fig. 15 shows the capacitor voltage during the steady-state conditions; over one fundamental period, the peak-to-peak ripple in the capacitor voltage is approximately 27% of the mean capacitor voltage. For a given cell capacitor value, this ripple is dependent on the P Q operating point and the cell capacitor voltage operating point. In addition to this, the cell rotation scheme also affects the capacitor ripple; a tradeoff

Fig. 16 shows the responses to ramp demands in real and reactive powers. Traces are shown for the line currents in the dq synchronous reference frame, the dc-link current, and the total energy stored in the chain-link capacitors. The d-axis of the dq reference frame is aligned with the fundamental component of the supply voltage. The line currents in the dq reference frame and the dc link track their reference demands well. During the transient, there is a small error in the d component of the line current, leading to a difference between the ac and the dc power; this occurs since the ac power reference is fed forward in the calculation of the dc power demand and not the actual ac power. This difference leads to a small error in the capacitor voltage during the transient, which is corrected by the controller after the transient. The maximum deviation


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Fig. 17. Loss breakdown as a percentage of real power at 1-p.u. power.

in the total stored energy is 7500 J; assuming that the energy stored in the capacitors is perfectly distributed by the balancing algorithm, this corresponds to approximately 50 V on each capacitor. It should be noted that these values indicate that the controller implemented is able to ensure that the net energy in all the cells is well regulated during transients.

Fig. 18. Total semiconductor losses as a function of rated power when using nine series IGBTs to form H-bridge limbs.

IX. S EMICONDUCTOR L OSSES Estimations of the semiconductor losses have been obtained through postprocessing the simulation results for the device currents and the conditions at each commutation, taking into account the device data sheet information for forward conduction drop and switching energy losses (Eon and Eof f ). This is a well-established method described in detail in many publications [23]–[25] and hence is not repeated here. The Toshiba MG1200FXF1US53C 3.3-kV 1.2-kA IGBT with antiparallel diode has been chosen as a representative device. Fig. 17 shows the breakdown of losses as a percentage of real power, which directly indicates the impact on the efficiency of the losses. As expected, efficiency decreases when there is a reactive power demand due to the additional reactive current component. Losses in the H-bridge converters account for approximately 80% of the total loss with the chain-link converters contributing only 20%. This is a direct result of using the chainlink converters to perform the wave-shaping function. Since the chain-link converters sit outside the main power path switching and conduction losses are minimized, as a result, the majority of the losses come from the conduction losses in the soft-switched H-bridge converters. This highlights the effectiveness of the converter topology in achieving inherently low semiconductor losses. Since the H-bridge conduction losses dominate, it is interesting to consider ways in which they can be reduced, noting that there are no demands on switching performance for these devices. One approach is to replace the IGBT devices in the H-bridges with integrated gate-commutated thyristor (IGCT) devices. This allows the use of fewer devices, each with reduced forward voltage drop. Based on the ABB 4.5-kV 2920-A IGCT and parallel diode pair, 5SHY 55L4500/5SDF 10H4520, five IGCT series devices may be used instead of nine IGBT devices in the demonstrator example. Figs. 18 and 19 show an estimation of total semiconductor losses plotted as a function of real power; Fig. 18 shows the case when IGBTs are used, while Fig. 19 shows the case when

Fig. 19. Total semiconductor losses as a function of rated power when using five series IGCTs to form H-bridge limbs.

the IGBTs are substituted for IGCTs. These figures clearly demonstrate the significant benefits of using IGCTs in the H-bridge limbs. At rated power, the use of IGCTs results in the losses being reduced to approximately 50% of those for the IGBT solution. The option to reduce losses in this manner arises as a consequence of the hybrid arrangement which separates soft-switched devices (where the main conduction losses are generated) from the hard-switched devices used to perform a wave-shaping function. X. E XPERIMENTAL R ESULTS Experimental results have been obtained for a low-power demonstrator rated at 10 kVA. Results are presented here when inverting into an R−L load, and the demonstrator parameters can be found in Table II. Six cells per phase have been used in the demonstrator; to compensate for this, the chain-link cells

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TABLE II E XPERIMENTAL PARAMETERS

Fig. 21.

DC-link current when inverting into an R−L load. α3 = −0.17.

Fig. 20. Converter voltage and current when inverting into an R−L load. α3 = −0.17.

are operated using the PWM strategy described in [14] with a switching frequency of 2.4 kHz. and the line Fig. 20 shows the line–line converter voltage vC current is . The voltage waveform vC is well synthesized with a THD of 7.71%; additionally, the third harmonic component of the phase voltage is well canceled in the line voltage waveform. The line current is near sinusoidal with a THD of 3.35%. Fig. 21 shows the dc-link current iDC to be well controlled to its reference value of 2.4 A. In the operating point shown, a negative value of α3 is used, and as a consequence, the characteristic 6n dc-link ripple is reduced. Fig. 22 shows the voltage across each of the six chain-link cell capacitors in phase a. The capacitor voltages are well regulated to their reference value of 47 V. From inspection of Fig. 22, the discharging of the capacitors is seen when the capacitors are not conducting; this occurs as a result of using bleed resistors in parallel with the capacitors, allowing safe discharge of the capacitors after shutdown. Analysis of the capacitor voltages shows that the second harmonic ripple is relatively low; this occurs as a result of the comparatively low P Q operating point for the voltage magnitude. This means that the second harmonic component of the capacitor voltage,

Fig. 22. Phase-a capacitor voltages when inverting into an R−L load. α3 = −0.17.

stemming from the fundamental power dissipated into the R−L load, is relatively small compared to the additional harmonics stemming from the ripple in the dc-link power associated with the ripple in the dc-link voltage. XI. C ONCLUSION A new low-loss VSC topology for HVDC power transmission has been described. The topology combines H-bridge converters utilizing soft-switched series IGBT (or IGCT) strings together with M 2 C technology used to provide a wave-shaping function.


The circuit inherently has low switching losses and makes efficient use of multilevel converter cells. A triplen harmonic addition modulation scheme is utilized to enable voltage control for real and reactive power regulation. Simulation results have been presented, demonstrating steady-state operation of the converter and transient performance. In addition, simulation results have confirmed the expected low semiconductor losses inherent in the topology. It has been shown that, using IGBT technology, semiconductor losses are expected in the region of 0.85% to 1.1% of the rated power. If the H-bridge IGBTs are replaced with IGCTs, semiconductor losses can be expected to be reduced down to 0.35% to 0.46% of the rated power. Experimental results have validated the steady-state operation of the converter when inverting into an R−L load. Using the chain-link converters to perform the wave-shaping function outside of the main conduction path makes efficient use of the hybrid arrangement; switching losses are reduced, and additionally, the ability to take advantage of different semiconductor technologies in one converter further enables the reduction of losses. R EFERENCES [1] F. Schettler, H. Huang, and N. Christl, “HVDC transmission systems using voltage sourced converters design and applications,” in Proc. IEEE Power Eng. Soc. Summer Meeting, 2000, vol. 2, pp. 715–720. [2] J. Pan, R. Nuqui, K. Srivastava, T. Jonsson, P. Holmberg, and Y.-J. Hafner, “AC grid with embedded VSC-HVDC for secure and efficient power delivery,” in Proc. IEEE ENERGY Conf., Nov. 17/18, 2008, pp. 1–6. [3] N. Flourentzou, V. Agelidis, and G. Demetriades, “VSC-based HVDC power transmission systems: An overview,” IEEE Trans. Power Electron., vol. 24, no. 3, pp. 592–602, Mar. 2009. [4] M. Bahrman and B. Johnson, “The ABCs of HVDC transmission technologies,” IEEE Power Energy Mag., vol. 5, no. 2, pp. 32–44, Mar./Apr. 2007. [5] S. Allebrod, R. Hamerski, and R. Marquardt, “New transformerless, scalable modular multilevel converters for HVDC-transmission,” in Proc. IEEE PESC, Jun. 2008, pp. 174–179. [6] M. Glinka and R. Marquardt, “A new ac/ac multilevel converter family,” IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 662–669, Jun. 2005. [7] M. Hagiwara and H. Akagi, “PWM control and experiment of modular multilevel converters,” in Proc. IEEE PESC, Jun. 2008, pp. 154–161. [8] M. Hagiwara and H. Akagi, “Control and experiment of pulsewidthmodulated modular multilevel converters,” IEEE Trans. Power Electron., vol. 24, no. 7, pp. 1737–1746, Jul. 2009. [9] R. Feldman, M. Tomasini, J. Clare, P. Wheeler, D. Trainer, and R. Whitehouse, “A hybrid voltage source converter arrangement for HVDC power transmission and reactive power compensation,” in Proc. IET-PEMD, Brighton, U.K., Apr. 19–21, 2010, pp. 1–6. [10] R. Feldman, M. Tomasini, J. Clare, P. Wheeler, D. Trainer, and R. Whitehouse, “A low loss modular multilevel voltage source converter for HVDC power transmission and reactive power compensation,” in Proc. IET-ACDC, London, U.K., Oct. 20/21, 2010, pp. 1–5. [11] M. Tomasini, R. Feldman, J. Clare, P. Wheeler, D. Trainer, and R. Whitehouse, “DC-link voltage ripple minimization in a modular multilevel voltage source converter for HVDC power transmission,” in Proc. 14th EPE, Aug. 30/Sept. 1, 2011, pp. 1–10. [12] D. Holmes, T. Lipo, and T. Lipo, Pulse Width Modulation for Power Converters: Principles and Practice. Piscataway, NJ, USA: IEEE Press, 2003, ser. IEEE Press Series on Power Engineering. [13] B. Wu, High-Power Converters and AC Drives. Hoboken, NJ, USA: Wiley, 2006. [14] E. Amankwah, J. Clare, P. Wheeler, and A. Watson, “Cell capacitor voltage control in a parallel hybrid modular multilevel voltage source converter for HVDC applications,” in Proc. IET-PEMD, Bristol, U.K., Mar. 27–29, 2012, pp. 1–6. [15] E. Amankwah, J. Clare, P. Wheeler, and A. Watson, “Multi carrier PWM of the modular multilevel VSC for medium voltage applications,” in Proc. 27th Annu. IEEE APEC, Feb. 2012, pp. 2398–2406.

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[16] P. K. Jin, M. Dahidah, and C. Klumpner, “Nine-level SHE-PWM VSC based STATCOM for VAR compensation,” in Proc. IEEE Int. PECon, Nov. 29/Dec. 1, 2010, pp. 135–140. [17] A. Shukla, A. Ghosh, and A. Joshi, “Natural balancing of flying capacitor voltages in multicell inverter under PD carrier-based PWM,” IEEE Trans. Power Electron., vol. 26, no. 6, pp. 1682–1693, Jun. 2011. [18] J. Vassallo, “Multilevel converters for regenerative fuel-cells,” Ph.D. dissertation, School Elect. Electron. Eng., Univ. Nottingham, Nottinghamshire, U.K., Jan. 2005. [19] J. Espinoza, G. Joos, and L. Moran, “Decoupled control of the active and reactive power in three-phase PWM rectifiers based on non-linear control strategies,” in Proc. 30th Annu. IEEE PESC, Aug. 1999, vol. 1, pp. 131–136. [20] R. Teodorescu, F. Blaabjerg, M. Liserre, and P. Loh, “Proportionalresonant controllers and filters for grid-connected voltage-source converters,” Proc. Inst. Elect. Eng.—Elect. Power Appl., vol. 153, no. 5, pp. 750– 762, Sep. 2006. [21] R. Ottersten and J. Svensson, “Vector current controlled voltage source converter-deadbeat control and saturation strategies,” IEEE Trans. Power Electron., vol. 17, no. 2, pp. 279–285, Mar. 2002. [22] L. Xu, B. Andersen, and P. Cartwright, “Control of VSC transmission systems under unbalanced network conditions,” in Proc. IEEE PES Transmiss. Distrib. Conf. Expo., Sep. 2003, vol. 2, pp. 626–632. [23] M. Bierhoff and F. Fuchs, “Semiconductor losses in voltage source and current source IGBT converters based on analytical derivation,” in Proc. 35th Annu. IEEE PESC, 2004, vol. 4, pp. 2836–2842. [24] A. Bhalla, J. Gladish, and G. Dolny, “Effect of IGBT switching dynamics on loss calculations in high speed applications,” IEEE Electron Device Lett., vol. 20, no. 1, pp. 51–53, Jan. 1999. [25] S. Eicher, S. Bernet, P. Steimer, and A. Weber, “The 10 kV IGCT—A new device for medium voltage drives,” in Conf. Rec. IEEE IAS Annu. Meeting, 2000, vol. 5, pp. 2859–2865.

Ralph Feldman received the Ph.D. degree in electrical engineering for his work on induction machine standard efficiency tests from The University of Nottingham, Nottingham, U.K., in 2007. Since 2007, he has been with The University of Nottingham as a Research Fellow within the Power Electronics, Machines and Control Group. His research interests include power-converter topologies and HVDC transmission systems.

Matteo Tomasini received the M.S. and Ph.D. degrees in electrical engineering from the University of Padua, Padua, Italy, in 2003 and 2007, respectively. Over that period, he focused his research on minimum time current and torque control of permanent-magnet synchronous machines, steer-bywire applications, and sensorless control of induction motors. Since 2007, he has been a Research Fellow with the Power Electronics, Machine and Control Group, Department of Electrical and Electronic Engineering, The University of Nottingham, Nottingham, U.K., where he has been working on innovative high-power electric drives and HVDC converters.

Emmanuel Amankwah received the M.Sc. degree in electrical engineering from The University of Nottingham, Nottingham, U.K., in 2009, where he is currently working toward the Ph.D. degree in the Power Electronics, Machines and Control Group. His research interests include high-power converter topologies and HVDC and FACTS systems.

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Jon C. Clare (M’90–SM’04) was born in Bristol, U.K., in 1957. He received the B.Sc. and Ph.D. degrees in electrical engineering from The University of Bristol, Bristol. From 1984 to 1990, he was a Research Assistant and Lecturer with The University of Bristol, where he was involved in teaching and research on power electronic systems. Since 1990, he has been with the Power Electronics, Machines and Control Group at The University of Nottingham, Nottingham, U.K., where he is currently a Professor of power electronics. His research interests include power-electronic converters and modulation strategies, variable-speed-drive systems, and electromagnetic compatibility.

Patrick W. Wheeler (M’00) received the Ph.D. degree in electrical engineering for his work on matrix converters from The University of Bristol, Bristol, U.K., in 1993. Since 1993, he has been with The University of Nottingham, Nottingham, U.K., where he was a Research Assistant with the Department of Electrical and Electronic Engineering and, in 1996, was a Lecturer in power-electronic systems with the Power Electronics, Machines and Control Group, where he has been a Professor since 2008. His research interests include power-converter topologies and their applications.

David R. Trainer was born in Wolverhampton, U.K., in 1963. He received the B.Sc.(Hons.) and Ph.D. degrees in electrical engineering from Staffordshire Polytechnic, Staffordshire, U.K., in 1985 and 1991, respectively. In 1985, he joined GEC and worked on the development of water-cooled thyristor valves for HVDC power transmission and reactive power compensation. In 1989, he began to investigate the use of high-power GTO thyristors for static reactive power compensation, which lead to the award of the Ph.D. degree. His research and development work continued and ultimately lead to a commercial STATCOM installation of ±75 MVA being installed on the U.K.’s National Grid at East Claydon. In 1998, he joined Goodrich Actuation Systems Ltd. to work on electric actuation systems for the more electric aircraft, and in 2004, he joined Rolls-Royce PLC, London, U.K., to work on more electric engine concepts. In 2008, he joined Alstom to work on the development of new voltage-sourced converters for HVDC power transmission. His research interests include HVDC power transmission, reactive power compensation, clean-power rectifier and inverter systems, distributed generation systems, and more electric concepts for future aircraft systems.

Robert S. Whitehouse was born in Sheffield, U.K., in 1956. He received the degree from North Staffordshire Polytechnic, Stoke-on-Trent, U.K., in 1979. He was with the GEC Power Electronics Division in 1981, working on the control systems for the Cross Channel 2000-MW HVDC project. Afterward, he continued control development in the company’s simulation laboratory, working on HVDC projects in Canada (APL McNeill, Neslon River), Korea (Cheju), India (Chandrapur, Vizag), and Uruguay (Rivera). After a period as an independent consultant, he joined Alstom Grid, Stafford, U.K., in 2008 to develop converter topologies and control systems for voltage source converters and their application to power systems.