A Low Dark Leakage Current High-Sensitivity CMOS ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014

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A Low Dark Leakage Current High-Sensitivity CMOS Image Sensor With STI-Less Shared Pixel Design Min-Woong Seo, Member, IEEE, Shoji Kawahito, Fellow, IEEE, Keita Yasutomi, Member, IEEE, Keiichiro Kagawa, Member, IEEE, and Nobukazu Teranishi, Fellow, IEEE

Abstract— A CMOS image sensor with a low dark current and high sensitivity is developed with shallow trench isolation (STI)less shared pixel. By sharing in-pixel transistors, such as the reset transistor, select transistor, and source follower amplifier, each pixel achieves a high fill factor of 43% and a high sensitivity of 144.6 ke− /lx · s. In addition, compared with a conventional image sensor which has the STI structure in the pixel for isolation, the developed image sensor achieves a relatively low dark current of 104.5 e− /s/pixel (median), corresponding to a current density Jdark of approximately 30 pA/cm2 at 60 °C. This is a low value and the consequence of not using STI as pixel isolation. Both types of pixels, namely the conventional and the proposed active pixel sensor have the same pixel size of 7.5 × 7.5 µm2 and are fabricated by the same process. The developed imager with STI-less shared pixel obtains sufficiently good responses at 400 to 900 nm, and, particularly, a peak QE of 68% at 600 nm. This is suitable for scientific applications. Index Terms— CMOS image sensor (CIS), high sensitivity, low dark current, shallow trench isolation (STI), shared pixel.

I. I NTRODUCTION

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HE shallow trench isolation (STI) technique is widely used as a device isolation technique in CMOS largescale integration (LSI) technology nodes of 250 nm and smaller. The STI contributes to high-packing density in CMOS LSIs. However, the use of STI in CMOS image sensors leads to a large surface leakage current induced by Si/SiO2 interface states. The leakage current contributes to the pixel dark noise, even though the noise performance of CMOS image sensors (CISs) [1], [2] has been greatly improved since the introduction of the pinned photodiode technology [3]. Currently, the dark signal components resulting from interface defects around the isolation are the most critical issue [4]–[8]. Manuscript received November 18, 2013; revised January 28, 2014 and March 27, 2014; accepted April 15, 2014. Date of publication May 6, 2014; date of current version May 16, 2014. This work was supported in part by the Grant-in-Aid for Scientific Research (S) under Grant 25220905 through the Ministry of Education, Culture, Sports, Science and Technology, and in part by the Japan Society for the Promotion of Science International Training Program. The review of this paper was arranged by Editor J. R. Tower. M.-W. Seo is with the Research Institute of Electronics, Shizuoka University, Hamamatsu 432-8011, Japan, and also with the Japan Society for the Promotion of Science, Tokyo 102-0083, Japan (e-mail: [email protected]). S. Kawahito, K. Yasutomi, K. Kagawa, and N. Teranishi are with the Research Institute of Electronics, Shizuoka University, Hamamatsu 432-8011, Japan (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TED.2014.2318522

To solve this problem, the recently reported STI-less CIS [9] has a high signal-to-noise ratio due to the removal of dark current generated from interface defects located at STI corners. However, this technology requires a special process for pixel isolation. This paper proposes a CMOS image sensor with a low dark current and high sensitivity. This CMOS active pixel sensor (APS), which is developed without any process modification, has 1.75 transistors/pixel. By eliminating the STI structures in the pixel, one of the major dark current sources is removed and so dark leakage current is significantly reduced. In addition, a ring-gate shared-pixel design eliminates the STI structure at the channel edge of metal–oxide–silicon field effect transistors. Without the STI structure, the results are a low 1/ f and random telegraph signal noise amplifier for CMOS active pixels. II. S ENSOR A RCHITECTURE A. Pixel Structure Fig. 1(a) and (b) shows the pixel structure using ring-gate transistors and its equivalent circuit schematic, respectively. Each pixel is isolated by a p-well and other highly-doped p-type layers. The p-type layers surrounding the pixels not only help to remove dark leakage sources, such as defects at the edge of the pixel, but also play the role of pixel isolators. Therefore, the proposed pixel does not need to employ an STI. This STI-less structure not only avoids large-surface dark leakage current but also allows fill factor improvement by the optimized pixel layout. The designed pixel has a large fill factor of 43%. The 2 × 2 shared-pixel shown in Fig. 1 consists of four photodiodes, a reset transistor (RT), a select transistor (SL), and an in-pixel source follower (SF) amplifier. The effective number of transistors per pixel is 1.75. Each accumulated signal charges in four photodiodes are transferred to a floating diffusion (FD) by opening one of the chargetransfer gates (TG1−4 ). Fig. 2 shows the cross-sectional view along line x–x shown on the left side of Fig. 1(a). The pinned photodiode surrounded by the p-well eliminates the dark current generated at the STI edge. The arrangement of in-pixel transistors and photodiodes is optimized by ring-gate shared design. The potential distribution of the STI-less shared pixel is shown in Fig. 3. The figure also shows that the potential barrier between

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Fig. 3.

Fig. 1. Schematic diagrams of the STI-less shared pixel (2 × 2). (a) Pixel layout. (b) Equivalent circuit diagram.

Fig. 2.

Cross-sectional view of the STI-less shared pixel.

adjacent pinned photodiodes is high enough to prevent the occurrence of crosstalk, even though it does not use the STI structure. B. Column-Parallel Readout Circuit Scientific applications of solid-state imagers strongly require very low temporal noise, wide dynamic range, and very high gray scale resolution as well as an optimized pixel structure. A column-parallel analog-to-digital converter (ADC) [10]–[16] in CMOS imagers is one of the important techniques for satisfying these requirements. To read image signals from an image array with low noise and wide

Potential distribution of the STI-less shared pixel.

Fig. 4. Block diagram and its timing diagram of the folding-integration/cyclic ADC.

dynamic range, a column-parallel folding-integration/cyclic ADC is used [17]. Fig. 4 shows a simplified block diagram and timing diagram of the column-parallel readout circuit. The circuit consists of an analog core for the ADC and the digital parts for calculation. The analog core is used for both the foldingintegration and the cyclic ADCs. This core is composed of a switched-capacitor (SC) amplifier, two capacitors, two comparators for a 1.5b sub-ADC, and a 1.5b digital-to-analog converter for reference subtraction. Briefly, in the folding-integration ADC mode, the pixel outputs are sampled multiple (M) times and the sampled signals are integrated by the SC integrator after the reset operation for initialization. Initialization enables precise digital correlated double sampling by eliminating the input dependence of the settling error resulting from the residual charges in a short sampling period. Then the amplified and folded analog output is converted to digital output in the cyclic ADC mode. More details concerning the operation of this column readout circuit are given in [17] and [18]. III. E XPERIMENTAL R ESULTS AND D ISCUSSION A CMOS image sensor using the STI-less shared pixel design is implemented with a 0.18-μm standard CMOS

SEO et al.: LOW DARK LEAKAGE CURRENT HIGH-SENSITIVITY CMOS IMAGE SENSOR

Fig. 7.

Fig. 5.

Fig. 6. level.

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Linearity of the proposed imager as a function of light intensity.

Prototype chip micrograph.

Measured random and photon shot noises as a function of signal

technology with pinned photodiodes. The die micrograph of the fabricated sensor chip is shown in Fig. 5. The chip consists of a pixel array (including the proposed pixel subarray), a column-parallel folding-integration/cyclic ADC [17], [18] for low-noise readout, a vertical shift register, a horizontal shift register, and reference voltage and current blocks. Fig. 6 shows the noise as a function of signal level. In this result, 1 least significant bit (LSB) corresponds to 15 μV with 1 V reference at 16-bit resolution. The measurements are performed at room temperature with an IR cut filter (BG-40, t = 1 mm). The conversion gain, obtained from the cross point of the sensor output and the photon shot noise, is 22.9-μV/e−. The STI-less shared pixel has relatively low conversion gain because four pixels share an FD node and the area of the FD region is relatively large. However, this conversion gain can be improved by layout optimization. The linearity of the prototype imager as a function of light intensity is shown in Fig. 7. For accurate measurements, a light source equipped with a collimator and dedicated for image sensor

Fig. 8. Cumulative probability of the pixel dark current and its median value at 60 °C (M = 16).

evaluation was used. The proposed image sensor achieved a high sensitivity of 144.6 ke− /lx · s with a high fill factor. Fig. 8 shows the cumulative probability (CP) of the pixel dark current at 60 °C. The dark current of the STI-less shared pixel is dramatically reduced compared with a conventional APS, which has the STI structure for pixel isolation. The dark current of the STI-less shared pixel is measured to be 104.5 e− /s/pixel (median), which corresponds to a current density Jdark− proposed of approximately 30 pA/cm2 . In contrast, the conventional test pixel has a large dark current of 2450 e− /s/pixel (median), corresponding to Jdark− conventional of approximately 700 pA/cm2 . Both pixels have the same pixel size of 7.5 × 7.5 μm2 and are fabricated by the same process. Fig. 9 shows the temporal noise characteristic of the CMOS image sensor with the STI-less shared pixel. Undesirable large noises might be generated by the imperfections in the gate oxide and interface defects located at the STI. In the proposed imager, however, no STI structure is added around the source follower amplifier of the pixel. Therefore, this imager

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TABLE I P ERFORMANCE S UMMARY

Fig. 9. Temporal noise characteristic of the proposed image sensor (M = 16).

QE of 68% at 600 nm (with microlens). This is a sufficiently good spectral response for scientific applications [19]–[21]. Table I summarizes the performance of the prototype chip. IV. C ONCLUSION We developed and evaluated a low dark current and highly sensitive CMOS image sensor with an STI-less shared pixel design. By sharing the in-pixel transistors, such as the RT, the SL transistor, and the SF amplifier, each pixel layout was optimized. Therefore, the proposed imager has a high sensitivity of 144.6 ke− /lx · s. The imager with the STI-less shared pixel structure achieved a relatively low dark current of approximately 30 pA/cm2 at 60 °C (104.5 e− /s/pixel when the pixel pitch is 7.5 μm) compared with that of a conventional APS, because the proposed APS does not have the in-pixel STI structures for pixel isolation. In addition, the proposed imager exhibited a satisfactory spectral response at 400 to 900 nm, including a high peak QE of almost 70% at 600 nm, even when using a front-side illumination method. Fig. 10. Measured spectral characteristic of the STI-less shared pixel array (at 400 to 1100 nm). (a) Spectral sensitivity. (b) Monochrome QE.

R EFERENCES

helps to suppress anomalously large noise. The maximum measured noise (CP = 7 × 10−5 , 410 μVrms ) for the STI-less shared pixel is only four times larger than the median value (CP = 0.5, 94 μVrms ) of the noise distribution. In contrast, the maximum noise (1660 μVrms ) for the conventional pixel [17] is more than 13 times larger than its median value (122 μVrms ) under the same condition (M = 16). Thus, the temporal noise reduction effect of the STI-less shared pixel is also demonstrated by this result. The monochrome quantum efficiency (QE) curve (at 400 to 1100 nm) measured for the STI-less shared pixel array is shown in Fig. 10. The STI-less CMOS imager achieves a peak

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Shoji Kawahito (S’86–M’88–SM’00–F’09) received the Ph.D. degree from Tohoku University, Sendai, Japan, in 1988. He has been a Professor with the Research Institute of Electronics, Shizuoka University, Shizuoka, Japan, since 1999. His current research interests include CMOS imaging devices, sensor interface circuits, and mixed analog/digital circuits designs.

Min-Woong Seo (S’11–M’13) received the Ph.D. degree from Shizuoka University, Shizuoka, Japan, in 2012. He has been the Imaging Devices Laboratory, Shizuoka University, since 2012, as a JSPS Research Fellow. His current research interests include CMOS imaging devices and mixed analog/digital circuit design.

Nobukazu Teranishi (F’10) has been with NEC, Tokyo, Japan, Panasonic, Kadoma, Japan, University of Hyogo, Kobe, Japan, and Shizuoka University, Shizuoka, Japan, for 35 years, where he has developed imagers and cameras. Mr. Teranishi serves as the President of the International Image Sensors Society. He was a recipient of the National Invention Awards and the J. J. Ebers Award.

Keita Yasutomi (S’08–M’11) received the Ph.D. degree from Shizuoka University, Shizuoka, Japan, in 2011. He is currently an Assistant Professor with the Research Institute of Electronics, Shizuoka University. His current research interests include high-speed CMOS image sensors and low-noise pixel design.

Keiichiro Kagawa (M’10) received the Ph.D. degree from Osaka University, Suita, Japan, in 2001. He has been an Associate Professor with Shizuoka University, Shizuoka, Japan, since 2011. His current research interests include CMOS image sensors and their biomedical applications.