Meng Zhao, Wengao Lu, Zhongjian Chen, Tingting Zhang, Feng Wu, Yacong Zhang and Dahe Liu. National Key Laboratory of Science and Technology on ...
A Low-Noise Switched-Capacitor Interface for a Capacitive Micro-Accelerometer Meng Zhao, Wengao Lu, Zhongjian Chen, Tingting Zhang, Feng Wu, Yacong Zhang and Dahe Liu National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Institute of Microelectronics Peking University Beijing, China Email: [zhaomeng2615, wglu]@pku.edu.cn
Abstract—This paper presents a low-noise single-ended openloop switched-capacitor interface circuit in 0.35µm CMOS technology for a comb structure micro-accelerometer. Using correlated double sampling, the low-frequency noise of the charge sensitive amplifier and the gain stage is suppressed, whereas the noise of the sensor charging reference voltage and the sampleand-hold circuit which follows the gain stage contributes considerably to the total output noise. In order to optimize the noise performance, an on-chip reference voltage generator and a dualsample-and-hold circuit are designed. A detailed noise analysis of the two blocks is also presented. The fabricated prototype interface circuit achieves a measured capacitive sensitivity √ of 734mV/pF with an input equivalent noise floor of 0.41aF/ Hz and a dynamic range of 119.93dB over a 200Hz bandwidth at 1MHz sampling frequency.
I.
Introduction
High-resolution MEMS accelerometers are demanded in a number of high-performance applications such as inertial navigation systems, earthquake prediction, and space microgravity measurements [1]. As a widely used accelerometer, capacitive micro-accelerometer has the advantages of high sensitivity, good dc response and noise performance, low drift and temperature sensitivity, and a simple structure [1]. Interface circuits for capacitive accelerometers can be divided into openloop [2]–[8] and closed-loop interfaces [9], [10]. Compared with the closed-loop counterpart, the main advantage of an open-loop accelerometer is simple implementation as well as ratiometric output [7]. Moreover, benefiting from the simple structure, an open-loop accelerometer can achieve good noise performance more easily. Many high-performance open-loop micro-accelerometers have been published during the last ten years [2]–[8]. However, the resolution of these accelerometers are not high enough to achieve dynamic range of around 120dB due to the small sensing capacitance [2], [3], the tradeoff with power dissipation [4]–[6], [8], or the complicated structure for some special functions [7], [8]. In an effort to achieve high resolution, this paper presents an open-loop switched-capacitive interface circuit for a comb structure micro-accelerometer which uses correlated double sampling (CDS) to suppress low-frequency noise, an on-chip reference voltage generator to reduce sensor charging reference voltage (SCRV) noise, and a dual-sampleThis work is supported by National Natural Science Foundation of China (Grant No. 61473007).
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TABLE I.
Sensing Element Parameters
Parameter
Symbol
Value
FS R
±25g(±2.9pF)
Sensing capacitance
Cs
18.75pF
Proof mass
m
1.45mg
∆C/∆a
116 f F/g
BW
200Hz √ 0.63µg/ Hz
Full scale range
Capacitance sensitivity Bandwidth Brownian noise floor
T NEA
and-hold (DS&H) circuit to acquire low-noise discrete-tocontinuous-time conversion. The rest of this paper is organized as follows. The system architecture is depicted in Section II. Designed on-chip reference voltage generator and DS&H circuit as well as the corresponding noise analysis are detailed in Section III and the measurement results of the implemented prototype are presented in Section IV. Conclusions are drawn in Section V. II.
System Architecture Description
The parameters of the comb structure sensing element used in the front-end design are given in Table I. Because of the heavy mass of the bulk-micromachined sensing element, it can be safely assumed that the Brownian noise does not limit the system noise performance and owing to the large sensing capacitance, the noise of the interface circuit can be reduced at the expense of higher power dissipation. The bandwidth of the accelerometer system is typically 200Hz and the noise in low-frequency range should be considered carefully. In bulk-micromachined accelerometers, the low-frequency noise of the interface circuit is dominant which can be divided into three categories: the flicker noise of the interface circuit, the folded thermal noise caused by under-sampling and the supply noise injected in the circuit [7]. Generally, to suppress the flicker noise of the front-end circuit, chopper stabilization (CS) is preferred in continuous-time voltage (CTV) sensing [3], [6] and CDS [2], [4], [7], [9], [10] or both CDS and CS [5], [8] are used in the switched-capacitor (SC) charge integration method. High sampling frequency is preferred to suppress the folding noise [3], [4], [9] and on-chip reference voltage generator is used to control the interference of the supply [5], [8], [10].
Fig. 1.
Schematic and timing of the accelerometer system
In this work, SC sensing with CDS is employed to reduce the flicker noise and cancel the dc offset, and 1MHz sampling frequency is chosen to suppress noise folding. Fig. 1 shows the schematic and timing of the accelerometer system. Differential capacitance of the sensing element is sensed by applying a pair of voltage pulses which are opposite in phase to the top and bottom plate respectively. The amplitude of the voltage pulse is made as large as possible to achieve a high signal-to-noise ratio (SNR) and the reference voltage of the two pulses are precisely generated on chip to obtain high output stability. The charge sensitive amplifier (CSA) and the gain stage (GAIN) are reset during the reset phase and the output of CSA which contains the error signal resulting from dc offset as well as the low-frequency noise of the amplifier and the KT/C noise as well as the charge-injection error of the switch φ2 is first sampled and amplified by gain stage at the end of the sample phase. At the beginning of the readout phase, the reference voltage Vbp and Vbn applied to the two stationary plates are reversed and the output of CSA is sampled and amplified again with the error signal of the first sample subtracted. The output of the gain stage during the readout phase is given by CG1 Vbp − Vbn ∆C (1) Vgain = CG2 CF where CG1 , CG2 and C F is the capacitance shown in Fig. 1, and ∆C is the differential capacitance of the sensing element. Meanwhile, the proposed DS&H circuit which will be detailed in the next section samples the output of the gain stage and converts the discrete signal to the continuous-time one with minimum noise injected. In addition, the temperature stability of the accelerometer can be compensated dynamically by using FPGA and on-chip temperature sensor to adjust the designed offset and gain compensation capacitor arrays in the CSA and gain stage. III.
Circuit Design
As the noise performance of the analog front-end, namely the CSA and gain stage, is optimally designed, the noise of the sensor charging reference voltage and the sample-and-hold circuit becomes the obstacle to the final goal of achieving high dynamic range of 120dB. In order to address this problem, an
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Fig. 2.
Schematic of the on-chip reference voltage generator
on-chip reference voltage generator and a dual-sample-andhold circuit are designed and the noise analysis of these blocks is also presented. A. The on-chip reference voltage generator By reversing the reference voltage Vbp and Vbn which are applied to the two stationary plates, the sense of differential capacitance is performed. Therefore, the output signal of the interface circuit will be spoiled by the noise on these reference voltages directly which is known as sensor charging reference voltage (SCRV) noise [9]. The low-frequency noise components and wide-band noise components of the SCRV noise folded to the baseband easily become one of the main noise sources of the whole system. Since the interference on the PCB is usually large and unpredictable, designing an onchip reference voltage generator may be a good choice to limit the SCRV noise. Fig. 2 shows the on-chip reference voltage generator designed in this work. The three reference voltages Vbp , Vre f and Vbn are generated based on bandgap reference voltage Vbg . By utilizing the fact that Vbp always performs pull-up and Vbn always performs pull-down, Vbp and Vbn are generated in the same current path with two resistors shared, which reduces the noise sources and power consumption. In order to ensure the stability, limit the bandwidth of the noise and increase
the charging speed by utilizing the charge sharing, a 10µF capacitor is set at the output pad of each reference voltage on the PCB. The two-sided power spectrum density (PSD) of the interface output noise resulting from the SCRV noise can be represented by the equation !2 C s CG1 (π fu T s ) S rw+ ( f ) sinc2 (π f T s ) S out r ( f ) = C F CG2 (2) !2 i ∆C CG1 h 2 (π fu T s ) S rw− ( f ) + S r f − ( f ) sinc (π f T s ) + C F CG2 where fu is the unity gain frequency of CSA amplifier, T s is the sampling period, S rw+ ( f ) is the wide-band noise component of S r+ ( f ), the PSD of Vbp + Vbn , S rw− ( f ) and S r f − ( f ) are the wide-band and flicker noise components of S r− ( f ), the PSD of Vbp − Vbn , respectively. S r+ ( f ) and S r− ( f ) are given by S r+ ( f ) = (2 + k1 k2 + k1 )2 S bg ( f ) + k22 S r4 ( f ) + S r3 ( f ) + [(1 + k1 ) (1 + k2 )]2 S a1 ( f ) + [k1 (1 + k2 )]2 S r2 ( f ) + (1 + k2 )2 S a2 ( f ) + S r1 ( f ) + (1 − k2 )2 S a3 ( f ) h i S r− ( f ) = [k1 (1 + k2 )]2 S bg ( f ) + S r2 ( f ) + k22 S r4 ( f ) +S r3 ( f ) + [(1 + k1 ) (1 + k2 )]2 S a1 ( f ) + (1 + k2 )2 S a2 ( f ) + S r1 ( f ) + S a3 ( f )
(3)
(4)
where k1 = R1 /R2 , k2 = R3 /R4 , S bg ( f ) is the PSD of Vbg , S a1 ( f ) ∼ S a3 ( f ) are the PSD of the three amplifiers in Fig. 2, and S r1 ( f ) ∼ S r4 ( f ) are the PSD of the four resistors in Fig. 2. In the first term of S out r ( f ), low-frequency component of S r+ ( f ) is high-pass filtered by the CDS operation with the folded wide-band component left, whereas in the second term of S out r ( f ), both the low-frequency component and folded wide-band component of S r− ( f ) are remained. The simulation result shows that owing to the compact structure with noise sources reduced and the limited bandwidth by the large capacitor on the PCB, finally the flicker noise component of S bg ( f ) is dominant in SCRV noise. B. The dual-sample-and-hold circuit An open-loop SC accelerometer with analog output usually needs an S&H circuit to convert the discrete signal to the continuous-time one. The S&H circuit which consists of a sampling switch, a holding capacitor and an amplifier configured as a buffer is often used in such accelerometers [4], [7]. However, the low-frequency noise of a buffer-type S&H circuit cannot be suppressed and directly contributes to the overall noise performance. Especially in an ultra-low noise accelerometer system with dynamic range of about 120dB and bandwidth of 0∼200Hz, the low-frequency noise of the S&H circuit becomes a considerable noise source. In order to acquire low noise in low-frequency bandwidth, a dual-sample-and-hold circuit is proposed which has two switched-capacitor S&H circuits sampling and holding alternately. The schematic and timing of DS&H circuit are shown in Fig. 1. When φ4 = 0, the upper S&H circuit is active and the output of the lower counterpart is connected to the system output and when φ4 = 1, the roles of the two S&H circuits are reversed. The total sampling period of DS&H circuit is T s and the sampling period of each S&H circuit is 2T s .
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(a)
(b)
Fig. 3. The equivalent circuits of the upper S&H circuit for noise calculation. (a) when φ5 = 1. (b) when φ5 = 0.
To analyze the noise performance of DS&H circuit, Fig. 3 can be used which depicts the equivalent circuits of the upper S&H circuit in Fig. 1 drawn for the φ5 = 1 and φ5 = 0 phases. Using the calculation method in [11], the output two-sided PSD of the DS&H circuit is given by S DS &H ( f ) = 2kT (2π fu T s ) (RS 1 + RS 2 2kT (RS 3 + RAEQ ) (5) +RAEQ )sinc2 (2π f T s ) + 1 + ( f / fu )2 where k is the Boltzmann’s constant, T is the absolute temperature, fu is the amplifier unity gain frequency of DS&H circuit, RS 1 ∼ RS 3 are the on-resistance of the switches S 1 ∼ S 3 in Fig. 3, and RAEQ is the hypothetical resistor which would generate as much thermal noise as the amplifier’s. The first term of S DS &H ( f ) is caused by the sampling process at the end of the phase φ5 = 1 and the second term is the wide-band direct noise resulting from the switch S 3 and the amplifier. The PNOISE simulation results of the output noise PSD of a buffer-type S&H circuit and a DS&H circuit which use the same amplifier, holding capacitor and switch are shown in Fig. 4. It is obvious that the DS&H circuit has much less lowfrequency noise than the buffer-type S&H one, whereas the noise floor of the DS&H circuit is a little higher due to the doubled sampling period. However, the increased wide-band noise can be filtered by a following low-pass filter. Moreover, it should be noted that the buffer-type S&H circuit needs a rail-to-rail input amplifier which may have more noise than the ordinary one and the charge injection of the CMOS switch will decrease the system linearity. Although the DS&H circuit has the improved noise performance at the expense of the increased power consumption and chip area, it is still a good choice for low-noise applications.
Fig. 4.
The PNOISE simulation results of the two kinds of S&H circuits
Fig. 5.
The micrograph of the interface chip
Fig. 7. The unfiltered output noise of the interface circuit only at zero input
performance has been achieved. The measured input √ equivalent noise floor of the interface circuit only is 0.41aF/ Hz and the corresponding dynamic range of the interface is 119.93dB in 2-200Hz bandwidth for ±2.9pF input range. Acknowledgment The authors wish to thank Su Weiguo, Zhang Wei, and Li Song for fabricating the sensing elements. Fig. 6.
References
The measured sensitivity of the open-loop interface circuit [1]
IV.
Measurement Results
[2]
The interface chip was designed in 0.35µm 2P4M CMOS process. Fig. 5 shows the fabricated circuit which has an area of 2.5mm × 5mm and consumes 37.86mA at a nominal supply voltage of 5V. It has an adjustable sensitivity between 0.572 and 1.032V/pF using digital trimmable capacitor arrays. Functionality test without the sensing element was performed by adjusting the offset compensation capacitor array from the nominal value -1pF to 1pF. Fig. 6 shows a measured sensitivity of 734mV/pF where the offset of the interface circuit was calibrated. The unfiltered output noise of the interface circuit only which is shown in Fig. 7 was measured at zero input by using an Agilent 35670A dynamic signal analyzer which was powered by a storage battery. From the measured √ output, the interface circuit can resolve about 300nV/ Hz, √ namely 0.41aF/ Hz, and it is believed that the peak at 0∼2Hz is caused by the measurement instrument. The interface circuit has a dynamic range of 119.93dB in 2∼200Hz bandwidth for ±2.9pF input range after being calibrated with the intrinsic noise of the measurement instrument. The measured dynamic range is close to the PNOISE simulation result of 122.96dB. V.
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[5]
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[7]
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[9]
Conclusion
In this paper, a low-noise single-ended open-loop switchedcapacitor accelerometer interface circuit which was implemented in the 0.35µm CMOS technology has been presented. The analytical and simulated results show that the lowfrequency noise of the analog front end is suppressed by using CDS, whereas the noise of the SCRV and the S&H circuit becomes considerable. With the on-chip reference voltage generator and DS&H circuit analyzed and designed, good noise
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