A Low Noise Wide Dynamic Range CMOS Image ... - IEEE Xplore

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IEEE SENSORS JOURNAL, VOL. 13, NO. 8, AUGUST 2013

A Low Noise Wide Dynamic Range CMOS Image Sensor With Low-Noise Transistors and 17b Column-Parallel ADCs Min-Woong Seo, Member, IEEE, Takehide Sawamoto, Tomoyuki Akahori, Tetsuya Iida, Taishi Takasawa, Keita Yasutomi, Member, IEEE, and Shoji Kawahito, Fellow, IEEE

Abstract— An extremely low temporal noise and wide dynamic range CMOS image sensor is developed using lownoise transistors and high gray-scale resolution (17b) foldingintegration/cyclic analog-to-digital converter (ADC). Two types of pixel are designed. One is a high conversion gain (HCG) pixel with removing the coupling capacitance between the transfer gate and the floating diffusion, and the other is a pixel for wide dynamic range (WDR) CMOS imager with a native transistor as a source follower amplifier. The CMOS image sensor that is in combination with the proposed pixels and the high performance column ADC has achieved a low pixel temporal noise of 1.1 e− rms , a wide dynamic range of 87.5 dB with the video rate operation (30 Hz) and the vertical fixed pattern noise of 1.08-µVrms. The implemented HCG CMOS imager and WDR CMOS imager using 0.18 µm technology have the pixel conversion gain of 73.2- and 22.8-µV/e− , respectively. Index Terms— CMOS image sensor (CIS), wide dynamic range, high conversion gain, low noise, folding-integration/cyclic analog-to-digital (A/D) converter (ADC). Fig. 1.

I. I NTRODUCTION

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N APPLICATIONS such as surveillance and microscopy for bioimaging, the low-noise [1], [2] and wide dynamic range imagers [3]–[5] are favored for their ability to reconstruct an image that covers a wide illumination range from various light emitting objects. The random telegraph signal (RTS) noise of in-pixel amplifiers is a dominant noise at low frequencies. Under the low-illumination conditions, the temporal noise is determined by 1/ f noise and RTS noise because these noises are very difficult to eliminate. One of solutions for reducing these noises is to use a buried-channel Manuscript received February 2, 2013; revised May 8, 2013; accepted May 11, 2013. Date of publication May 21, 2013; date of current version July 2, 2013. This work was supported in part by the Knowledge Cluster Initiative and Grant-in-aid for Scientific Research (A) of the Ministry of Education, Culture, Sports, Science, and Technology and the JSPS International Training Program. The associate editor coordinating the review of this paper and approving it for publication was Prof. Weileun Fang. M.-W. Seo, T. Takasawa, and K. Yasutomi are with the Research Institute of Electronics, Shizuoka University, Hamamatsu 432-8011, Japan (e-mail: [email protected]; [email protected]; kyasuidl.rie.shizuoka.ac.jp). T. Sawamoto, T. Akahori, and T. Iida are with Brookman Technology, Inc., Hamamatsu 432-0936, Japan (e-mail: [email protected]; takahori@ brookmantech.com; [email protected]). S. Kawahito is with the Research Institute of Electronics, Shizuoka Univeristy, Hamamatsu 432-8011, Japan, and also with Brookman Technology, Inc., Hamamatsu 432-0936, Japan (e-mail: [email protected]). Digital Object Identifier 10.1109/JSEN.2013.2264483

Block diagram of the whole chip.

transistor [6]. If the imperfection of the gate oxide has to be accepted, the alternative will have to take the conducting carriers away from the Si-SiO2 interface. In this case, however, the additional process is inevitable to make the buried-channel under the ordinary pixel structure [7]. A high conversion gain is also enabled to lower the readout noise and achieve excellent image capturing performance at the low light intensity. In this paper, a new type of the pixel structure using lownoise transistor such as a native transistor [8], [9] is developed for wide dynamic range (WDR) imager. In addition, a pixel structure for reduced floating diffusion (FD) node capacitance in the pixel for high conversion gain (HCG) CMOS imager is also introduced and demonstrated with video rate operation of 30 Hz. The rest of this paper is organized as follows. Section II describes the architecture of the proposed pixels including the 17-b column-parallel ADC. Section III shows the simulation and experimental results of the prototype imagers. Section IV gives the conclusions. II. A RCHITECTURE OF I MAGERS Fig. 1 shows a block diagram of the whole chip. It consists of a pixel array (including the two-type pixels for HCG and WDR imagers), a two-stage column-parallel foldingintegration/cyclic ADC, an analog and digital correlated

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SEO et al.: LOW NOISE WIDE DYNAMIC RANGE CMOS IMAGE SENSOR

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Fig. 3.

Fig. 2. Cross section of the proposed pixel for achieving the high conversion gain and its potential distribution.

double sampling (CDS), a low-voltage differential signaling (LVDS), a vertical and horizontal shift registers, a reference block, a timing generator, and serial-parallel interface block. The HCG and WDR imagers are based on a high performance column-parallel ADCs [10], [11] as illustrated in this figure. A. High Conversion Gain Imager The performance of CMOS image sensors has been analyzed and characterized in electrons or photons. However, the output of pixels is always an analog signal which in most cases is an analog voltage. Thus, there is an important process that converts the light signal into an electronic signal inside the pixels. Conversion gain is the parameter which represents the efficiency of this process. The linearity and uniformity of the pixel response, light sensitivity, and the pixel random noise are all influenced by its value and distribution. Especially we have designed the particular FD structure in the pixel for increasing the conversion gain to take care of the sensor’s noise. An active pixel includes a photodiode (photo-sensitive element) formed in a semiconductor substrate. A transfer transistor is formed between the photodiode and the FD and selectively operative to transfer a signal from the photodiode to the FD node. Generally, the FD is formed from an n-type implant, and the conversion gain is controlled by the FD node capacitance. An HCG imager provides the increased sensitivity and low read noise for low-light scenes, relatively, as optimizing the FD node structure. Fig. 2 shows the cross-sectional structure and the potential diagram of the proposed pixel structure for achieving high conversion gain. As putting a fully depleted diode structure between the transfer gate (TG) and the FD, the coupling capacitance which is

Pixel layout of the HCG imager.

generated between the TG and the FD is minimized, because the proposed pixel structure allows us to separate interface of two components. As a result, high conversion gain is achieved by the minimized FD node capacitance and the noise performance is improved by removing one of noise source from power supply. The implemented pixel layout of the HCG imager is shown in Fig. 3. This is designed by 0.18-μm standard CMOS technology with the pinned photodiode. B. Wide Dynamic Range Imager As mentioned above, a dynamic range is also an important performance factor for image sensors. Dynamic range quantifies the sensor’s ability to adequately image both high lights and dark shadows in a scene. CMOS image sensors generally suffer from high read noise and non-uniformity, resulting in lower signal to noise ratio (SNR) and dynamic range than CCDs. Several techniques and architectures such as well capacity adjusting [12], multiple capturing [3], [4], spatially varying exposure [13], time-to-saturation [14], [15], and logarithmic sensor [16], [17] have been proposed for extending image sensor dynamic range. However, the reported techniques are not sufficient for the linear image sensors. Authors have already developed the high performance readout circuit [10], [11] for the linear image sensor and this circuit can improve the dynamic range as well as the noise performance of the imager. But the in-pixel noise is difficult to eliminate, e.g. 1/ f or RTS noise which are usually generated by a source follower amplifier in a pixel, even though this readout circuit was used. Particularly, the RTS noise [18], which is caused by trapping of an individual carrier, due to a single active trap in the oxide, or by a scattering in the vicinity of the inversion layer of the device, becomes the most critical issue. Therefore we used a native transistor as the in-pixel amplifier for reducing this noise. A native transistor (or natural transistor) which is formed in a lightly-doped substrate is one of the MOSFETs. Most common is the n-channel native transistor. In the native MOSFET, the vertical electric field is smaller and the channel has a little broader depth. In addition, a number of charge traps on the silicon surface of the native transistor are smaller

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Fig. 4.

Cross section of the native transistor in CMOS process.

than that of the ordinary transistor in p-well (or n-well). These features of the in-pixel native transistor improve the noise performance, particularly due to RTS noise. In addition, the linearity of the native transistor as in-pixel source follower is relatively better than that of the ordinary transistor [see Fig. 11]. This makes it possible to reduce the vertical fixed pattern noise (vFPN) by minimizing the nonlinearity of the inpixel source follower. Fig. 4 shows the simple cross section of the native transistor in comparison with the transistor in wells. Native transistors are transistors that lie directly in a lightlydoped substrate, whereas well transistors are transistors that lie in highly-doped wells, relatively. In this case, the native transistor has n-type source and drain, and the well transistor has p-type source and drain. The channel formed by the native transistor in the p-type substrate will be n-channel. Fig. 5 shows a schematic diagram of the pixel structure with the native transistor for achieving the wide dynamic range and low noise. An extra capacitor (MOS cap.) is added to the FD region for extending the dynamic range by decreasing the conversion gain on purpose. C. Column-Parallel ADC Scientific applications of solid-state imagers strongly require very low temporal noise (80dB), and very high gray scale resolution (>16b) as well as optimized pixel array. A column-parallel ADC in CIS is one of key techniques to meet these requirements. Recently, the delta-sigma () ADC was reported [19]. It has an attractive feature that low temporal noise and high resolution can be simultaneously attained by an oversampling technique. Particularly, a 2nd order -ADC can dramatically reduce the ADC’s quantization noise by the noise shaping and the ADC architecture’s complexity is also similar level compared with that of the proposed ADC. For very high resolution, however, a number of samplings for a pixel output, e.g., more than 512 samplings for 17b, is required. In contrast, the folding-integration/cyclic ADC requires only 44 samplings for attaining 17b. As a result, the proposed column-parallel ADC [10], [11], [20], [21] is relatively high speed, low-noise, and high gray-scale resolution CMOS imagers, particularly for scientific applications. A timing diagram of the one horizontal period is shown in Fig. 6. The horizontal scanning time is 32.1 μs at a frame rate of 30 fps with 1028 vertical lines. Labels RT and TX represent control signals for the reset transistor and for the

Fig. 5. Schematic diagram of the proposed pixel for achieving the wide dynamic range.

transfer gate in the pixel, respectively. A two-stage foldingintegration/cyclic ADC repeats the same configurations at the reset phase and signal phase for obtaining the each digital code, because obtained digital codes which are for the reset and the signal levels are used for cancelling the reset noise through the digital CDS operation. Each phase (reset or signal) has roughly three-step as follows [see Fig. 6]: 1) sampling and amplifying operations by two-stage FI/cyclic ADC, 2) keeping the counted number by FI-ADC and digital codes by the cyclic ADC (first and second stages, respectively) in each register, 3) transferring the final data to the output buffer (LVDS) by the horizontal scanner. In this case, the first-stage and second-stage analog cores perform the first four cycles and the remaining eight cycles of the cyclic A/D conversion, respectively. Especially, the separated work by the two-stage ADC allows us to achieve the background operation and makes it possible to improve the sensor’s operation speed. Fig. 7 shows a block and circuit diagrams of the columnparallel two-stage folding-integration/cyclic ADC [11]. The proposed imagers (for HCG and WDR) are based on this column-parallel ADC which is composed of two analog cores for the ADCs (first and second stages), two comparators for a 1.5b sub-ADC, a 1.5b digital-to-analog converter (DAC) for reference subtraction, a digital counter for folding-integration ADC, and the registers for the cyclic ADC. In the foldingintegration ADC mode, only one comparator is used for a 1b sub-ADC and DAC because this is necessary to control the output signal range of the folding integration to be the same as that of the cyclic ADC. The detailed operation of the folding-integration/cyclic ADC is explained in [10], [11]. Briefly, in the folding-integration ADC mode, the pixel outputs are sampled multiple (M) times and the sampled signals are integrated over in a switched-capacitor (SC) integrator after the reset operation for initialization which enables the precise digital CDS by eliminating an input dependence of the settling error resulting from the residual charges in a short sampling period. And then the amplified and folded analog output is converted to digital in the cyclic ADC mode. In these circuit operations, the folding number is measured by a counter and the digital code of the counter output is used for the MSBs (most significant bits) side of the final digital output.


Fig. 6.

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Timing diagram of two-stage folding-integration/cyclic ADC.

(a)

Fig. 8.

(b)

Fig. 7. Two-stage folding-integration/cyclic ADC. (a) Block diagram. (b) Circuit diagram.

The digital code by the cyclic ADC is used for LSBs (least significant bits) side. Using these digital codes for, the digital CDS operation is performed on chip to achieve greatly reduced the vFPN. This architecture helps to realize very low-noise, wide dynamic range, and high gray-scale (17 bits) resolution CMOS image sensors. III. S IMULATION AND M EASUREMENT R ESULTS A CMOS image sensor with two-type special pixels for obtaining high conversion gain and wide dynamic range is

Chip micrograph of the proposed imagers.

implemented with 0.18-μm standard CMOS technology with pinned photodiode. The die micrograph of the fabricated sensor chip is shown in Fig. 8. As mentioned in session II, the whole pixel array consists of three-type imagers and each pixel array has its own distinct characteristics. Among them, type 2 and type 3 are for the HCG and WDR imagers, respectively. Fig. 9 shows the measured noise histogram of the HCG imager. A very low temporal noise of 1.1e− rms is obtained with M = 32 and ADC reference voltage VR of 1.0 V. In the condition of M = 32 and ADC reference voltage VR = 2.0 V, the measured noise level is 1.17e− rms which is slightly larger than the measurement with the setting of VR = 1.0 V. The HCG imager has good noise performance because of the high conversion gain. However the tailing part of noise distribution of the HCG imager is relatively longer than that of the WDR imager. Fig. 10 shows the comparison of the cumulative probability (CP) of the measured noises between the HCG and WDR imagers with M = 32 and VR = 2.0 V. The noise can be analysed well by the cumulative noise histogram, particularly, the large noise. Because cumulative probability plot shows the existence probability of the noisy pixels (or number of noisy pixels). As shown in this measurement result, the anomalously large RTS noise (the part shown in dotted line) is dramatically

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Fig. 11. Simulation result of the linearity of an in-pixel source follower amplifier using an n-ch. native MOSFET. Fig. 9.

Measured noise histogram of the HCG imager.

Fig. 12. Column-wise plot of the measured vFPN of WDR imager (Type 3). Fig. 10. Comparison of noise characteristic between the HCG and WDR imagers (VR = 2.0 V).

decreased by the effect of used native MOSFET compared with that of the HCG imager which uses the n-channel MOSFET in the p-well as an in-pixel amplifier. In other words, the native MOSFET as in-pixel source follower amplifier has a significant noise reduction effect for large noise pixels such as RTS noise [18], [22]–[24]. For example, the maximum noise amplitude where CP = 1 × 10−5 is 247.3 μVrms if n-channel MOSFET is used. By using the native MOSFET, the maximum noise is reduced to 121.5 μVrms . In addition, a very wide intra-scene dynamic range of 87.5 dB is obtained, although the measured noise level is increased in this case (3.7e− rms , median at VR = 2.0 V) because of the low conversion gain. Fig. 11 shows the simulation result of a linearity of the n-ch. native MOSFET as the in-pixel source follower amplifier. It has high gain (0.93 V/V) and the wide linear range. Fig. 12 shows the measurement result of the vFPN of the WDR imager. Extremely low vFPN is achieved by the hybrid (analog and digital) CDS and high-resolution ADC of 17-bit. And the n-ch. native transistor which uses as an in-pixel amplifier also helps to achieve the very low vFPN because it has good linearity. The measured vFPN under the dark condition is 1.08-μVrms and 5.14-μVp−p at the video rate operation (30fps). For measuring this vFPN, the influence of the temporal random noise is suppressed by averaging the image data (1000 rows × 100 frames). Hot pixels larger than

TABLE I P ERFORMANCE S UMMARY OF THE I MAGERS Parameter Technology Chip size Power supplies Number of effective pixels Pixel type Pixel size Fill factor ADC resolusion Input referred noise (Type 2) Vertical FPN Conversion gain Dynamic range (Type 3) Frame rate Power consumption

Value 0.18-μm 1P4M CIS process 12.0 (H) mm × 12.0 (V) mm 1.8V (Digital), 3.3V (Analog, Digital) 100 (H) × 1028 (V) (Type 2 for HCG) 1000 (H) × 1028 (V) (Type 3 for WDR) 4-transistor APS with pinned photodiode 7.1 μm × 7.1 μm 45% (without microlens) 17 bits (Max.) 1.10 e− rms (# of samplings = 32,VR = 1V) 1.17 e− rms (# of samplings = 32,VR = 2V) 1.08 μVrms , 5.14 μVp−p 73.2 μV/e− (Type 2) 22.8 μV/e− (Type 3) 87.5 dB (# of samplings = 32, VR = 2V) 30 fps (# of samplings = 32) 466.3 mW

300 LSB in the pixel array (Type 3) are excluded for averaging the image data. In this result, 1 LSB corresponds to 7.63 μV with 1.0-V ADC reference at 17b resolution. Fig. 13 shows a noise floor of the HCG and WDR imagers as a function of incident light input. The conversion gain of the both imager can be confirmed in these results and those of HCG and WDR imagers obtained from the cross points where the photon shot noise becomes one electron are 73.2-μV/e− and 22.8-μV/e−, respectively.


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the surveillance, bioimaging, and space applications require relatively high sensitivity compared with the other parameters. In this case, large pixel size (or column pitch) is chosen for obtaining the high responsivity [25]. On the other hand, the employment of small pixel size is required for low-cost consume applications. In the prototype chip, the sensor’s responsivity is relatively important factor for the low-light imaging. The column pitch of 7.1 μm has not only high fill factor of 45%, but is also suitable for the scientific applications. IV. C ONCLUSION (a)

(b) Fig. 13. Photon shot noises as a function of signal level (VR = 1.0 V). (a) HCG imager. (b) WDR imager.

An extremely low temporal noise and wide dynamic range CMOS image sensor is developed by using lownoise transistors and high gray-scale resolution (17b) foldingintegration/cyclic ADC. Two types of pixel have been designed. One is a high conversion gain pixel with optimized FD node structure and the other is a pixel for achieving the wide dynamic range with an n-ch. native transistor. The CMOS image sensor which is in combination with the proposed pixels and the high performance column-parallel hybrid ADC has achieved a low pixel temporal noise of 1.1e− rms (type 2) at ADC reference voltage VR = 1.0 V and a wide dynamic range of 87.5 dB (type 3) at ADC reference voltage VR = 2.0 V with the video rate operation. In addition, the WDR imager has an extremely low vFPN of 1.08-μVrms and a very small occurrence of the RTS noise because of the noise reduction effect of the native transistor as an in-pixel source follower amplifier. R EFERENCES

Fig. 14. Captured image at low-illumination condition of 0.03-lx, F = 1.4 (M = 32 and VR = 1.0 V).

Fig. 14 shows the captured images at 30 fps and low light level of 0.03–lx. In the low-illumination condition, the HCG imager (Type 2) is reproduced the target pictured better than the WDR imager (Type 3) but both cases are no visible vFPN. Table I shows the summary of the prototype sensors performance. The total area of the chip is 12.0 mm × 12.0 mm. The types of the two pixels are a four-transistor active pixel sensor (APS) and the pixel pitch is 7.1 μm The choice of pixel array pitch depends on the sensor’s applications. E.g.,

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Min-Woong Seo (S’11–M’13) received the B.S. and M.S. degrees in electrical and electronic engineering from Kyungpook National University, Daegu, Korea, in 2007 and 2009, respectively, and the Ph.D. degree from Shizuoka University, Hamamatsu, Japan, in 2012, for his thesis on low noise, high dynamic range CMOS image sensor using high performance ADCs. He joined the Imaging Devices Laboratory, Shizuoka University, in 2012, as a JSPS Research Fellow, working on sensor interface circuits and high performance sensors. His current research interests include CMOS imaging devices, bioimaging devices, and mixed analog/digital circuit designs. Dr. Seo received the Grand Prize at 7th IDEC Design Contest from IDEC Regional Center at Kyungpook National University in 2008, the Dean’s Award for Graduate School of Science and Technology from Shizuoka University, and Hori Award for Young Researcher from the Research Institute of Electronics, Shizuoka University in 2012.


Takehide Sawamoto received the M.E. degree from Shizuoka University, Hamamatsu, Japan, in 2012. Since 2012, he joined Brookman Technology, Inc., Hamamatsu. His current research interests include design of image sensor.

Tomoyuki Akahori received the B.S. degree from Daido University, Aichi, Japan, in 2002. He joined Sanei Hytechs Co., Ltd, Hamamatsu, Japan, from 2002 to 2008. His current research interests include design of analog circuit. In 2008, he joined Brookman Technology, Inc., Hamamatsu, where he has been working on the development and design of CMOS image sensor and analog circuits.

Tetsuya Iida received the B.S. and M.S. degrees from Shizuoka University, Hamamatsu, Japan, in 2008 and 2010, respectively. In 2010, he joined Brookman Technology, Inc., Hamamatsu. His current research interests include CMOS image sensor and analog circuits.

Taishi Takasawa received the B.S. degree from Tokai University, Kanagawa, Japan, in 2003. In 2009, he joined Shizuoka University, Hamamatsu, Japan. His current research interests include design of the digital circuit and the verilog language.

Keita Yasutomi (S’08–M’11) received the B.E. and M.E. degrees in electrical and electronic engineering and the Ph.D. degree from Shizuoka University, Hamamatsu, Japan, in 2006, 2008, and 2011, respectively. He is currently an Assistant Professor with the Research Institute of Electronics, Shizuoka University, Hamamatsu. His current research interests include time-resolved CMOS image sensors and low-noise imagers. Dr. Yasutomi is a member of the Institute of Electronics, Information and Communication Engineers of Japan and the Institute of Image Information and Television Engineers of Japan.


Shoji Kawahito (S’86–M’88–SM’00–F’09) received the Ph.D. degree from Tohoku University, Sendai, Japan, in 1988. In 1988, he joined Tohoku University as a Research Associate. From 1989 to 1999, he was with the Toyohashi University of Technology, Toyohashi, Japan. He was a Visiting Professor with ETH, Zurich, Switzerland, from 1996 to 1997. Since 1999, he has been a Professor with the Research Institute of Electronics, Shizuoka University, Hamamatsu, Japan, since 2006, he has been a CTO of Brookman Technology, Inc., Hamamatsu. His research interests include CMOS imaging devices, sensor interface circuits and mixed analog/digital circuits designs. He has published more than 300 papers in referred journals and international conference proceedings. He received many awards including the Outstanding Paper Award at the 1987 IEEE International Symposium on Multiple-Valued Logic, the Special Feature Award in LSI Design Contest at the 1998 Asia and South Pacific Design Automation Conference, the Beatrice Winner Award for Editorial Excellence at the 2005 IEEE International Solid-State Circuits Conference, the IEICE Electronics Society Award in 2010, and the 24th Takayanagi Memorial Award in 2010. He is a fellow of the Institute of the Image Information and Television Engineers and a member of the Institute of Electronics, Information and Communication Engineers and the Society of Photo-Optical Instrumentation engineers.

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