A low voltage CMOS floating resistor - IEEE Xplore

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resistor. The proposed CMOS realization is based on the maximum number of transistors connected between the supply voltages is two to operate under the low ...
A Low Voltage CMOS Floating Resistor Soliman. A. Mahmoud Electronics and Communications Engineering Department, Cairo University, Fayoum Campus, Fayoum, Egypt. proposed circuit using CMOS 0.35 p m technology is given.

Abstract- This paper presents a new CMOS floating resistor. The proposed CMOS realization is based on the maximum number of transistors connected between the supply voltages is two to operate under the low power supply condition. The proposed floating resistor circuit is operating at supply voltages of kl.5 V, it has a total standby current of 100 pA. Therefore the proposed CMOS floating resistor is suitable for low voltage low power applications. The proposed floating resistor is simulated using CMOS 0.35pm technology.

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I. INTRODUCTION

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The CMOS resistor is a basic circuit element in analog circuits. The direct implementation of resistors in analog CMOS circuits is usually avoided because of the low sheet resistance, accuracy limitations and its value can not be tuned. Extensive research has been proposed for replacing the resistors in analog circuits by MOS transistors [ 1-51 such that the circuit is fully integrated. Usually, the realization of the CMOS floating resistor is based on the linearization of the current difference of two MOS transistors operating in the saturation region using suitable biasing circuits which can be explained by Fig.1. In the first configuration, the two gates of the transistors are the two terminals of the resistor where VI and Vz are applied as shown in Fig.1 (a) and the two sources are biased by a suitable voltages V, and Vb such that the current flowing through the resistor (Ii =lo) is linear with the voltage across the resistor (V, - V,). In the second configuration, the two sources of the transistors are the two terminals of the resistor as shown in Fig.1 (b) and the two gates are biased to achieve the desirable linearity. The differential current of the two transistors is forced to be the current flowing through the resistor Ii =I, =I1 - I2 as shown in Fig.1. In these configurations, at least three transistors are needed between the two rails, one of them is the basic transistor and two other transistors for current transfer [l], resulting less range for the input voltage swing when the supply voltage is reduced. In this paper, a new configuration is proposed such that the number of transistors between the two voltages rails is reduced to two transistors. The paper is organized as follows. In section 11, the realization of CMOS floating resistor is presented. In section 111, the second order effects like the mobility reduction and channel length modulation are presented. In section IV, the simulation results of the

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(b)

Fig.1 The two basic configurations of the two NMOS transistors to realize a floating resistor [l].

11. The CMOS Resistor Circuit The CMOS floating resistor circuit is shown in Fig.2; the nodes 1 and 2 are the two terminals of the resistor. The matching transistors M1, M2, M3 and M3 are the basic transistors of the resistors and the remaining transistors perform the current transfer to the two nodes 1 and 2. All transistors are assumed to be operating in the saturation region with their sources connected to the substarehulk. The MOS drain current in the saturation is given by:

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K

-(vGs -v,>* D-2 -

(1)

W K = pLncox-, pn is the electron L mobility, Coxis the oxide capacitance per unit area, Where,

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111. Second Order Effects

W is the transistor aspect ratio and V, is the L

threshold voltage.

The above analysis is based on the square law drain current equation. Effects like mobility reduction and channel length modulation will help to calculate the linearity error in the proposed circuit.

From Fig.2,

Ii = I, = (Il + 13)- (I2 + 14)

(2)

a. Mobility Reduction

Where,

The drain current of the MOS transistor with the effect of mobility reduction is given by :

K I, = -(V1 2

-

K I2.=--(V2 2

-v,

-V,)2

K I3 = -(V2 2

-v,

-vT)

v, - V,)2

(3)

(9) (4) 2

Where 8 is the mobility degradation parameter , by taking mobility reduction effect of the currents of the basic four transistors M1, M2, M3 and M4, The resistor current is given by ;

(5)

Therefore, the current flowing through the resistor is given by :

Where %’’ is given by:

Therefore, the CMOS circuit in Fig.2 simulates a floating resistor between the nodes 1 and 2 and its value is controlled by the differential voltage (vb - ) , independent of the threshold voltage and is given by:

The error resulting from the mobility reduction can be reduced by making the common mode of the input voltages is close to ( 0.5(Va + vb) + V, ).

va

1 - (V, -v,> R = (V, -V*) Ii Io K(V, - V,)

b. Channel Length Modulation

(8) The drain current of the MOS transistor with the effect of channel length modulation is given by :

From eqn. 8, for Vb > V , the circuit operates as a resistor with positive resistance and when Vb < V , the circuit operates as a negative resistor. VDD

I

Where k is the channel length modulation parameter, by taking channel length modulation effect of the currents of the basic four transistors M1, M2, M3 and M4, The resistor current is given by ;

1, = I , =K(V, -V,>(VI -V2)+A

(13)

Where , A is given in terms of the drain voltages VD1 and VD2of ( M1, M3) and (M2, M4) respectively by :

and Fig.2. The Proposed CMOS Floating Resistor

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V. Conclusion A CMOS floating resistor has been introduced, analyzed and simulated. The CMOS floating resistor is based on a new configuration with only two transistors between the supply rails. The circuit is suitable for low voltage and low power applications. The proposed CMOS resistor circuit is characterized by the ability to achieve high resistor values independent of the threshold voltage.

From the above equations, the channel length modulation error A is neglected at small input voltages (VI and V,) and also small biasing voltages (V, and vb).

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IV. Simulation Results PSpice simulations were carried out to verify the performance of the proposed CMOS floating resistor circuit using model parameters of 0.35pm CMOS process provided by MOSIS. The supply voltages were equal to f 1.5 V. Fig.3 illustrates the I-V DC characteristics between the resistor current and the input voltage VI for different values of Vz with the biasing voltages v,= -1.05V and Vb =-0.85 v. It is shown that the proposed CMOS resistor features a linear resistor over the input differential voltage range from -0.5 V to 0.5V and resistance value of R = 50Ko. Fig.4 illustrates the I-V DC characteristics between the resistor current and the input voltage VI for V2 equal zero volt with the biasing voltage V, scanned from -1 .V to -1.4 V and Vb = - O M V. It is shown that the proposed CMOS resistor features a linear resistor over the single ended input voltage range from -0.25 V to 0.25V and resistance values from R=25 K to R = 50 K n. The THD is less than 0.4 % for a 100 KHz 0.2V peak-to-peak sinusoidal input. The standby current of the proposed circuit is less than lOOpA . Fig.5 indicates the magnitude frequency response of the CMOS resistor current flat to 1OMHz.

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Fig.4 The I-V characteristic of the proposed CMOS Floating Resistor with V2 =OV, vb=-o.85v and V, scanned from -lV TO -1.4V pw-~ .........................................................................................

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Fig.5 The magnitude frequency response of the CMOS resistor current REFERENCES

[l] S. A. Mahmoud, H. 0. Elwan and A. M. Soliman," Generation of CMOS voltage controlled floating resistors," Microelectronics J., 28, pp. 627-640, 1997. [2] H. 0. Elwan, S. A. Mahmoud and A. M. Soliman," CMOS voltage controlled floating resistor," Int. J. of Electronics, 81, pp. 571576.1 996.

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Fig3 The I-V Characteristic of the proposed CMOS Floating Resistor with V2 as a parameter ( v,=-1.05 v and Vb=-O.SSV)

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[3] Z. Czamul," Novel MOS resistive circuit for synthesis of fully integrated continuous-time filters," IEEE Trans. Circuits Syst., 33, pp. 718-721, 1986. [4] Y. Tsividis , M. Banu, and J. Khoury, " Continuous time MOSFET filters in VLSI," IEEE J. of Solid State Circuits, 21, pp. 15-31, 1986. [5] S. A. Mahmoud and A. M. Soliman," New CMOS fully differential difference transconductors and application to fully differential filters for VLSI," Microelectronics J., 30, pp. 169-192, 1999.

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