A Millimeter-Wave System-on-Package Technology ... - IEEE Xplore

IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 32, NO. 1, FEBRUARY 2009

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A Millimeter-Wave System-on-Package Technology Using a Thin-Film Substrate With a Flip-Chip Interconnection Sangsub Song, Student Member, IEEE, Youngmin Kim, Jimin Maeng, Heeseok Lee, Youngwoo Kwon, Senior Member, IEEE, and Kwang-Seok Seo

Abstract—In this paper, a system-on-package (SOP) technology using a thin-film substrate with a flip-chip interconnection has been developed for compact and high-performance millimeter-wave (mm-wave) modules. The thin-film substrate consists of Si-bumps, ground-bumps, and multilayer benzocyclobutene (BCB) films on a lossy silicon substrate. The lossy silicon substrate is not only a base plate of the thin-film substrate, but also suppresses the parasitic substrate mode excited in the thin-film substrate. Suppression of the substrate mode was verified with measurement results. The multilayer BCB films and the ground-bumps provide the thin-film substrate with high-performance integrated passives for the SOP capability. A broadband port terminator and a V-band broad-side coupler based on thin-film microstrip (TFMS) circuits were fabricated and characterized as mm-wave integrated passives. The Si-bumps dissipate the heat generated during the operation of flipped chips as well as provide mechanical support. The power dissipation capability of the Si-bumps was confirmed with an analysis of DC-IV characteristics of GaAs pseudomorphic high electron-mobility transistors (PHEMTs) and radio-frequency performances of a V-band power amplifier (PA). In addition, the flip-chip transition between a TFMS line on the thin-film substrate and a coplanar waveguide (CPW) line on a flipped chip was optimized with a compensation network, which consists of a high-impedance and low-impedance TFMS line and a removed ground technique. As an implementation example of the mm-wave SOP technology, a V-band power combining module (PCM) was developed on the thin-film substrate with the flip-chip interconnection. The V-band PCM incorporating two PAs with broadside couplers showed a combining efficiency higher than 78%. Index Terms—Flip-chip interconnection, millimeter-wave (mm-wave), power amplifier, power combining module, pseudomorphic high electron-mobility transistor, Si-bump, system-on-package (SOP), thin-film microstrip, thin-film substrate.

I. INTRODUCTION LONG with the recent rapid increase in the demand for more bandwidth and automobile driving safety, millimeter–wave (mm-wave) applications such as a short-range

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Manuscript received July 11, 2007; revised February 12, 2008. Current version published February 13, 2009. This work was recommended for publication by Associate Editor P. Franzon upon evaluation of the reviewers comments. S. Song, Y. Kim, J. Maeng, Y. Kwon, and K.-S. Seo are with the School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Korea (e-mail: [email protected]; [email protected]; jeem9@naver. com; [email protected]; [email protected]). H. Lee is with Samsung Electronics, Interconnect Product and Technology, Yongin 151-742, Korea (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TADVP.2008.2006626

broadband wireless communication and an automobile advanced cruise control are currently attracting great interest and investment [1]–[3]. These applications require a commercial packaging technology allowing their practical reality. The mm-wave system-on-package (SOP) approach using a thin-film substrate with a flip-chip interconnection is a prospective solution for these systems due to its mature multilayer fabrication and high-performance interconnection technology. The thin-film technology is capable of not only providing high-resolution patterns, a necessity for accommodating mm-wave frequencies having very short wavelength, but also allowing high-performance integrated passives. The flip-chip interconnection allows a high-performance interconnection with high reproducibility and low assembly-cost [4]–[6]. However, in the conventional thin-film technology with the flip-chip interconnection, flip-chip bumps are directly located on a thin-film layer having a high coefficient of thermal expansion (CTE) and a low thermal conductivity. It causes thermal and thermo-mechanical problems in flip-chip structures. To improve the thermal and thermo-mechanical performance of the flip-chip structure, the Si-bumps were introduced into the thin-film substrate by our group [7]. The Si-bumps, which and a high thermal conductivity have a CTE of 3.5 of 150 W/mK, allow the thin-film substrate to have close thermal expansion match with a flipped chip and to dissipate the heat generated during the operation of an active flipped chip. In addition to the Si-bumps, the ground-bumps were formed at the same time during the process of the Si-bumps [8]. The ground-bumps provide high-performance integrated passives based on thin-film microstrip (TFMS) circuits without a deep-via-hole process. In this paper, we have demonstrated the thin-film technology considering the flip-chip interconnection suitable for the mm-wave SOP approach. A V-band power combining module (PCM) was developed as a demonstration of the flip-chip capability of the thin-film substrate. The following section addresses the fabrication process of the thin-film substrate. Section III discusses electrical performances of the thin-film substrate at mm-wave frequencies. The mm-wave integrated passives such as a broadband port terminator and a V-band broadside coupler were fabricated and characterized based on the TFMS circuits, which are shown in Section IV. In Section V, the flip-chip transition between TFMS lines on the thin-film substrate and a CPW line on the flipped chip was optimized. Effectiveness of the Si-bumps on the power dissipation capability was confirmed with an analysis of DC-IV characteristics of the mounted GaAs

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Fig. 1. Cross-sectional view of the thin-film technology considering the flipchip interconnection.

pseudomorphic high electron-mobility transistors (PHEMTs) and radio-frequency (RF) performances of the mounted V-band PA in Section VI. Section VII shows a V-band PCM using the thin-film technology with the flip-chip interconnection. Finally, this paper concludes with a summary in Section VIII. II. THIN-FILM SUBSTRATE CONSIDERING THE FLIP-CHIP INTERCONNECTION The thin-film technology considering the flip-chip interconnection is shown in Fig. 1. A distinctive feature of the thin-film substrate is Si-bumps and ground-bumps introduced on a lossy ) as a base plate. To fabricate the silicon substrate (20 was wet-etched in bump structures, a silicon substrate a 45% KOH solution until a depth of 24 m was achieved. A 1000 layer was deposited to prevent DC leakage current from flowing through the Si-bumps because the Si-bumps were made of lossy silicon. After a ground plane of TFMS circuits and a passivation layer to protect the Si-bumps were defined, the first benzocyclobutene (BCB) layer of 20 m was spin-coated on the etched silicon substrate and cured in a vacuum oven to avoid oxidation. Then, the second BCB layer of 5 m was spin-coated and cured. The etched silicon substrate coated with the BCB layers has a very flat plane because the BCB film has a high degree of planarization property. Lumped compo) and capacinents such as NiCr resistors (20 tors (880 ) were realized on the second BCB layer. A thick Au layer of 3 m was electroplated as transmission lines after the third BCB layer of 5 m was spin-coated and cured. Via-holes were formed with a plasma RIE process without a deep via-hole process. For the flip-chip interconnection, Au/Sn bumps were electroplated as flip-chip bumps. More information on the process of the thin-film substrate was presented in [8]. III. ELECTRICAL PERFORMANCES OF THE THIN-FILM SUBSTRATE RF circuits enclosed within a package do not perform quite as well as predicted. Unwanted parasitic modes, which might change the impedance of RF circuits and bring instability into RF circuits, are generated inside a package. Especially, RF circuits using CPW lines can seriously suffer from the parasitic substrate mode because the substrate mode is excited between

Fig. 2. (a) Geometry of the short-circuited CPW lines with bend-slots (b) measured transmission of the CPW line against a lossy silicon substrate (20 1 cm) and a high resistivity silicon substrate ( 10 k 1 cm).

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the CPW ground plane and the package metal plane [9]. This substrate mode results in the substrate resonance and the multiple-modes interference. To suppress the substrate mode, shorting via-hole and insertion of a lossy submount layer have been proposed [10], [11]. In our thin-film substrate, a lossy ) has been used as a base plate to silicon substrate (20 attenuate and absorb the leakage in the form of the substrate mode. In order to investigate the effect of the lossy silicon substrate, short-circuited CPW lines with bend-slots were fabricated on the thin-film substrate using a high resistivity silicon (HRS) substrate and a lossy silicon (20 ) substrate, respectively. Fig. 2(a) shows a geometry of the short-circuited CPW lines with bend-slots. The transmission between the short-circuited CPW lines with bend-slots was measured by an on-wafer measurement up to 110 GHz with the HP 8510C network analyzer. The two-port short-open-load-thru (SOLT) calibration was performed using Cascade ISS 104-783 standards. A reference plane was at the probe tips. Ideally, the transmission between the short-circuited CPW lines should be zero. However, Fig. 2(b) shows that the CPW line on the HRS substrate suffers because the parasitic subfrom significant fluctuations of strate mode is excited by a metal plane formed during on-wafer in the lossy silmeasurements. Otherwise, fluctuations of icon substrate were greatly suppressed as the lossy silicon substrate attenuates and absorbs the resonant leakages. Even though the lossy silicon substrate was used as the base plate to suppress the substrate mode, a low loss transmission line such as a TFMS line can be fabricated owing to the BCB

SONG et al.: A MILLIMETER-WAVE SYSTEM-ON-PACKAGE TECHNOLOGY USING A THIN-FILM SUBSTRATE

Fig. 3. Measured insertion loss of the 50- TFMS lines and the 50- CPW line on the third BCB layer.

layers. The TFMS line is known to be free from substrate properties because the ground plane of the TFMS line shields the signal line from the substrate effects. In the thin-film substrate, a 50- TFMS line having a low insertion loss of 0.13 dB/mm at 60 GHz was realized on the third BCB layer. Furthermore, with the BCB layers deposited on the lossy silicon substrate, the insertion loss of the CPW line was minimized. A 50- CPW line on the third BCB layer showed an insertion loss of 0.34 dB/mm at 60 GHz when the ground to ground spacing was 100 m. The measurement results of the CPW line and the TFMS line characterized from a length of 5 mm are presented in Fig. 3. These results show that mm-wave integrated passives with high-performance can be fabricated on the thin-film substrate using the lossy silicon substrate.

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Fig. 4. Microphotograph and measured return loss of the 50- port terminator using an integrated resistor of 20 =square and 25 m width.

Fig. 5. Microphotograph and measured return loss of the fabricated port terminator with the open-ended stub.

IV. INTEGRATED PASSIVES IN THE THIN-FILM SUBSTRATE A. Broadband Port Terminator Port terminator is important to minimize the reflection of RF power for power applications. This can be easily realized with an integrated thin-film resistor. However, even with an integrated resistor, the return loss of a port terminator is degraded at mm-wave frequencies due to the parasitic self-inductance of the resistor. As shown in Fig. 4, the measured return loss of the 50port terminator using the integrated resistor of 20 and 25 m width reaches 10 dB at 100 GHz. In order to realize a broadband port terminator, the port terminator was compensated by adding an open-ended stub considered as a capacitor to cancel the effect of the inductance. The length and width of the stub were determined by the electromagnetic (EM) simulation. Fig. 5 shows the microphotograph and the measurement result of the fabricated port terminator with the open-ended stub. The measurement result shows the terminator achieves a good return loss of 20 dB up to 110 GHz. B. V-Band Broad-Side Coupler Power dividers are required for power division or power combining in high-performance mm-wave modules. These are usually of the equal-division (3 dB) type, which is realized by the Lange coupler. On BCB layers having a low dielectric constant,

the Lange coupler using parallel-coupled multiconductor transmission lines can not afford the equal power division because tightly coupled thick metal structure is difficult to realize. Therefore, we developed a coupler using a broadside coupling structure, which was proposed as an alternative structure to obtain tight coupling [12]. Fig. 6 shows the microphotograph and the measurement result of the fabricated V-band broad-side coupler. The upper metal width, lower metal width, and overlaid width between the metals of the broadside coupling structure were optimized with the EM simulation. The measurement result shows that the transmission and coupling loss of 3.8 0.2 dB, return loss better than 15 dB, and isolation better than 18 dB at V-band (45 GHz 75 GHz). V. BROADBAND FLIP-CHIP TRANSITION A. Compensation Network Using a High-Impedance and Low-Impedance TFMS Line A flip-chip transition has an inductive and a capacitive contribution [6]. The capacitive part is attributed to a dielectric overlap of a thin-film substrate and a flipped chip in bump pads. The inductive part is attributed to a flip-chip bump and a fringing effect of the current in a flip-chip bump. At lower frequencies, the capacitive part dominantly affects the flip-chip transition. At

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Fig. 6. Microphotograph and measured S-parameters of the fabricated V-band broadside coupler.

Fig. 8. Schematic and measured return loss of the flip-chip structure with the removed ground technique.

B. Optimized Compensation Network With a Removed Ground Technique

Fig. 7. SEM image and measured return loss of the flip-chip structure with the compensation network.

higher frequencies, the inductive part is more dominant. In order to compensate this behavior in the flip-chip transition, a compensation network using a high-impedance and low-impedance line was proposed [13]. We applied this compensation network to the flip-chip transition between TFMS lines on the thin-film substrate and a CPW line on the flipped chip. The compensation network was optimized to achieve a minimum return loss of the flip-chip transition in mm-wave range. A 2-mm–50CPW line (ground to ground spacing: 80 m, signal width: 30 m) was fabricated on a GaAs substrate as the flipped chip. The TFMS lines were fabricated on the thin-film substrate with the Si-bumps, so the flip-chip bumps are located on the Si-bumps. The dimension of the compensation network was determined by the EM simulation at Ka-band (40 GHz), V-band (60 GHz), and W-band (77 GHz), respectively. Fig. 7 shows the SEM image and the measured return loss of the flip-chip transition with the compensation network. As shown in Fig. 7, the flip-chip structures show very good return loss better than 20 dB at the target frequency.

The compensation network using a high-impedance and lowimpedance line shows the improved flip-chip transition performance only in the target frequency. To achieve more broadband flip-chip transition performance, the intrinsic parasitic components in the flip-chip transition structure have to be excluded. As mentioned above, the flip-chip transition structure has the inductive and the capacitive contribution. The capacitive part can be easily decreased by removing the ground plane of the TFMS line under flip-chip bumps, as presented in Fig. 8. To analyze the effect of the removed ground technique on the flip-chip transition, we measured the return loss of the flip-chip transition , as shown in Fig. 8. The reagainst removed ground sizes sult indicates that the removed ground technique decreases the capacitive part, which results in the improved transition performance at low frequency. By increasing the removed ground size, the flip-chip transition in low frequency shows better return loss, m because but it gets worse with very large of the increased inductive part. From these results, we optimized the flip-chip transition between the TFMS lines and the CPW line. The optimized compensation network consisted of the high-impedance and low-impedance TFMS line and the removed ground technique m . The measured return loss of the optimized flip-chip transition is shown in Fig. 9. The optimized compensation network shows about 6 dB improvement in the return loss against the nonoptimized one. VI. THERMAL MANAGEMENT IN THE THIN-FILM SUBSTRATE Due to the poor thermal conductivity of dielectric layers used in a thin-film substrate, a successful power application in a mm-wave SOP technology using a thin-film substrate requires careful thermal considerations. In a thin-film substrate with a flip-chip interconnection, special attention has to be paid to the thermal management since heat dissipation is concentrated at flip-chip bumps.


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Fig. 9. Comparison for measured S-parameters between the optimized compensation network and nonoptimized one.

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Fig. 10. Microphotograph of 2 50, 4 50, and 8 75 m GaAs PHEMTs and the thin-film substrate with or without the Si-bumps.

A. Thermal Analysis With DC-IV Characteristics of GaAs PHEMTs To provide reliable thermal management in the flip-chip structure, DC-IV characteristics of active devices under various package conditions (on-wafer and flip-chip bonding (FCB) with or without the Si-bumps) have been analyzed based on measurement results. All the active devices presented here are commercial 0.15- m gate GaAs PHEMTs with 100 m GaAs thickness suitable for mm-wave applications. 50, 4 We investigated DC-IV characteristics of 2 50, and m PHEMTs. The PHEMT devices were flip-chip-mounted on the thin-film substrate with or without the Si-bumps as presented in Fig. 10. Fig. 11(a) shows the m PHEMTs. measured DC-IV characteristic of the There is little difference of the DC-IV characteristic between on-wafer and FCB with the Si-bumps, whereas the PHEMT in FCB without the Si-bumps is slightly degraded compared with on-wafer as the gate bias increases. As shown in Fig. 11(b), m PHEMT. the degradation is more apparent in the The PHEMTs in on-wafer and FCB with the Si-bumps show the similar DC-IV characteristic. However, the device in FCB without the Si-bumps suffers from the thermal problem in the absence of heat dissipation routes.

Fig. 11. DC-IV characteristics of GaAs PHEMTs under on-wafer and FCB with or without the Si-bumps (a) 2 50 m GaAs PHEMT, (b) 4 50 m GaAs PHEMT, and (c) 8 75 m GaAs PHEMT.

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Even in the m PHEMT for a high-power amplifier, there is no degradation of the DC-IV characteristic in FCB with the Si-bumps [Fig. 11(c)]. In case of FCB without the Si-bumps, as expected, the device shows a 30% degradation in the DC-IV and . Furthermore, the characteristic at device has stopped working when a voltage higher than 5 V was . This phenomenon is explained by the increased applied to gate current. As the device dissipates more output power with

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Fig. 12. Microphotographs of a flip-chip mounted V-band PA on the thin-film substrate with the Si-bumps.

Fig. 14. Microphotograph of the developed V-band power combining module.

B. Thermal Analysis With RF Performances of a V-Band PA A V-band PA has been designed using a m GaAs PHEMT MMIC based on the grounded CPW with 100 m GaAs thickness. The PA was flip-chip-mounted on the thin-film substrate with or without the Si-bumps (Fig. 12). Thermal management of the PAs was evaluated in terms of S-parameters and output power. Fig. 13(a) shows the measured small signal S-parameters of the PAs. The PAs show very similar return loss regardless of the package conditions due to the improved flip-chip transition. In a small signal gain, FCB with the Si-bumps shows 1.6 dB smaller than on-wafer, which is mainly induced from the flip-chip transition loss, whereas FCB without the Si-bumps shows a significant reduction of 4.6 dB in a gain compared with on-wafer. The measured power gain and output power of the PAs as a function of the input power are presented in Fig. 13(b). Compared with on-wafer, FCB without the Si-bumps leads to a saturation power reduction of 2.6 dBm, whereas FCB with the Si-bumps shows a saturation power reduction of 1 dBm due to the flip-chip transition loss. These results confirm that our thin-film substrate is promising technology for a high power RF module. VII. V-BAND HIGH EFFICIENCY PCM

Fig. 13. (a) Measured S-parameters and (b) measured power gain and output power of PAs under on-wafer and FCB with or without the Si-bumps.

increasing , the dissipated power increases the device temperature. As shown in Fig. 11(c), a rise in the device temperature increases the gate current, which results in the destruction of the device.

Power available from PAs is limited at mm-wave frequencies, and subsequently a high efficiency power combiner is required to achieve high output power. Many power-combining approaches have been tried in mm-wave frequencies. Several techniques such as the quasi-optical power-combining and the waveguide-based spatial power-combining have been proposed to get a high combing efficiency [14]–[16]. However, these techniques might be promising approaches in integrating a large number of power circuits because these techniques suffer from insufficient modeling results, a complicated mechanical assembling, and a large physical size. In mm-wave modules, a 1 2 or 2 2 MMIC PA combining scheme is usually required to meet the system specifications. In this case, a planar structure using Wilkinson power combiners or


Fig. 15. Measured S-parameters of the V-band power combining module.

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Fig. 17. Measured saturated output power and combining efficiency of the flipped V-band PA and the V-band power combining module against frequency.

frequency, the combining-efficiency of the PCM is about 89%. Moreover, this PCM technology can be applied to higher frequency because it is based on the thin-film substrate with the flip-chip interconnection. VIII. CONCLUSION

Fig. 16. Measured power gain and output power of the flipped V-band PA and the V-band power combining module against input power.

Lang couplers is an effective combining solution due to its sufficient modeling results and simple construction. In this work, the high-performance V-band PCM using the mm-wave SOP technology has been demonstrated with the broad-side couplers integrated in the thin-film substrate. Fig. 14 shows the photograph of the fabricated V-band PCM. In the developed PCM, two PAs are flip-chip mounted on the thin-film substrate with the Si-bumps. The V-band broad-side couplers integrated in the thin-film substrate divide input power and combine output power of the flipped PAs. Fig. 15 shows the measured S-parameters of the PCM. The PCM shows a small signal gain of 12.5 dB at 58 GHz, which is 1.6 dB gain degradation compared with the flipped PA, due to the insertion loss of the couplers. The input and output matching of the PCM follows the return loss of the broadside Lange coupler as expected. The measured output power and power gain of the flipped PA and the PCM as a function of the input power at 58 GHz are shown in Fig. 16. As the input power increases, the flipped PA begins to saturate and shows a saturated output power of 18.5 dBm, whereas the PCM shows a saturated output power of 21.4 dBm. The measured saturated output power and combining efficiency at the input power of 14.9 dBm are shown in Fig. 17 as a function of frequency. The combining-efficiency over this frequency bandwidth is higher than 77%. The maximum output power of the PCM was 21.5 dB at 59 GHz. At this

The thin-film technology considering the flip-chip interconnection was presented for a mm-wave package solution. The thin-film substrate was characterized in terms of the electrical performance, the integrated passives, the flip-chip transition, and the thermal management. It is confirmed that the developed packaging approach enables a high-performance mm-wave SOP technology. As a prototype using the proposed mm-wave SOP technology, we developed a V-band PCM, exhibiting combining efficiencies higher than 78%. These results demonstrate that the proposed power combining technique in the SOP technology is promising for high-power applications at mm-wave frequencies. REFERENCES [1] H. Zirath, T. Masuda, R. Kozhuharov, and M. Ferndahl, “Development of 60-GHz front-end circuits for a high-data-rate communication system,” IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1640–1649, Oct. 2004. [2] I. Gresham, N. Jain, T. Budka, A. Alexanian, N. Kinayman, B. Ziegner, S. Brown, and P. Staecker, “A compact manufacturable 76–77-GHz radar module for commercial ACC applications,” IEEE Trans. Microwave Theory Tech., vol. 49, no. 1, pp. 44–58, Jan. 2001. [3] J. Wenger, “Automotive radar-status and perspectives,” in IEEE Compound Semiconductor Integrated Circuit Symp. Dig., 2005, pp. 21–24. [4] W. Diels, K. Vaesen, P. Wambacq, S. Donnay, W. D. Raedt, M. Engels, and I. Bolsens, “Single-package integration of RF blocks for a 5 GHz WLAN application,” IEEE Trans. Adv. Packag., vol. 24, no. 3, pp. 384–391, Aug. 2001. [5] G. Carchon, K. Vaesen, S. Brebels, W. D. Raedt, E. Beyne, and B. Nauwelaers, “Multilayer thin-film MCM-D for the integration of high-performance RF and microwave circuits,” IEEE Trans. Compon. Packag. Tech., vol. 24, no. 3, pp. 510–519, Sep. 2001. [6] W. Heinrich, “The flip-chip approach for millimeter-wave packaging,” IEEE Micro. Mag., vol. 6, pp. 36–45, Sep. 2005. [7] S. Song, S. Kim, S. Yeon, S. Park, J. Lee, S. Lee, W. Choi, Y. Kwon, and K.-S. Seo, “The flip-chip mounted MMIC technology using the modified MCM-D substrate for compact and low-cost W-band transceiver,” in IEEE MTT-S Dig., 2005, pp. 1011–1014. [8] S. Song, J. Maeng, H. Lee, and K.-S. Seo, “High-performance millimeter-wave SOP technology with flip-chip interconnection,” in Proc. 57th IEEE Electron. Compon. Technol. Conf., Reno, NV, 2007, pp. 1007–1013.

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[9] H. Shigesawa, M. Tsuji, and A. A. Oliner, “Conductor-backed slot line and coplanar waveguide: Dangers and full-wave analyses,” in IEEE MTT-S Dig., May 1988, pp. 199–202. [10] N. K. Das, “Methods of suppression or avoidance of parallel-plate power leakage from conductor-backed transmission lines,” IEEE Trans. Microwave Theory Tech., vol. 44, no. 2, pp. 169–181, Feb. 1996. [11] S.-J. Kim, H.-S. Yoon, and H.-Y. Lee, “Suppression of leakage resonance in coplanar MMIC packages using a Si sub-mount layer,” IEEE Trans. Microwave Theory Tech., vol. 48, no. 12, pp. 2664–2669, Dec. 2000. [12] J. S. Izadian, “A new 6–18 GHz, 3 dB multisection hybrid coupler using asymmetric broadside, and edge coupled lines,” in IEEE MTT-S Dig., 1989, pp. 243–246. [13] F. J. Schmuckle, A. Jentzsch, H. Oppermann, K. Riepe, and W. Heinrich, “W-band flip-chip interconnects on thin-film substrate,” in IEEE MTT-S Dig., 2002, vol. 3, pp. 1393–1396. [14] S. C. Ortiz, J. Hubert, L. Mirth, E. Schlecht, and A. Mortazawi, “A high-power Ka-band quasi-optical amplifier array,” IEEE Trans. Microwave Theory Tech., vol. 50, no. 2, pp. 487–494, Feb. 2002. [15] N.-S. Cheng, P. Jia, D. B. Rensch, and R. A. York, “A 120-W X-band spatially combined solid-state amplifier,” IEEE Trans. Microwave Theory Tech., vol. 47, no. 12, pp. 2557–2561, Dec. 1999. [16] J. Jeong, D. Kim, S. Kim, and Y. Kwon, “V-band high-efficiency broadband power combiner and power-combining module using double antipodal finline transitions,” Electron. Lett., vol. 39, no. 4, pp. 378–379, Feb. 2003.

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Sangsub Song (S’07) was born in Korea, in 1979. He received the B.S. degree in electronics engineering from the University of Seoul, Seoul, Korea, in 2002, the M.S. degree, in 2004, from electrical engineering from Seoul National University, Seoul, Korea, where he is currently working toward the Ph.D. degree in electrical engineering. His current research activities include the design of MMICs for millimeter-wave and their system integration using system-on-packaging technology.

Youngmin Kim was born in Masan, Korea, in 1979. He received the B.S. degree in electrical engineering from Sung Kyun Kwan University, Seoul, Korea in 2001 and the M. S. degrees in electrical engineering, in 2005, from Seoul National University, Seoul, Korea, where he is currently working toward the Ph.D. degree. His current research activities include the design of MMICs for millimeter-wave system, their system integration and millimeter-wave high power amplifier.

Jimin Maeng was born in Korea, in 1979. He received the B.S. degree in electrical engineering from Hanyang University, Seoul, Korea, in 2003, and the M.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 2008. He is currently with the Interuniversity Semiconductor Research Center, Seoul National University, Seoul, Korea. His research interests include system-on-a package (SOP) and RF/millimeter-wave passive components.

Heeseok Lee received the B.S. degree in electronic communication engineering from Hanyang University, Seoul, Korea, in 1996, and the M.S.E.E. and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1998 and 2002, respectively. Since 2002, he has been with Samsung Electronics, Kiheung, Korea. In 1998, he served as a Student Researcher at Electronics and Telecommunication Research Institute (ETRI), Daejeon, Korea. He was appointed to the position of visiting scientist at the University of Michigan, Ann Arbor, from 1999 to 2000. His research experience during his graduate study includes the picosecond photoconductive probe based on LT-GaAs, terahertz imaging system, the design and modeling of high-speed interconnects, and numerical techniques for EM field solution. He holds a registered U.S. patent with several pending U.S. patents and 11 registered Korean patents. He is working on signal integrity, power integrity, EM field solution methodology, 3-D packaging and integration with die-stacking and through-silicon via, system-in–package, and development of novel high-speed/power microelectronic package. Dr. Lee was a receipt of a scholarship award from the Korea Foundation for Advanced Studies (KFAS) during his graduate study and he was also a scholarship student supported by the Korea Research Foundation (KRF) under grants for the Junior Researchers Program from 2001.

Youngwoo Kwon (S’90–M’94–SM’04) was born in Korea, in 1965. He received the B.S. degree in electronics engineering from Seoul National University, in 1988, and the M. S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, in 1990 and 1994, respectively. From 1994 to 1996, he was with Rockwell Science Center as a member of technical staff, where he was involved in the development of millimeter-wave monolithic integrated circuits. In 1996, he joined the faculty of School of Electrical Engineering, Seoul National University, Seoul, Korea, where he is currently a Professor. He has authored and coauthored over 150 technical papers in the internationally renowned journals and conferences. Over the past years, he has directed a number of RF research projects funded by Korean government and US companies. He is a coinventor of switchless stage-bypass power amplifier architecture called “CoolPAM” and cofounded Wavics, a power amplifier design company, which is now fully owned by Avago Technologies. He holds more than 20 patents on RF MEMS and power amplifier technology. Dr. Kwon has been working as an Associate Editor for IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. He has also served as a technical program committee member of various microwave and semiconductor conferences including IMS and IEDM. In 1999, he was awarded a Creative Research Initiative program by Korean Ministry of Science and Technology with a nine year term to develop new technologies in the interdisciplinary area of millimeter-wave electronics, MEMS, and biotechnology. He was the recipient of Presidential Young Investigator award from Korean government in 2006.

Kwang-Seok Seo received the B.S. degree from Seoul National University, Seoul, Korea, in 1976, and the M.S. degree from the Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 1978, and the Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor in 1987. From 1978 to 1982, he was a Senior Research Engineer at the Korea Institute of electronic Technology. From 1987 to 1988, he was a postdoctoral fellow at the IBM T. J. Watson Research Center. Since 1989, he has been with Seoul National University, Seoul, Korea, where he is now an Associate Professor in the School of Electrical Engineering. His current interests include high-speed device physics and technology, high-frequency circuit design, and their system integration using system-on-packaging technology.