0.5 mmX0.5 mm, excluding the output matching circuit, is achieved with conversion ... balanced frequency doubler which consists of a common- gate FET (CGF) ...
IEFE TRANSACTIONS O N MICROWAVE THEORY AND TECHNIQUES, VOL.
1932
38, NO. 12, DECEMBER 1990
A Miniaturized Broad-Band MMIC Frequency Doubler
Abstract -A miniaturized broad-band balanced MMIC frequency doubler, which consists of a common-gate FET and a common-source FET directly connected on each drain electrode, is proposed. A size of 0.5 mmX0.5 mm, excluding the output matching circuit, is achieved with conversion loss from 8 to 10 dB and fundamental signal suppression better than 17 dB from 6 to 16 GHz. The broad-band doubler as a miniaturized MMIC function module is valuable for MMIC oscillators, front ends, and transmitters.
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I. INTRODUCTION
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REQUENCY doublers and multipliers are important circuits in microwave and millimeter-wave components. Recently, single-ended frequency doublers [11which employ GaAs MESFET's because of their conversion gain and unilateral characteristics and balanced frequency doublers [2],constructed with two single-ended doublers and a balun for balanced operation, have been demonstrated in monolithic form. A wide-band MMIC frequency multiplier [3] based on the distributed amplifier architecture has also been reported. However, conventional doublers occupy a large area because of physically large hybrids, baluns, and fundamental frequency trapping stubs. The distributed amplifier configuration is still rather large because a large number of FET's, inductive lines, and transmission lines are used. This paper proposes a miniaturized broad-band MMIC balanced frequency doubler which consists of a commongate FET (CGF) and a common-source FET (CSF) connected in parallel electrically and in series at electrode locations, that is, source-gate-drain-gate-source. Advantages of the proposed MMIC doubler are that it remarkably reduces chip size and operates over a broad band, owing to active trapping of fundamental signals from the CGF and the CSF and to an active input impedance match by the CGF. The MMIC chip size is so small, 0.5 mmx0.5 mm, and the operating outputManuscript received April 3, 1990; revised July 23, 1990. T. Hiraoka and T. Tokumitsu were with ATR Optical and Radio Communications Research Laboratories, Sanpeidani, Inuidani, Seikacho, Soraku-gun, Kyoto 619-02, Japan. They are now with NTT Radio Communication Systems Laboratories, Nippon Telegraph and Telephone Corporation, 1.23% Take, Yokosuka-shi. Kanagawa 238-03, Japan. M. Akaike is with ATR Optical and Radio Communications Research Laboratories, Sanpeidani, Inuidani, Seika-cho, Soraku-gun, Kyoto 61902, Japan. IEEE Log Number 9038871.
(b)
Fig. 1. A proposed frequency doubler configuration. (a) Equivalent circuit diagram. (b) F E T electrode locations (source-gatedrain-gate-source).
frequency region is so wide, up to 20 GHz, that 2" frequency multipliers can be implemented by using the same MMIC chips. AND OPERATION 11. CONFIGURATION
The configuration of the proposed balanced frequency doubler is shown in Fig. 1. The area enclosed by the dotted line is the CGF/CSF section, which is realized using a two-gate GaAs FET configuration, that is, source-gate-drain-gate-source, as shown in Fig. l(b). One gate, GI, is grounded through a capacitor C, for the CGF structure, and one source, S,, beside the other gate, G,, is directly grounded for the CSF structure. S , and G, are connected in phase at the input port through, respectively, a phase shift circuit and a dc-block capacitor, C,. The phase shift circuit compensates for a phase error between the outputs from the CGF and the CSF. Drain D is the output port of both FET's and is connected to an output matching circuit. The CGF and the CSF are, as shown in the figures, connected in parallel electrically and
0018-9480/90/1200-1932$01.00 01990 IEEE
HIRAOKA
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1933
01.:A MINIATURIZED BROAD-BAND M M l C F R E O l IFNCY DOUBLER
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Fig. 2. A simplified frequency doubler configuration
fo = 5GHz -30 0.0
in series at electrode locations, resulting in a configuration similar to the conventional FET configuration. The doubler operates near the gate-source pinch-off voltage, which is given through the gate resistors R I and R,. The drain currents through the CSF and the CGF are swung nonlinearly by large input signals. The amplitudes of the output signals from the two FET's are made equal by adjusting each gate bias. In the CSF section, the output phase shifts at the fundamental frequency, fo, and the second harmonic, 2fo, are 180" and 360" respectively. In the CGF section, the output phase shifts at fo and 2fo are the same, 0". Thus, the fundamental-frequency signals from the CGF and the CSF cancel each other. On the other hand, the second harmonics are emphasized. This active trapping, along with an active input match by the CGF, realizes a miniature broad-band doubler. Fig. 2 shows a simplified frequency doubler which has a configuration similar to that in Fig. 1. The doubler is constructed with only a CGF/CSF section and a dc bias circuit. This simplified doubler is designed and demonstrated here. The phase shift circuit and the output matching circuit are eliminated for expanded application of the MMIC and for the following reason. Fig. 3 shows the magnitude and phase error versus input power characteristics calculated at a 5 GHz input signal frequency. The magnitude error is the ratio of the CSF output level to the CGF output level at fo, and the fundamentalfrequency phase error is the phase difference after subtracting 180". Fig. 3(a) is obtained when the gate-source dc bias voltage, Vgs, for both FET's is equal to the pinch-off voltage, V,. As shown in the figure, the phase error between the outputs from the CGF and the CSF is less than lo" at fo. This error is small enough for a fundamental-frequency signal suppression (isolation) of about 20 dB. At the same time, the phase error of less than 20" between the harmonic outputs from the CGF and the CSF causes little loss to the doubler performance. Therefore, the phase shift circuit is not necessary, up to Ku-band practically, in high-power operation near the pinch-off voltage. It is required only when much higher isolation is needed. The magnitude error of about 3 dB is not ignored for a high isolation; however, this error can easily be removed by adjusting the gate-source dc bias voltage for the CSF slightly. Fig. 3(b) is calculated under
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input power ( d h ) (a)
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fo = 5GHz
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input power (darn)
(b) Fig. 3. Magnitude and phase error versus input power characteristics calculated at 5 GHz input signal frequency. (a) VJCGF] = VJCSF] = V,. (b) V,,[CGFl= V,; Vx,[CSF] = 0.9 V,.
Gs
the condition where for the CGF (VJCGFI) is V , and Vgs for the CSF (V,,[CSF]) is 0.9 Vgs.As shown in Fig. 3(b), the magnitude error is nearly 0 dB above an input power of 10 dBm. 111. DOUBLER DESIGN A harmonic-balance, nonlinear circuit simulation was performed in order to determine the optimum gate width and gate-source voltage for wide-band characteristics. A J-FET model with the following parameters was used: p = 0.02 (A/V2), A = 0.05 (l/V), V, = - 1.15 (V), pb = 0.8 (VI, C,, = 0.25 (pF), and Cgd= 0.025 (pF). While the CGF is an unconditionally stable device in the microwave frequency range, it is sufficiently stable when the source electrode of the CGF is connected to a 50 R signal source impedance and C, is greater than 10 pF. A. Optimum Gate Width Conversion loss, return loss, and isolation versus gatewidth characteristics are calculated at input frequencies of 5 and 10 GHz and are shown in Fig. 4.Each FET is dc
1934
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38, N O 12, D F C F M H F R 1990
I K A N \ A C T I O N S O N MICROWAVE T H F O R Y A N D TECIINIOULS, VOL
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input power (dBm) Fig. 8. Conversion loss versus input power (fo= 5 GHz).
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Fig. 6. Photomicrograph of the fabricated MMIC doubler (chip size: 0.8 mm X 0.7 mm, intrinsic area: 0.5 mm X 0.5 mm).
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input power (dBrn) Fig. 9. Isolation versus input power (f0= 5 GHz).
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IV. RESULTS
- measured _ _ - - calculated
An MMIC frequency doubler implemented using the conventional GaAs MMIC process is shown in Fig. 6. The input and output coplanar waveguide impedance is SO R IO for on-wafer measurement. The chip size is only 0.8 mm X 0.7 mm (intrinsic area: 0.5 mm X 0.5 mm). This area is about 1/10 that of previously reported doublers [l].An 20 ion-implanted FET with a typical cutoff frequency of 20 GHz, a gate length of 0.5 pm, and a gate width of 150 p m is used in the doubler MMIC, where the gate width ratio wx/wao is 1.5. Capacitors C, and C, are 10 pF and 0.5 pF, respectively. Resistors R , and R , are 750 R. 3 4 5 6 7 8 9 10 The measured and calculated frequency responses at 10 input frequency (GHz) dBm input power are shown in Fig. 7. The gate-source (b) voltage, Vgs,is adjusted so that the MMIC exhibits an input return loss of around 10 dB and reasonably low conversion loss and high isolation, where Vgsis 0.9 V, for _._________________________.________________----the CSF and V, for the CGF. A conversion loss of 8-10 wl -*-.----*\./ dB is achieved for output frequencies between 6 and 16 10 vds = 3 v f GHz. Fundamental-frequency isolation is better than 17 VgslCSFl= 0.9Vp + Vgs[CGF] = Vp measured dB up to 20 GHz. An input return loss better than 7 dB is 2 calculated , , achieved without any input matching circuits owing to the pinf19dBy , , 20 active matching characteristic of the CGF. Power con3 4 5 6 7 8 9 10 sumption is about 42 mW when the input signal power is input frequency (GHz) 10 dBm. Degradation of the conversion loss at the output frequency between 16 and 20 GHz is due to the absence (c) Fig. 7. Measured and calculated performance of the doubler. (a) Con- of a phase compensation circuit. The operating frequency version loss. (b) Isolation. (c) Input return loss. range can be extended as the FET's are improved and by v
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also wish to thank Dr. H. Yamamoto, Dr. K. Habara, and Dr. Y. Furuhama for their advice and encouragement.
REFERENCES L
3 *
F VgsICSF] = 0.9Vp Vgs[CGF] = Vp
20.0
5.0
0.0
10.0
15.0
input power (dBm) Fig. 10. Input return loss versus input power ( f,,= 5 GHz).
using a miniature thin-film microstrip (TFMS) line phase shift circuit [4]. The broad-band performance and very small size of the MMIC are extremely valuable for generic use. The measured and the calculated performance as a function of 5 GHz input power are shown in Figs. 8, 9, and 10. Conversion loss decreases gradually as the input power increases and approaches the minimum value of 8 dB at an input power above 10 dBm. Input return loss is improved monotonically and is greater than 9 dB at an input power above 10 dBm. The fundamental-frequency isolation is greater than 17 dB up to 15 dBm input power. The difference between the measured and the calculated performance at input power levels below 5 dBm is due to insufficient FET model description near the pinch-off voltage.
V.
CONCLUSION
A miniaturized broad-band balanced MMIC frequency doubler, composed of a common-gate FET and a common-source FET directly connected to each drain electrode, has been proposed and demonstrated. The doubler is designed and fabricated as a miniaturized function module using a conventional two-gate FET configuration, active trapping, and active impedance matching. The doubler design has been performed through phase error estimation, gate width optimization, and gate-source voltage optimization. The phase error estimation in a nonlinear condition has eliminated phase error compensation circuits. The fabricated chip size is only 0.5 mm x 0.5 mm, which is about 1/10 the area of previously reported doublers. A conversion loss of 8-10 dB, a fundamental frequency suppression better than 17 dB, and an input return loss better than 8 dB are obtained in the output frequency range from 6 to 16 GHz. The broad-band doubler as a miniaturized MMIC function module can be applicable to small-size oscillator MMIC’s and multifunction MMIC’s. ACKNOWLEDGMENT The authors would like to thank Dr. M. Aikawa for his participation in helpful discussions and suggestions. They
T. Ohira et al., “Development of key monolithic circuits to Ku-band full MMIC receivers,” in IEEE Microwure and Millimeter- Wace Monolithic Circuits Symp. Dig.,June 1987, pp. 69-74. T. Hirota and H. Ogawa, “Uniplanar monolithic frequency doublers,” IEEE Trans. Microwac,e Theory Tech., vol. 37, pp. 1249-1254, Aug. 1989. A. M. Pavio, S. D. Bingham, R. H. Halladay, and C. A. Sapashe, “ A distributed broadband monolithic frequency multiplier,” in IEEE MTT-S Int. MicrowaLz Symp. Dig., June 1988, pp. 503-504. T. Hiraoka, T. Tokumitsu, and M. Aikawa, “Very small wide band MMIC magic T’s using microstrip lines on a thin dielectric film,” IEEE Trans. Microwuc,e Theory Tech., vol. 37, pp. 1569-1575, Oct. 1989.
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Takahiro Hiraoka (A’87) was born in Oita, Japan, in 1960. He received the B.E. and M.E. degrees in electrical engineering from Oita University, Oita, Japan, in 1983 and 1985, respectivplv - -, In 1985, he Joined NTT Electrical Communicdtion LabOrdtOrieS, Kanagawa, Japan, where he did research on GaAs MMIC’s and their application to space-borne equipment for satellite communicdtionv In 1987, he joined A T R Opticdl and Radio Communications Research Laboratories, Osaka, Japan. There his research dealt with highly integrated MMIC‘s for future digital mobile communications. H e is now with the NTT Radio Communication Systems Laboratories, Kanagawa, where he has been engaged in research and development work on monolithic microwave and millimeter-wave integrated circuits and their applications. Mr. Hiraoka is a member of the institute of Electronics, Information and Communication Engineers of Japan.
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Tsuneo Tokumitsu (M’88) was born in Hiroshima, Japan, in 1952. H e received the B.S. and M.S. degrees in electrical engineering from Hiroshima University, Hiroshima, in 1974 and 1976. respectively. H e joined the Yokosuka Electrical Communication Laboratories, Nippon Telgraph and Telephone Public Corporation, Kanagawa, Japan, in 1976, where he did research on microwave and millimeter-wave integrated circuits, MIC’s, and MMIC’s and worked on the develomnent of on-board satellite equipment. In September 1986, he joined A‘TR Optical and Radio Communications Research Laboratories, Osaka, where he was engaged in research on highly integrated MMIC‘s for future digital mobile communications. In February 1990, he was appointed senior research engineer of the NTT Radio Communication Systems Laboratories, Kanagawa. Since then he has been engaged in the development of monolithic T R modules for digital radio trunk transmission systems. Mr. Tokumitsu is a member of the Institute of Electronics, Information and Communication Engineers of Japan.
HIRAOKA
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U / . : A M l N l A T l J R l Z E D RROAD-BAND MMlC FRFOlJENCY DOUBLER
Masami Akaike (S’65-M’84) was born in Kdmakura, Japan, on October 15, 1940 H e received the B Eng., M Eng., and D r Eng degrees in electronics engineering from the University of Tokyo in 1964, 1966, and 1969, respectively He joined the Electrical Communication Ldboratories, Nippon Telegraoh and Telephone Public Corporation, Tokyo, Japan, in 1969 From 1969 to 1981, he was engaged in the development of guided millimeter-wave trammission
1937 systems dnd terrestrial digital microwave systems In particular he was responsible for solid-state devices operating at microwave and millimeter-wave frequencies From 1982 to 1983, he worked on the design of ISDN test systems From 1983 to 1988, he was engaged in research on radio propagation and MMIC‘s. Currently, he is the head of the Radio Systems Department, ATR Optical and Radio Communications Research Laboratories, Kyoto, Japan, working on propagation characterization and microwave/millimeter-wave devices for mobile radio \ystems Dr Akaike IS now Vlce-Chairman of the Tokyo chapter of the IEEE Microwave Theory and Techniques Society
