A Narrow-Band Delta-Sigma Frequency-to-Digital Converter - CiteSeerX

7 downloads 0 Views 132KB Size Report
shifted from the analogue towards the digital domain. Delta-sigma techniques have also found their way to frequency-to-digital conversion systems [2], [3], [4]. In.
1

A Narrow-Band Delta-Sigma Frequency-to-Digital Converter Mats Høvin1 , Trond Sæther2 , Dag T. Wisland1 and Tor Sverre Lande1 1

Dept. of Informatics, University of Oslo, Blindern, N-0316 Oslo, Norway, [email protected] 2 Nordic VLSI A/S, Vestre Rosten 81, N-7075 Tiller, Norway, [email protected]

Abstract— This paper describes a novel frequency-to-digital conversion technique based on the D flip-flop frequency deltasigma concept. It is shown that given some frequency constraints, there is no need for using a sampling frequency twice the maximum FM frequency. For narrow-band FM demodulation, it is further shown that by sampling the clock signal width the FM signal, the digital resolution is more effectively increased by raising the constant clock frequency. A narrowband D flip-flop frequency-to-digital converter have been realized in a FPGA confirming the theory.

will be referred to as a sampled-clock system. In section V we finally present measured results from a sampled clock frequency-to-digital conversion system realized in a FPGA.

I. I NTRODUCTION

fm(t) = sin[θ(t)],

D

ELTA-SIGMA noise-shaping techniques [1] have found extensive use in both analog-to-digital and digital-to-analog conversion systems. The main reason for their popularity is that many of the Nyquist rate A/D and D/A implementational challenges are shifted from the analogue towards the digital domain. Delta-sigma techniques have also found their way to frequency-to-digital conversion systems [2], [3], [4]. In [5], [6], [7] it is shown that just by oversampling the traditional pulse-counting frequency-to-digital converter, equivalent delta-sigma noise-shaping results. A further result of this analysis is that for systems where the sampling frequency is more than twice the maximum FM frequency, the counter may be replaced by a standard D flip-flop. By using modulo arithmetic the dump and reset operation is carried out by a one-bit XOR gate (Fig. 1). θ(t) fm(t)

x(t) frequency modulator

count mod-2 D Q1 clk

D clk Q2

output bit stream

diff mod-2 fclk

Fig. 1. The standard D flip-flop frequency-delta-sigma modulator.

In section II we repeat the D flip-flop frequency deltasigma-modulator (FDSM) concept and present a system level simulation. In section III we show that a D flip-flop FDSM may also be used for sampling frequencies less than twice the maximum FM frequency given some frequency constraints. Section IV shows that by exchanging the D and clk inputs we keep an equivalent first-order delta-sigma conversion system where the digital resolution is increased more effectively by increasing the constant clock frequency. The new solution may be suitable for narrow-band FM demodulation and

II. T HE S TANDARD D F LIP -F LOP FDSM The D flip-flop FDSM is derived from the fact that a FM signal can be represented by

where θ(t) = 2π

Z

(1)

t

(fc + kx(τ ))dτ.

(2)

−∞

In this expression fc represents the carrier frequency, x(τ ) the modulating input signal, and k the frequency sensitivity. From Eq. 2 we see that the FM signal variable θ(t)/2π is the integral of fc + kx(τ ). By using a D flip-flop both as a hard-limiter and as a modulo-2 edge-counter we extract a quantized representation of the FM phase θ(t)/2π at time nTclk where Tclk is the sampling clock period. The quantization error will then be the scaled residual phase φn ∈[0, 1i given by the phase difference between the sampling clock edge and the previous FM edge as illustrated in Fig. 2. As both the integrated signal x(τ ) represented by θn and it’s quantization error are subsequently differentiated by the modulo-2 XOR differentiator, the quantization error will be shaped while the signal is just scaled and biased. fml (t)

φn

sample edge

Fig. 2. Quantization error φn relative to limited FM signal.

The D flip-flop FDSM signal-to-quantization noise ratio (SQN R) is given from [5], [7] as   3/2 !  π fmax SRo − 20 log , (3) 2 SQN R ≈ 20 log √ 6 fclk 2 where fmax is the maximum frequency of the modulating signal x(τ ) and fclk is the sampling frequency. Buried in the output bit-stream, the output signal

2

range (SRo ) is given by 4∆f/fclk where ∆f is the maximum frequency deviation of the FM signal. In Fig. 3 a system-level simulation of a D flip-flop FDSM is shown. The frequency modulator was modulated by a single sinusoidal signal at 3430Hz producing a frequency deviation of ±4MHz for a 40MHz carrier sampled at 100MHz. As we see, the frequency spectrum is shaped according to delta-sigma theory. Fig. 5. Measured passband noise against DC input for a traditional delta-sigma modulator. Oversampling ratio =73. The arrow indicates the calculated noise level.

Fig. 3. A 218 point FFT analysis of a D flip-flop FDSM output for a modulating input signal at 3430Hz, ∆f =4MHz, fc =40MHz and fclk =100MHz.

III. T HE R EDUCED S AMPLING F REQUENCY C ONCEPT The D flip-flop FDSM system is based both on modulo-2 counting and modulo-2 differentiation. This principle works well as long as the counted number of FM edges during the sampling interval is 0 or 1. However, the unambiguity of the modulo arithmetic will still be present if the counted number is any integer constant m plus 0 or 1. But this constraint may be satisfied even if the sampling frequency is less than twice the maximum FM frequency by omitting certain (fc ± ∆f)/fclk ratios. fm(t)

clk(t)

By increasing the fclk /fc ratio we notice that the output of the D flip-flop FDSM approaches an exact digital representation of the FM signal edge positions (Fig. 4). fml (t) Q1[n] out[n]

fml (t) Q1[n] out[n]

Fig. 4. D flip-flop FDSM intermediate/output signals. Top: modest fclk /fc ratio, bottom: high fclk /fc ratio.

By looking at Fig. 1 we also notice that phase modulating noise (clock jitter) enter the circuit after the integrator or frequency modulator and will hence be firstorder noise-shaped together with the quantization error. In a D flip-flop FDSM, the output signal range SRo will normally be very small compared to it’s corresponding integer quantization level interval. By choosing an appropriate fc /fclk ratio the signal range may therefore be shifted into a pattern nose ‘valley’ between the pattern noise peaks (Fig. 5).

Fig. 6. FM signal relative to sampling clock. Shaded areas indicate ambiguous regions.

To find these ratios we notice that the highest variation in possible edge counts will occur when the previous sampling edge is close to an FM edge (Fig. 6). To restrict the outcome to m + 0 or m + 1 we therefore must ensure that the next sampling edge must not occur in the shaded regions given by the FM deviation in Fig. 6. The frequency constraint will therefore be that the number of FM edges per second must not be divisible by the sampling frequency or  2(fc + δf) −∆f < δf < ∆f . (4) 6= m, m∈N fclk This statement may be formulated as

fclk 6∈ [2(fc − ∆f)/m, 2(fc + ∆f)/m], m ∈ N .

(5)

For a given m, the allowed samping frequencies will then be all frequencies determined by the corresponding shaded intervals in Fig. 6 which from Eq. 5 is fclk ∈ h2(fc + ∆f)/(m + 1), 2(fc − ∆f)/mi,

m ∈ N. (6) To find the maximum m or ‘squeezing’ limit the following statement must be true 2(fc + ∆f)/(m + 1) < 2(fc − ∆f)/m,

m∈N

(7)

3

and mmax