A New CMOS Differential Input FM Quadrature ...

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[6] Reinhard Reimann and Hans-Martin Rein, “Bipolar. High-Gain Limiting Amplifier IC for Optical-Fiber. Receivers Operating up to 4Gbit/s”, IEEE Journal of.
A New CMOS Differential Input FM Quadrature Demodulator Radu Gabriel Bozomitu, Vlad Cehan, and Robert Gabriel Lupu “Gheorghe Asachi” Technical University, Dimitrie Mangeron No. 67 Av., 700050, Iaşi, Romania [email protected], [email protected], [email protected]

Abstract: This paper presents a new CMOS differential input FM quadrature demodulator for

integrated circuits. The proposed circuit is based on Bilotti’s quadrature demodulator that uses an external differential phase shift network and a differential phase detector with a single ended output. The phase detector is represented by an analog multiplier implemented with a Gilbert cell and the phase shift network is an external RLC resonator circuit. The current consumption of the FM detection stage is about 258μA from a 3.3V supply voltage. The simulations performed in 0.13μm CMOS technology confirm the theoretical result.

1. INTRODUCTION Many solutions of FM signal demodulation have been used along the years [1-8]. FM detection can be realized on the basis of slope detector, Foster-Seeley discriminator, PLL demodulator, and quadrature demodulator [1-3]. The FM discriminators use a tuned RF transformer to convert frequency changes into amplitude changes. The FM slope detector uses the attenuation slope of a tuned circuit to convert frequency modulation into amplitude modulation that can be detected by using an envelope detector [1-3]. The block diagram of a VLSI receiver that is used in many FM radio, cellular telephone, and other communication systems is illustrated in Fig. 1 [1-4].

The limiter amplifier stage must be used before the FM detector, to remove amplitude variations in the signal which would be detected as noise. This circuit determines a large dynamic range with simple circuitry [3]. This paper presents a new CMOS implementation of the FM detector and limiting amplifier stages illustrated in the block diagram from Fig. 1. In Section 2 the principle of FM quadrature demodulator is presented. The VLSI implementations of the new differential input FM quadrature demodulator and the limiter amplifier stage in CMOS technology are presented in Sections 3 and 4. In Section 5 the simulation results of the proposed FM quadrature demodulator are illustrated. The conclusions are drawn in Section 6.

RF In

Phase shift network Mixer LNA

Band-select filter

IFA

LO

FM demod.

10.7MHz Limiting amplifier

Fig. 1. Block diagram of a typical VLSI receiver.

LFA

2. PRINCIPLE OF FM QUADRATURE DEMODULATOR

|H(jω)|

One of the usual methods of FM signal detection for integrated circuit is Bilotti’s quadrature demodulator [1-5]. The block diagram of this circuit, illustrated in Fig. 2, is composed of an external phase shift network, an analog multiplier and a low-pass filter (LPF). The FM signal at the circuit input can be written: t uMF ( t )  U 0 cos 0 t    u 1 ( )d  , u 1 ( t )  1 0  

uMF ( t )  U 0 cos 0 t   ( t )

(1)

where u 1 ( t ) is the low frequency modulating signal and ω0 ( 0  2  10.7e 6 rad/s ) is the intermediate frequency of the FM signal. The frequency response and the phase function of the phase shift network from Fig. 2 are given in (2) and (3), taking into account that      0   0 and

tan 1 x  x [3]: H ( j ) 





jQ C s C s  2C p    1  jQ  2 0 

(2)

      (3)  tan 1  Q    2Q 0  2 0 2  where Q is the quality factor and ω0 is the center frequency of the RLC circuit. If the center frequency of the phase shift network, ωx is different from center frequency of FM signal, ω0, as it is shown in Fig. 3, the expression of the phase shift signal is given by:     ud ( t )  U d cos  0 t   ( t )   2Q  0   x 2   (4)     U d sin  0 t   ( t )  2Q  0  x   where

 ( ) 



2

2 0

up(t)

VIP

uMF(t)

VIN

LPF

u JF(t) Vout

ud(t) Rp Cs

Cs

Lp

Phase shift network

Cp

Fig. 2. Block diagram of FM quadrature demodulator

ωx

φ(ω)

0 π/2

ω0

ω

ω

Fig. 3. AC characteristic (magnitude and phase vs. frequency) of the untuned external phase shift network (ω0 ≠ ωx).

0  2Q   x  0   x 

(5)

The output signal from the multiplier in Fig. 2 is: u p ( t )  uMF ( t )  ud ( t ) 

   sin  2 0 t  2 ( t )  2Q  0   2 x   k pU 0U d      0  sin  2Q 2 x   where kp is the gain of the multiplier. The low frequency component of the signal at LPF output from Fig. 2 is:   1  uJF ( t )  k pU 0U d sin  2Q  0  2 x   Since 2Q     x   x   6...  4 then from (7) and using sin x  x , results: 1  uJF ( t )   k pU 0U d 0  Qk pU 0U d  2 x 

k pU 0U d

 Qk pU 0U d  0   x 

(6)

the (7)

(8)

(9)

 x  k   u ( t )

where Δω(t) is the instantaneous frequency deviation which is linear dependent on the modulator signal, uΩ(t). From equation (9) we can notice a DC output offset ( Qk pU 0U d  0   x   x ), proportional with gain kp, magnitudes U0, Ud and phase shift 0 - see Fig. 3. In Section 5, the dependence of this DC offset voltage on passive component tolerance will be discussed. The DC offset voltage at the FM quadrature demodulator output is the main problem of this type of detector, which can be minimized only by using passive components with very low tolerance and by trimming.

3. FM QUADRATURE DEMODULATOR IMPLEMENTATION IN CMOS TECHNOLOGY In Fig. 4 is presented the electrical schematic of the proposed CMOS differential input FM quadrature demodulator with a single ended output. The main advantage of the proposed structure is represented by the differential connection of the phase shift network. The transfer function of the external phase shift network in Fig. 4 is the ratio of ΔV0(s) over ΔVin(s), given by:

 C s 2  Lp s V0 ( s )  (10) Vin ( s )  C p  C s 2  Lp s 2   Lp R p  s  1 2

H ( s) 

where V0 ( s )  V0 ( s )  V0 ( s ) , Vin ( s )  Vin ( s )  Vin ( s ) , Cs1 = Cs2 = Cs = 1.5pF. From (10), the center frequency and the quality factor of the phase shift network are given by: C p  Cs 2 1 ; Q  Rp (11) 0  Lp Lp C p  C s 2





As a consequence of     0   0 , the equation (10) reduces to (2). The phase shift network of the quadrature demodulator is implemented with an external LC tank (Lp = 14.004μH, Rp = 15kΩ, and Cp = 15pF) having a quality factor Q = 16. VDD W = 16u L = 2u

M18 W = 500n L = 8u

M9

M20 Cs1

1.5p

W = 32u L = 400n

M1

W = 16u L = 2u

Lp 14u

W = 32u W = 32u L = 400n L = 400n

M5

M12

In practical implementations the external phase shift network is implemented using ceramic filters.

P2 M21

 VV0N 0

W = 500n L = 8u

W = 16u L = 2u

M13

W = 16u L = 2u

M14

W = 32u L = 400n

W = 16u L = 2u

W = 16u L = 2u P4 W = 16u L = 2u

P6 P5

W = 8u L = 2u W = 8u L = 2u

2

Cf

M22 W = 500n L = 8u

M10

Cp 15p

Ibias M11

W = 16u L = 2u

Zp

W = 32u L = 400n

V

5. SIMULATION RESULTS

Rp 15k

W = 500n L = 8u

VIP  in

A gain stage of the limiting amplifier can be a conventional simple source-coupled pair with diode load as illustrated in [4]. Many limiting stage presented in the literature [67] require higher supply voltage. In Fig. 5 is shown the electrical scheme of differential limiter amplifier proposed in [4] used in our implementation to diminish the voltage magnitude at the FM demodulator input. By using the folded diode connected transistors M3 and M4, the supply voltage of this circuit can be significantly reduced [4]. The voltage gain and the dynamic range of the limiter amplifier from Fig. 5 have been established by the bias current and the device Q1,2, Q5,6 ratios.

P3

 VV0P 0

M19

M7

4. LIMITER AMPLIFIER STAGE

P1

1

W = 500n L = 8u

This network gives a 90° phase shift at the center frequency of 10.7MHz. Unlike other circuit solutions reported in the literature [5], the use of an external differential phase shift network (having the impedance Zp in Fig. 4) assures a performing rejection of the common mode perturbations and better EMC immunity of the circuit.

W = 32u L = 400n

M2 M3

R1

W = 32u W = 32u L = 400n L = 400n

W = 32u L = 400n M15

M4

25p OUT

M23 Cs2

1.5p

Rf

W = 500n L = 8u

500k W = 32u L = 400n

M8

M26

VIN

Vin

W = 3.8u L = 2u

M6

W = 16u L = 2u

M27

M16

W = 16u L = 2u

M17

M24

M25

W = 16u W = 16u L = 2u L = 2u

Fig. 4. Electrical schematic of CMOS with differential input FM quadrature demodulator.

W = 4u L = 500n W = 16u L = 2u

M9 M10

M12

Ibias Ibias

VDD

M5 M6

M11

M3

 VVIP in

M1

M2

 V VIN in

VON

M8

 Vout

M4

VOP

M7

 Vout

Fig. 5. Electrical scheme of limiter amplifier

Due to the difficulties of modeling the ceramic filters, in the following simulations we used a simple RLC filter. The proposed differential input FM quadrature demodulator is analyzed by simulation in 0.13μm CMOS technology. A supply voltage of 3.3V is used. The magnitude of the differential voltage Vin  Vin at the FM quadrature demodulator input is kept constant by using the limiter amplifier stage, illustrated in Fig. 5. First, the operation of limiter amplifier stage is analyzed by simulation in 0.13μm CMOS technology. In Fig. 6 the differential DC transfer characteristic of the circuit in Fig. 5 is presented. The limiter amplifier stage illustrated in Fig. 5 is designed in order to provide a differential input dynamic range of 224mVpp, as results from Fig. 6. In Fig. 7 is presented the differential output voltage of limiter amplifier stage for different values of the input voltage (100mVpp – 1Vpp). According to the simulation results illustrated in Fig. 7, the differential output voltage of the circuit in Fig. 5 is limited to 224mVpp.

Fig. 6. Differential DC transfer characteristic of limiter amplifier

Fig. 7. Differential output voltage of limiter amplifier for different values of input voltage (100mVpp – 1Vpp)

In Fig. 8 the AC characteristic (magnitude and phase vs. frequency) of the external phase shift network, for a center frequency of 10.7MHz, is presented. The proposed FM quadrature demodulator with limiter amplifier stage is analyzed for FM signals with three frequencies of the modulator signal in the audio domain (fm = 1kHz, 10kHz and 15kHz) and three values of frequency deviation Δf = 15kHz, 50kHz and 75kHz. Corresponding to these values of fm and Δf, results the values of frequency modulation index,    f f m used in the following simulations. In Figs. 9 a) – c) the demodulated output voltage for all these values of fm and Δf are presented.

Fig. 8. AC characteristic (magnitude and phase vs. frequency) of the external phase shift network

In practice, the center frequency of the FM signal, f0 is different from the center frequency of the phase shift network, fx, as it is shown in Fig. 3.

Vdemod β = 15

β = 50

β = 75

a)

b) -100k

a)

-50k

0

50k

100k

Δf0x ( Hz ) Fig. 10. DC offset (a) and THD value of the demodulated signal (b) depending on Δf0x

Vdemod β = 1.5

β=5

β = 7.5

b) Vdemod β=1

β = 3.33

β=5

c) Fig. 9. Demodulated audio signal for different values of frequency deviation (Δf) and modulation frequency: fm = 1kHz (a); fm = 10kHz (b); fm = 15kHz (c)

This situation generates a DC offset voltage (Voffset) to the circuit output (equation (9)), which is proportional with phase deviation 0 . This DC offset voltage cannot be eliminated by minimizing the parameters kp, U0, Ud and Q from (9), because the magnitude of the demodulated signal depends on the same parameters.

The values of DC offset were calculated as the difference between the average values of the demodulated signal and the common mode output voltage (VCM = 1.5V). That was done by simulating at different frequency deviations Δf0x = f0 - fx, see Fig. 10.a). Due to the DC offset, the operating point approaches to the non-linear region (saturation, blocking) of the transistors, the variable component of the signal is deformed and the level of distortion increases. This THD dependence on frequency deviation Δf0x is shown in Fig. 10.b). According to the simulation results (illustrated in Fig. 9) performed in 0.13μm CMOS process, the THD value of the demodulated signal is lower than 1% for all values of the modulating signal frequency in the audio domain (30Hz – 15kHz), considering Δf0x = 0. It is on interest the dependence of DC offset value on the components tolerances. Since the intermediate frequency comes from RF signal frequency and local oscillator frequency, usually done with frequency synthesizer, we can admit that the frequency f0=10.7MHz is kept constant. Thus, the offset Δf0x comes from the deviation of the phase shift network center frequency, fx, from the intermediate frequency f0. The center frequency of the phase shift network from Fig. 4 is: 1 (12) fx  2 Lx C x where C x  C p  C s 2 and Lx  L p . The ideal value of fx is: 1 f x 0  f0  2 Lx 0C x 0

(13)

relative deviation δfx of the phase shift network center frequency. In the same Table are given the relative deviations of the components ( C x C x 0   Lx Lx 0 ), which determines the relative frequency deviation δfx and, as consequence, the offset value, Voffset. According to the results in Table 1, in order to have a relative variation of DC offset lower than 3%, the external phase shift network must be implemented by using LC passive components having a tolerance lower than 0.1%.

implemented. As consequence, the circuit uses an external phase shift network, differential connected to assure a performing rejection of the common mode perturbations. In paper is shown that the DC offset at the FM quadrature demodulator output depend on the phase shift introduced due to variation of LC tank center frequency from the intermediate frequency of 10.7MHz. The value of DC offset at the circuit output is expressed as function of LC passive components tolerance. If the tolerance of these passive components is higher than 0.1%, the output DC offset can be minimized only by trimming. The THD value of the demodulated signal is lower than 1% for all values of the modulation frequency in the audio domain (30Hz – 15kHz). The simulations performed in 0.13μm CMOS technology confirm the theoretical result.

Table 1. Relative variation of DC offset due to deviation of LC components value from the phase shift network.

REFERENCES

From the equations (12) – (13), the relative frequency deviation of the phase shift network is:  f x 1  C x  Lx  (14)     fx   2  C x0 f x0 Lx 0  where ΔCx and ΔLx are total variation of Lx and Cx. In Table 1 is calculated, by simulation, the relative variation of DC offset ( Voffset VCM ) for different

Voffset (mV)

Δfx (kHz)

Voffset VCM (%)

δfx (%)

45 75 150 225 300 375 450 525

5 8 16 24 32 40 48 56

3 5 10 15 20 25 30 35

0.047 0.075 0.15 0.224 0.3 0.37 0.45 0.52

C x

 Lx  C x0 Lx 0 (%) 0.093 0.15 0.3 0.448 0.6 0.74 0.9 1.04

[1] Clarke, K.K., Hess, D.T., “Communication Circuits: Analysis and Design”, Addison-Wesley Co., USA, 1971; [2] Robert C. Dixon, “Radio receiver design”, Marcel Dekker, Inc., 1998; [3] Donald O. Pederson, Kartikeya Mayaram, “Analog Integrated Circuits for Communication - Principles, Simulation and Design”, Springer Science + Business Media, LLC, 2008; [4] Po-Chiun Huang, Yi-Huei Chen, and Chorng-Kuang Wang, “A 2-V 10.7-MHz CMOS Limiting Amplifier/RSSI”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 10, October 2000, pp. 1474-1480;

Otherwise, to minimize the DC output offset voltage, the external phase shift network must be realized on the basis of trimmer passive components. The main problem of this demodulation principle is represented by the DC output offset voltage depending on the deviation of the RLC network center frequency (due to passive components tolerances) from the intermediate frequency of 10.7MHz. This is the reason why it is very difficult to use a differential output for this type of demodulator.

[5] D. Coffing and E. Main, “A Quadrature Demodulator Tutorial”, EE Times, http://www.eetimes.com/document.asp?doc_id=1275839; [6] Reinhard Reimann and Hans-Martin Rein, “Bipolar High-Gain Limiting Amplifier IC for Optical-Fiber Receivers Operating up to 4Gbit/s”, IEEE Journal of Solid-State Circuits, vol. sc-22, no. 4, August 1987, pp. 504-511; [7] Renuka P. Jindal, “Gigahertz-Band High-Gain LowNoise AGC Amplifiers in Fine-Line NMOS”, IEEE Journal of Solid-State Circuits, vol. sc-22, no.4, August 1987, pp. 512-521;

6. CONCLUSION

[8] Andrei Drumea, “Education in development of electronic modules using free and open source software tools”, “HIDRAULICA”, Magazine of Hydraulics, Pneumatics, Tribology, Ecology, Sensorics, Mechatronics, ISSN1453-7303, no.3-4,2012, pp.54-60.

In this paper a new CMOS implementation of a differential input FM quadrature demodulator has been presented. Due to large values of passive LC component, the LC tank circuit cannot be VLSI