A New Design Methodology Based on System

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A New Design Methodology Based on System-Level Interconnect Prediction Dirk Stroobandt Ghent University, ELIS Dept., Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium. E-mail: [email protected] Abstract— In current deep sub-micron chip design, interconnect effects start to dominate the chip’s performance. Therefore, the design flow has to become more interconnect-oriented. To limit the number of design iterations (and hence improve the time-to-market) one has to estimate interconnect parameters and their impact as early as possible. This is the goal of the field of System-Level Interconnect Prediction. New research results are becoming available and the last couple of years have brought both more interest and more progress in the field than in the thirty years before. This paper is an introduction to the field and provides an overview of some of the recent advances in system-level interconnect prediction, including several applications.

I. I NTRODUCTION

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AINSTREAM processors today surpass gigahertz global clock frequencies. This achievement is due to an ever progressing technology allowing increased miniaturization of the active components (transistors) within chips (also known as Moore’s law: the number of transistors on a chip doubles every 18 months although the total chip area roughly remains the same). The downscaling of transistor feature sizes has some problematic consequences: • Since the processing of transistors includes a lithography step where light shines through holes in a layout masks, the accuracy of very small feature sizes depends on the wavelength of the light one uses. By going to ultraviolet light (smaller wavelengths) and using techniques such as Optical Proximity Correction1 (OPC, [26]) and Phase Shifting Masks2 (PSM, [28], [29]) one can alleviate the problem. Current breakthroughs in nanotechnology (transistors of the size of a molecule) also promise interesting solutions that will allow Moore’s law to continue for a while. • The speed of signals through the interconnections on a chip is not unlimited. As long as the wavelength associated with the propagation of signals is several times longer than the length of the interconnects, these interconnects can be treated as simple galvanic connections. Since the wavelength is inversely proportional to the signal frequency, increasing frequencies correspond to shorter wavelengths so that interconnections have to be treated as much more complex waveguides. For long interconnections (one side of the chip to another side of the chip) it currently takes several clock cycles for a signal to traverse the wire, hence the wire has a significant effect on the chip behaviour. • If interconnect dimensions would be scaled as transistor dimensions in subsequent technology generations, the delay of Dirk Stroobandt is a Postdoctoral Fellow of the Fund for Scientific Research (F.W.O., Flanders, Belgium). 1 In this technique one changes the mask so that negative effects of light interference are cancelled out. 2 In this technique one uses light with a different phase at neighbouring holes so that interference effects do not occur (or occur less).

signals in the wires would grow prohibitively. In practice, wires are not scaled (or even inversely scaled) which means that wires relatively take more space on the chip than for earlier generations. This means that interconnects now also take up a significant amount of chip area and are responsible for the larger part of the chip power consumption. The last two consequences show that the effects of the interconnection topology on the performance of the chip significantly increased and this has brought interconnects to the center of attention in chip design. Today, interconnects are the limiting factor for both performance and density, i.e., the value and the cost of a VLSI system. Due to these trends, chip planning and layout tools must embrace new paradigms. Where chip design used to be focused on the optimization of the functional blocks, these days one has to account for the wiring as well. Just considering interconnect issues within the current design flow soon will not suffice anymore. Therefore I advocate (together with others in the field) a completely new design methodology where interconnects are the center of attention. Because design tools and designers are used to focusing on the functional blocks within a chip, such a drastic change in design methodology is not feasible (at least not on short notice). However, introducing interconnect effects early in the design flow is a necessity. Today, a focal point for improved interconnect modelling, more cost-effective system architectures, and more productive design technology centers on new methods and models for a priori system-level interconnect prediction. Although basic works in this area are almost thirty years old, no cohesive research community for interconnect prediction was established until the First International Workshop on System-Level Interconnect Prediction (SLIP) [53] in April 1999. An overview of the basic concepts of and recent research work on a priori interconnect prediction is presented in a book completely devoted to this field [51] and a collection of recent research work can be found in two special issues of IEEE Transactions on VLSI Systems [61], [62]. In 2002, the SLIP Workshop will be held for the fourth time and a new special issue of TVLSI is planned. This paper aims at introducing the field of System-Level Interconnect Prediction and at providing an overview of recent research work in this new and exciting area. A first step towards an interconnect-centric design methodology is shown in Section II. Section III continues with an introduction on a priori interconnect prediction and the importance of Rent’s rule, the basis for all modelling. Section IV gives an overview of wire length estimation models and provides a common framework for such models. In Section V some applications of wire length estimations are presented.

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Fig. 1. The various steps of digital design (after [45]).

II. A N I NTERCONNECT- CENTRIC D ESIGN M ETHODOLOGY In order to design a digital system, quite a few design steps are necessary. The classical (linear) design flow is illustrated in figure 1. The design starts with a specification of the system to be designed. It is a high-level representation of the system containing requirements for performance, functionality, physical dimensions, power consumption etc. This representation is informal since it makes use of language, diagrams, plots etc. for formulating the problem. It is then transformed into a formal description of the system behaviour through the functional design step. In the logic design step, the arithmetic and logic operations that realize the behaviour of the functional design, are derived and tested. These operations are then transformed to a structural view on the design (circuit design) and this logical structure is further refined to a physical structure as a realization in a certain technology. It is only in this design step, the layout generation or the physical design step, that the system acquires its final form as a chip, a board, motherboard or cabinet and that the interconnections obtain their fixed form as real (physical) wires. The fabrication, packaging and testing of the chip finally produce the end product. The linear design flow of figure 1 only marginally accounts for the interconnections. It is mainly focused on the functional implementation. As stated in the introduction, this was a viable approach until the introduction of Deep Sub-Micron

(DSM) technologies where the effects of the interconnections on performance, area and power started to prevail. Performance evaluation after physical layout nowadays always reveals several problems that result in the chip not following the specifications. Therefore, several iterations are needed on the physical design step to get everything right (loop A in figure 1). Most of the times, not all problems can be solved by a physical redesign alone and one has to go back to a circuit redesign (loop B). Sometimes one even has to redesign the logic or perform a different functional decomposition (loop C). Iterations in the design flow naturally are time-consuming and in the light of current time-to-market requirements one has to limit the number of iterations drastically. A completely new design approach that centers on the interconnections first and the functions later (an interconnect-centric design approach) is the ideal solution in the changed design environment but it is not feasible on a short term because all Computer-Aided Design (CAD) tools and thousands of experienced designers are targeted on the functionality-based design flow. An intermediate solution therefore introduces estimations of physical and technological parameters and their influence on the design at early design stages. The sooner one can add such a priori design estimations to the design flow, the better the designer can anticipate physical problems leading to fewer design cycle iterations. That is the goal of the a priori interconnect prediction methods presented in this paper.

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Fig. 2. The three components of models for physical design: the circuit, the chip architecture and the layout generation. The combination of these models results in the (model for the) layout.

III. A P RIORI I NTERCONNECT P REDICTION AND R ENT ’ S RULE A. Focus on Layout CAD Tools The physical design step consists of the consecutive steps of floorplanning (roughly deciding where functional blocks will be placed on the chip layout), placement (a detailed placement of the gates – a collection of transistors – on the chip layout) and routing (assigning routes to interconnects between gates). The Computer-Aided Design (CAD) tools for placement of logic gates in a circuit optimize for small interconnection lengths between gates or, alternatively, for small delays in the critical wires.3 This requires knowledge of the interconnect routing. Routing, on the other hand, can only be done after the place of the gates is known. Hence, during the layout of computer chips, also several iterations between placement and routing are needed. To reduce or even eliminate the number of placement/routing iterations, a priori estimations of interconnection lengths are very helpful because they allow an evaluation of placements without a routing step, leading to a better initial placement and a better initial routing result. CAD tools for layout generation therefore especially benefit from a priori (i.e., pre-layout) wire length estimation techniques [47], [50]. Current applications of a priori interconnect estimation are found in technology extrapolation [4], e.g., the International Technology Roadmap for Semiconductors (ITRS) [44]. For estimations of the performance of future designs, very little is known about the design and a priori techniques are essential. The same applies to the evaluation of new chip architectures. A priori estimates immediately provide a solid ground for drawing preliminary conclusions about the benefits of new chip architectures and for comparing different architectures. These applications are discussed in Section V. However, applications of a priori estimation on even higher levels of abstraction (earlier in the design flow) are needed and very useful for, e.g., (i) early eval3 Critical wires are those wires that are on a long chain of interconnections that

have to be traversed by a signal in a single clock cycle.

uation of functional hardware decompositions; (ii) early exploration of hardware (and software) implementations in the partitioning phase between hardware and software blocks in embedded systems; and (iii) early evaluation of processor architecture decisions [5], [21]. B. A Priori Interconnect Prediction Models A priori interconnect estimation typically requires three models (Figure 2): (i) a circuit model (ii) a model for the physical chip architecture in which the circuit will be placed, and (iii) a model for the layout generation (placement and routing). Current practice models the circuit as a collection of logic gates connected to each other through interconnections, models the chip architecture as a (two-dimensional) Manhattan grid, and assumes a “good” placement (i.e., one that successfully minimizes wire lengths) and enough space available to route all interconnects along the shortest (Manhattan) path. However, these simple models do not suffice to make powerful estimations about the resulting layout. For this, one needs to have a notion of (i) the complexity of the interconnection topology and (ii) the quality of the placement. This information is provided by the so-called Rent’s rule. In 1971 Landman and Russo [31] described a relationship between the average number of terminals T of a part of the circuit (a module) and the average number of logic gates (basic logic blocks B) inside the module (basically a relation between interconnect and logic). This relation is given by T = tB p

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and is called Rent’s rule. The parameter t is the average number of terminals per logic gate and the exponent p is the Rent exponent. Its value depends on the complexity of the interconnect topology and on the quality of the placement.4 The maximal 4 Both a more complex interconnect topology and a less optimized placement are reflected in a higher Rent exponent. A discussion of these different aspects of the Rent exponent can be found in [70], [73].

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Fig. 3. Donath’s placement model: recursive partitioning of both circuit (a) and Manhattan grid (b) and mapping of circuit parts to grid parts.

value of the Rent exponent p is 1 for a very complex topology or a random placement [12]. Rent’s rule proves to be valid for most designs and it is recently shown that it applies to any homogeneous design [12]. Rent’s rule has also been extended for rectangular regions in [14], [15] and for heterogeneous systems in [74], [76]. A circuit partitioning (as in Figure 3) results in a log-log plot of number of terminals versus number of logic gates as in Figure 4. The validity of Rent’s rule follows from the fact that all points follow – on average – a straight line in the plot. The deviation from the straight line for high values of T and B is known as Rent’s region II and has been described in [31], [66]. Recently, Christie [10] has presented a more accurate derivation of Rent’s rule that also accounts for the region II behaviour. Another deviation at the low end (called region III) is described in [46]. With Rent’s rule, sufficiently accurate estimates of interconnection lengths can be made. In the remaining of this paper the use of Rent’s rule for wire length estimation is described. Some direct applications of Rent’s rule include (i) estimations of the number of terminals to aid circuit partitioning [48] and (ii) generation of benchmark circuits for evaluating physical design tools [16], [52], [60], [71].

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Fig. 4. Rent’s rule: number of terminals per module T versus number of gates per module B during the partitioning of a benchmark circuit (ISCAS89 [3] benchmark ‘s953’) with the ‘ratiocut’ partitioning method [72]. The size of the circles corresponds to the percentage of modules (on a total number of modules around an average number of gates, at equal distances in the log-log plot) that has B gates and T terminals.

   

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IV. W IRE LENGTH E STIMATION A. Donath’s Model Rent’s rule has been used for wire length estimation for the first time by Donath in 1979 [19]. The idea is simple: the circuit is partitioned hierarchically into equally large parts (see Figure 3(a); four parts in each hierarchical step). The Manhattan grid is partitioned as well in a symmetrical way (Figure 3(b)) and each circuit part is mapped to a grid part. This partitioning process is repeated recursively until all logic gates are assigned to a single grid cell in the Manhattan grid. The average number of interconnections between parts at a certain hierarchical level is estimated from Rent’s rule (details can be found in [19]) and the average length of a connection at each hierarchical level is estimated by assuming that source and destination cells are uniformly distributed over the grid part for that hierarchical level (Figure 5). This placement model ensures that shorter interconnects (at deeper hierarchical levels) will outnumber longer ones (due to the use of the hierarchical model together with Rent’s rule) but keeps the placement of cells within a hierarchical part simple (random). Despite the simplicity of Donath’s model, it is able to predict the scaling of the average wire length as a function of circuit size quite well. Figure 6 shows that circuits of low complex-

  

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Fig. 5. The average length on a hierarchical level is estimated by assuming that source and destination cells are uniformly distributed over the grid cells within the partition. We distinguish adjacent combinations (a) and diagonal combinations (b).

ity (p < 0.5) result in an average wire length that converges to a constant value (depending on the value of the Rent exponent) for large circuits. The average wire length of circuits of average complexity (p = 0.5) scales with the logarithm of the circuit size and for complex circuits the average wire length increases without bounds for increasing circuit sizes. This result has also been observed for real circuit placements. However, Donath found that his quantitative average wire length predictions were approximately a factor of 2 off from measured values for real circuits, as can be seen from Figure 7.

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Fig. 16. Average wire length as a function of number of layers and the cost of the third dimension interconnection. For higher costs, the optimal number of layers (for minimal average length) decreases.

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Fig. 17. Opto-electronic demonstrator. Inset: partially packaged opto-electronic FPGA (Field Programmable Gate Array) chip.

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