A New Diode Clamping Multilevel Inverter - Ivo Barbi

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Phone: +41- 1-632-6973 Fax: +41-1-632- 1212. Abstract: .... In cell (a), Sz, S3 and S4 are always ... S3 and S3' work alternatively connecting the inverter output.
A New Diode Clamping Multilevel Inverter Xiaoming Yuan

Ivo Barbi

Power Electronics and Electrometrology Laboratory Swiss Federal Institute of Technology Zurich ETH-Zentrum / ETL, CH-8092 Zurich Switzerland Phone: +41- 1-632-6973 Fax: +41-1-632- 1212

Power Electronics Institute Federal University of Santa Catarina P. 0. Box: 51 19, 88040-970, Florianopolis-SC Brazil Phone: +55-48-331-9204 Fax: +55-48-234-5422

Abstract: This paper proposes a new diode clamping multilevel inverter, which gets rid of the need for series association of the clamping diodes in the conventional diode clamping multilevel inverter. The new diode clamping inverter utilizes the same number of switches and diodes as the conventional one for synthesizing an inverter of a given level. Operation fundamentals, clamping mechanism as well as experimental verifications are presented.

I. INTRODUCTION In response to the growing demand for high power inverter unit, multilevel inverters have been attracting extensive attention from academia as well as industry in the recent decade. Among the best known topologies are the Hbridge cascade inverter, the capacitor clamping inverter (imbricated cells), and the diode clamping inverter. Literature review shows that the H-bridge cascade inverter has been used in several instances for broadcasting amplifier [l], plasma [2], industrial drive [3] as well as STATCOM [4] applications etc.. The main limitation consists in the provision of isolated supply for each individual H-bridge cell when real power is demanded. For STATCOM application, the power pulsation at twice output frequency occurring with the DC link of each H-bridge cell necessitates over-sizing of the DC link capacitors. The capacitor clamping inverter, though proposed in the early 80’s [5], had been rarely discussed internationally until the introduction of the “imbricated cells” [6]. Unlike the normal DC link capacitor which is always required to offer energy storage, the clamping capacitor needs only to smooth the switching frequency ripple and therefore the capacity is small. However, as the number of level increases, thermal designing, low-inductance designing, as well as insulation designing of the system will become critical. The Neutral-Point-Clamped (NPC) inverter [7] [8] was introduced also in the early 80’s and has been extensively used today in various applications. The three level diode clamping structure was later extended to multilevel by different authors [9] [IO] [ l l ] in the early 90’s. A five level structure of which is illustrated in Fig. 1. Despite the continuous research inputs from both academia and industry, no practical applications have been reported yet. In addition to the DC link unbalance problem which has been well investigated [I21 [ 133, other problems with the structure are briefed in the following [14]: a. Indirect Clamping of the Inner Devices: Unlike the normal two level inverter, switching devices in the diode

0-7803-5160-6/99/$10.000 1999 IEEE.

Fig. I . Conventional diode clamping inverter (five level).

clamping inverter, except for the lateral two, are actually not directly clamped to the DC link. Any indirectly clamped device may have to see more than the nominal blocking voltage, which is VdJ(M-l) for a M-level inverter. b. Tum-on Snubber f o r the Inner DC Rails: Similar to the matrix converter, each inner DC rail in the diode clamping inverter carries bidirectionally controlled current, preventing the use of polarized turn-on snubber. Nonpolarized snubber is known to be especially inefficient [ 151. c. Multiple Blocking Voltage of the Clamping Diodes: Unlike each main switch, the blocking voltage of each clamping diode in the diode clamping inverter is dependent on its position in the structure. For a M-level leg, one can find two diodes each sees blocking voltage of M-I-k (1) Vdiode =

M - ] ”‘

where M is the number of inverter levels, k goes from 1 to M-2 and Vdcis the total DC link voltage. Indirect clamping problem comes inherently with the diode clamping structure of the circuit. Unless an active switch be put in parallel with each clamping diode (which achieves direct clamping), the problem may not be easily removed. However, the problem will be mitigated when construction inductance is reduced. The turn-on snubber problem prevents the use of GTOs in the diode clamping inverter, as a turn-on snubber is mandatory when GTOs are used. Therefore, the capacity a diode claming inverter can reach is limited to IGBTs.

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However as today’s high power IGBTs are approaching the traditional domain of GTOs, the problem will no longer be critical in terms of inverter capacity. Conventional solution to the clamping diodes multiple blocking voltage problem has been to put appropriate number of diodes in series [16], as shown in Fig. 2. The possible over-voltage across the series diodes due to the diversities of diodes switching characteristics as well as their stray parameters calls for large RC snubbing network to be introduced leading to expensive and voluminous system. It is therefore the objective of this paper to discuss an alternative diode clamping inverter free of this problem.

always ON, while S4 and S4’ work alternatively connecting the inverter output to -vdc/4 and -vd&2respectively.

T Fig. 3. Proposed new diode clamping inverter (five level).

Each switching cell works actually as a normal two level inverter, except for that each forward or freewheeling path in the cell involves M-1 devices rather than only one. Taking cell (b) as an example, the forward path of the uparm involves DI, Sz, S3 and S4, whereas the fi-eewheeling path of the up-arm involves SI, Dlz, D8 and Dz, connecting the inverter output to VdJ4 level for either positive or negative current flow, as shown in Fig. 5(a). Meantime, as shown in Fig. 5(b), the forward path of the down-arm involves SI’, Sz’ Dlo and D4,whereas the freewheeling path of the down-arm involves D3, D7, S3 and S4, connecting the

T Fig. 2. Conventional diode clamping inverter with series clamping diodes (five level).

inverter output to 0 level for either positive or negative

11. PROPOSED INVERTER AND ITS OPERATION

current flow. The following rules govern the switching operation of a M-level diode clamping inverter: a. At any moment, there must be M-1 neighboring switches that are ON. b. For each two neighboring switches, the outer switch can only be turned on when the inner switch is ON. c. For each two neighboring switches, the inner switch can only be turned off when the outer switch is OFF.

The proposed diode clamping inverter is shown in Fig. 3. For the five level case, a total of eight switches and twelve diodes of equal voltage rating are used, which are the same with the conventional one. This pyramid architecture is extensible to any level unless otherwise practically limited. A M level inverter leg requires (M-1) storage capacitors, 2(M-1) switches and (M-l)(M-2) clamping diodes.

A. Switching Cells and ForwaraWreewheeling Paths

B. Clamping Diodes Blocking States

The new hverter can be decomposed into two-level switching cells as its basic operation units. For the five level case, one can define (5-1) switching cells as shown in Fig. 4(a), (b), (c) and (d). In cell (a), Sz, S3 and S4 are always ON, while SI and SI’ work alternatively connecting the inverter output to v d & ? and vd&4respectively. Similarly, in cell (b), S 3 , S4 and S I ’are always ON, while S2 and S2’ work alternatively connecting the inverter output to Vd‘J4 and 0 respectively. In cell (c), S4, SI’and SZ’are always ON, while S3 and S3’ work alternatively connecting the inverter output to 0 and -Vdc/2 respectively. In cell (d), SI’, S2’ and S3’ are

Clamping diodes change their blocking states as the switches change their states. With inverter output connected to certain level by relevant switches, the involved clamping diodes will block zero voltage whereas the remaining clamping diodes will block zero or the nominal voltage dependent on their positions in the clamping network. As an example, when inverter output is connected to level 0 with switches S3. S4, SI’ and Sz’ON, as shown in Fig. 6(c), the involved clamping diodes including D3, D4; D7, Ds, Dg, Dlo; and D I I ,D12 will all block zero voltage. All

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A

A

-#

cell (a): S,/S,' alternating

-

A

cell (b): S*/S2' alternating

I

A

cell (c): S3/S3' alternating

h

Fig. 4. ?he four switching cells of the proposed new diode clamping multilevel inverter.

A

(b): d 0 w n - m forwardfreewheeling paths

(b): UP-forwardlfreewheeling paths

T Fig. 5. Forward and freewheeling paths for the up and down arms of cell (b).

497

T

h

T

A

A

(e): sI’,s2’,s,’,s4’

498

Fig. 6. Changes of the clamping diodes blocking states in relation with the blocking states of the switchs.

outside terminals of the arm including a, b, c, d and e will be of the same potential at 0. Then D2 must block the nominal voltage as its cathode terminal is at level VdJ4 whereas DS must also block nominal voltage as its anode terminal is at level -VdJ4. Besides, as S I and S4’ are OFF, DI and D6 must block zero voltage. When inverter output is connected to Vd,/2, VdJ4, -VdJ4 or -VdJ2, as it may happen, the corresponding clamping diodes blocking states can be deducted similarly, as shown by the other diagrams in Fig. 6. As an observation, D I , D7, D I I always follow SI’; D3, D9 always follow S2’; DS always follows S3’; whereas Dg. Dlo, DI2 always follow SJ; D4, Dx always follow S3; D2 always follows S 2 , without regard to the inverter output level. Output voltage synthesizing in association with blocking states of switches and clamping diodes is shown in Fig. 7.

SI’

SI’

........................

s2

S2’

.............. S3‘ ........

S3’

.......

tVtkI4 r

I I

Vs3‘ms VS4’

b

I

Vsmm,omn VEIIMIDX

1

I

Vsm2 VSI

I

b

b

.+VSI.mlm71DI

vS2‘/DWW

I

A

b

+

S.

I

b

S?’

...............

SI

I

I

...............................

............................... ......................

while DI is directly clamped to C1by D,,. Suppose that for cell (a), Sz’, S3’ and S4’ each blocks VdJ4 voltage, and DZ, D8. D12 each blocks zero voltage. Then, SI and SI’,DI, D7, D I are ~ all clamped to C, at VdJ4 when OFF. Among which SI and DI are directly clamped while SI’, D7 and D I I are indirectly clamped. Similar mechanism can be witnessed with cell (b), where DZ. D3 are directly clamped to Cz, while Sz’, D9, SZ are indirectly clamped to Cz. In cell (c), D4, D5 are directly clamped to C3, while S3’, S3, D8 are indirectly clamped to C3. In cell (d), SJ’, D6 are directly clamped to C4, while S4, Dlo, Dl2 are indirectly clamped to C4. Graphical illustration of the clamping mechanism for the new diode clamping inverter is shown in Fig. 8(a)(b).

I

I

b b b

(a) clamping mechanism for the down-arm switches

b b

I

F

_L

w

Fig. 7. Inverter output voltage synthesizing in association with the blocking states of switches and clamping diodes.

111. SWITCH AND DIODE CLAMPING MECHANISM A. Switch and Diode Clamping Mechanism As the name of the diode clamping inverter implies, any main switch in the string at blocking state must be clamped to a corresponding DC link capacitor via relevant clamping diodes. By which, blocking voltage of the switch will be constrained to the nominal value. This mechanism in the proposed diode clamping inverter will be discussed below. Refering back to Fig. 5, in cell (a), Sz, S3 and S4 are always ON, while S2’, S3’ and S4’ are always OFF, SI and SI’ work alternatively connecting the inverter output to VdJ2 and VdJ4 respectively. Obviously, SI is directly clamped to CI by DI after it’s turn-off, while SI’ in series with Dz, Dx and DI2is indirectly clamped to CI by D,I, Ds2, Ds3and Dd after its turn-off. Further, DII in series with D2 and D8 is indirectly clamped to CI by Dsl, Ds2and Ds3; D7 in series with Dz is indirectly clamped to CI by D,I and Ds2,

(b) clamping mechanism for the up-arm switches Fig. 8. Clamping mechanism for the new diode clamping inverter.

In summary, for the proposed new diode clamping inverter, not only the switches are clamped, so are the clamping diodes. Among which, the 8 lateral devices ( S I , S4’, DI, Dz, D3, D4, D5,and D6) are directly clamped, 499

whereas the remaining devices (S2, S3, Da, S4, Dlo, D12,SI’, D7, D I 1 , S2’, Dg, S3’) are indirectly clamped, to the corresponding DC link capacitor.

B. Indirect Clamping and Blocking Voltage Distribution Indirect clamping will possibly result in unequal voltage distribution among the blocking devices, due mainly to the stray inductances in the diode clamping network. In the following context, the commutation process from S I ’ ,D12, D8, D2 to Ds4, Ds3, Ds2, DSIwill be considered. As SI’ is indirectly clamped, S I ’ and D I Iand D7 will have to block more than the nominal voltage during the OFF state. Upon the releasing of the turn-off signal for S I ’ ,the stray capacitance of S I ’ will first be charged. Until the voltage across the stray capacitance reaches vdc/4, freewheeling diodes D,,, Ds2, Ds3, and Ds4 will conduct, leading to demagnetization of the parasitic inductance in the clamping path, as shown in Fig. 9. The stray capacitance of S I ’ will continue be charged, whereas the stray capacitances of Sz’, S3’ and S4’ will be discharged. Such over-charging and discharging will not be recovered subsequently, as the discharging path for the stray capacitance of SI’, and the charging path for the stray capacitances of Sz’, S3’ and S i are both blocked by D2, Da and DI2. Consequently, SI’ will block more than vd44 while S2’, S3’ and S4’ together will block less than 3Vdc14 during the steady state. Moreover, Dz, Ds and DI2together sees the difference between the blocking voltage of SI’ and v d & . Meanwhile, D I Isees vdJ4 plus Vm and VD8, D7 sees vd44 plus V D ~while , DI sees Vdd4.

voltage while the inner device will always block more voltage. The center device will always be exposed to the highest voltage stress. Unequal blocking voltage distribution problem arising from indirect clamping exists also with the conventional diode clamping inverter as mentioned before. The severity of this problem is dependent on the stray inductances of the clamping network. With refined bus-bar designing technique, the problem will be mitigated. Naturally, the number of level will be limited due to this problem.

Iv . FURTHER COMPARISON WITH THE CONVENTIONAL DIODECLAMPING INVERTER The new diode clamping inverter can be further compared to the conventional one in the following aspects: a. Turn-on snubber problem in the conventional diode clamping inverter remains in the new structure. However, the new structure offers significant convenience for turn-off snubbing or clamping arrangement. This feature is deemed practically interesting as a turn-off snubbing or clamping is always interesting for IGBTs. The details of which will be addressed in a future occasion. b. DC link unbalance problem of the conventional inverter remains with the new structure, with exactly the same reason. This implies that the diode clamping inverter may be more applicable for STATCOM application.

v. EXPERIMENTATION RESULTS A scaled laboratory prototype has been built for verification of the new diode clamping inverter. For the half bridge five level prototype, four 120V DC power sources each in series with a lOmH inductor are employed to establish the four separate DC supplies for the DC link. A 8mH inductor in series with a 12R resistor are connected between the inverter output and the DC neutral point. Fundamental frequency modulation scheme eliminating the 5th and the 7th harmonics is implemented. Fig. 10 (a) (b) (c) and (d) shows the experimental output voltage in relation to the blocking voltages across S4, S3, S2 and S I respectively, which clearly demonstrate the operation of the proposed new diode clamping inverter.

k

E

Fig. 9. Stray inductance demagnetizationduring the commutation process from SI’,D ~ zDE , and D1 to D.1, Ds2, D,.cand Dd.

Indirect clamping and the subsequent unequal blocking voltage distribution problem holds also for S2’ and Sa, S3’ and S3, and S4 together with their relevant clamping diodes in cell (b), cell (c) and cell (d). Due to the fact that the stray capacitance of the neighboring outer switch experiences one more discharging than the inner switch, the outer switch will always block less

1OoVlDiv; 4mSDiv

(a) output voltage in relation to Sq voltage

500

REFERENCES [ l ] W. Schminke, “High Power Pulse Step Modulator for 500KW Short Wave and 600KW Medium Wave Transmitters”, Brown Bovery Review, Vol. 72, No. 5, 1985, pp. 235-240. [2] M. Marchsoni, M. Mazzucchelli and S. Tenconi, “A Non-conventional Power Converter for Plasma Stabilization”, IEEE Trans. on Power Electronics, Vol. 5 , No. 2, April 1990, pp. 212-219. [3] P. W. Hammond, “A New Approach to Enhance Power Quality for Medium Voltage AC Drives”, IEEE Trans. on Ind. App., Vol. 33, No. 1, Jan./Feb. 1997, pp. 202208. [4] J. D. Ainsworth, M. Davies, P. J. Fitz, K. E. Owen and D. R. Trainer, “Static Var Compensator (STATCOM) Based on Single Phase Chain Circuit Converters”, IEE Proc. -Gener. Transm. Distrib., Vol. 145, No. 4, July 1998. [5] T. Maruyama and M. Kumano, “New PWM Control for A Three-Level Inverter”, Record of IPEC, 1990, pp. 870-877. [6] T. Meynard and H. Foch, “Multi-Level Conversion: High Voltage Choppers and Voltage Source Inverters”, Record of IEEE PESC, 1992, pp. 397-403. [7] J. Holtz, “Self-Commutated Power Converter with Stair Cased Output Voltage for High Power and High Switching Frequency”, Simens Research and Development Report, Vol. 6, No. 3, pp. 164-171, 1977. [8] A. Nabae, I. Takahashi, and A. Akagi, “A New NeutralPoint Clamped P W M Inverter”, IEEE Trans. Ind. App., Vol. 19, No. 5,Sep./Oct. 1981, pp. 518-523. [9] J. M. Andrejak and M. Lescure, “High Voltage Converters Promising Technological Developments” , Record of EPE Conference, 1987, pp. 1.159-1.162. [lo] N. S. Choi, J. G. Cho, and G. H. Cho, “A General Circuit Topology of Multilevel Inverter”, Record of IEEE PESC, 1991, pp. 96-103. [ 111 M. Carpita, S. Tenconi, “A Novel Multilevel Structure for Voltage Source Inverter”, Record of EPE Conference, 1991, pp. 1. 90-1.94. [12] F. Z. Peng, J. S. Lai and J. MeKeever, “A Multilevel Voltage-Source Converter System with Balanced DC Voltages”, Record of IEEE PESC, 1995, pp. 1144-1150. [13] F. Z. Peng and J. S. Lai, “A Static Var Generator Using a Staircase Waveform Multilevel Voltage Source Converter”, Record of Power Quality Conference, Sep. 1994, pp. 58-66. [ 141 Xiaoming Yuan, “Soft Switching Techniques for Multilevel Invreters”, Ph. D Thesis, INEP-UFSC, Brazil, May, 1998. [ 151 W. McMurray, “Efficient Snubbers for Voltage Source GTO Inverters”, IEEE Trans. on Power Electronics, Vol. 2, NO. 3, July 1987, pp. 264-272. [16] J. S. Lai and F. Z . Peng, “Multilevel Converters-A New Breed of Power Converters”, IEEE Trans. on Ind. App., Vol. 32, No. 3, MayIJune 1996.

(b) output voltage in relation to S3 voltage

lM)V/Div; 4mSIDiv (c) output voltage in relation to Sz voltage

IOOViDiv; 4mSDiv

(d) output voltage in relation to SI voltage Fig. IO. Experimental output voltage of the new inverter in relation to the blocking voltages across SJ, S3, S l . and Sf respectively.

VI. CONCLUSIONS From the analysis and experimentation presented above, the proposed new diode clamping inverter solves the diodes series problem of the conventional structure. It further offers significant convenience in turn-off snubbing or clamping arrangement. The other aspects of the circuit as indirect clamping, DC link unbalance, device utilization etc. remain unchanged. The proposal represents an improved structure for large power conversion and may facilitate the practical application of the diode clamping inverter.

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