A New Hybrid Boosting Converter for Renewable Energy Applications

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 2, FEBRUARY 2016

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A New Hybrid Boosting Converter for Renewable Energy Applications Bin Wu, Student Member, IEEE, Shouxiang Li, Student Member, IEEE, Yao Liu, and Keyue Ma Smedley, Fellow, IEEE

Abstract—A hybrid boosting converter (HBC) with collective advantages of regulation capability from its boost structure and gain enhancement from its voltage multiplier structure is proposed in this paper. The new converter incorporates a bipolar voltage multiplier, featuring symmetrical configuration, single inductor and single switch, high gain capability with wide regulation range, low component stress, small output ripple and flexible extension, which make it suitable for front-end PV system and some other renewable energy applications. The operation principal, component stress, and voltage ripple are analyzed in this paper. Performance comparison and evaluation with a number of previous single-switch single-inductor converters are provided. A 200-W 35 to 380 V second-order HBC prototype was built with peak efficiency at 95.44%. The experimental results confirms the feasibility of the proposed converter. Index Terms—Bipolar voltage multiplier (BVM), hybrid boosting converter (HBC), nature interleaving, renewable energy, singleswitch single inductor.

I. INTRODUCTION N recent years, the rapid development of renewable energy system calls for new generation of high gain dc/dc converters with high efficiency and low cost. The front end of “Plug and Play” PV system usually demands step-up converter which is capable of boosting the voltage from 35 to 380 V with regulation capability due to the low terminal voltage and the requirement of MPPT tracking function for single PV panel. Considering a wind farm with internal medium-voltage dc (MVDC)-grid system, a MVDC converter able to boost the voltage from 1–6 to 15–60 kV is required to link the output of generator-facing rectifier to the MVDC line [1]. Some other energy storage systems such as fuel cell powered system also require high-gain dc/dc converter due to their low voltage level at storage side. In order to achieve high voltage conversion ratio with high efficiency, many high gain enhancement techniques were investigated in the previous publications. Among them, switchedcapacitor structure [2], [3], tapped/coupled inductor-based technique [4], [5], transformer-based technique [6], [7], voltage multiplier structure [8], [9] or combinations of them [10]– [12] attracted significant attentions. Each technology has its

I

Manuscript received November 24, 2014; revised January 30, 2015; accepted March 24, 2015. Date of publication April 8, 2015; date of current version September 29, 2015. Recommended for publication by Associate Editor M. M. Peretz. The authors are with the Department of Electrical Engineering and Computer science, University of California, Irvine, CA 92617 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2015.2420994

unique advantages and limitations. The switched capacitor dc–dc converter can achieve high efficiency but has pulsating current and poor regulation capability. Introduction of resonant switched-capacitor converter can alleviate the pulsating current but does not solve the regulation issue [13]. The tapped-inductor and transformer facilitates gain boosting function but requires snubber circuit to handle leakage problem [14]. The combination of above technologies usually yields promising circuit features but with excessive number of components [12]. In this paper, gain enhancement technology based on modification of traditional boost converter while maintaining single inductor and single switch is investigated, targeting at simplifying the circuit design, reducing the cost, satisfying the demands of normal high gain applications, and facilitating mass production. The idea of gain enhancement from a boost converter started from quadratic boost [15]. It achieved higher voltage gain with a single switch, yet introduced high component voltage stress. Nevertheless, this converter motivated high gain converter development follow on. Many gain extension methods of boost converter by adding only diodes and capacitors were investigated in the past. The method of combining boost converter with traditional Dickson multiplier and Cockcroft–Walton multiplier to generate new topologies were proposed in [16], such as topologies in Fig. 1(a) and (b). Air core inductor or stray inductor was used within voltage multiplier unit to reduce current pulsation in [17]. An elementary circuit employing the super lift technique was proposed in [18] and extended to higher gain applications such as Fig. 1(c). Its counterpart of negative output topology and double outputs topology were proposed and discussed in [19] and [20]. The concept of multilevel boost converters was investigated in [21] and the topology of Fig. 1(d) was given as central source connection converter. Besides, two switched capacitor cells were proposed in [22] and numerous topologies were derived by applying them to the basic PWM dc–dc converters. Typical topologies are shown as Fig. 1(e) and (f). A modified voltage-lift cell was proposed in [23] and the topology of Fig. 1(g) was produced. Inspired by the above topologies, a new hybrid boosting converter (HBC) with single switch and single inductor is proposed by employing bipolar voltage multiplier (BVM) [32] in this paper. The second-order HBC is shown as Fig. 1(h). Compared with other listed topologies in Fig. 1, the proposed converter decreases the voltage rating of output filter capacitor and exhibits the nature interleaving operation characteristics. Compared with the converter in Fig. 1(d), the proposed converter has smaller

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Fig. 1. Previous high-gain dc–dc converters with single-switch single-inductor and proposed topology. (a) Boost + Dickson multiplier [16], (b) Boost + Cockcroft–Walton multiplier [16], (c) superlift with elementary circuit [18], (d) central source multilevel boost converter [21], (e) Cuk derived [22], (f) Zeta derived [22], (g) modified voltage lifter [23], and (h) proposed second-order HBC.

output ripple and higher components utilization rate with respect to conversion ratio. Some interleaving technologies for ripple reduction and power expansion were reported in the literature [24], [25], but these methods are normally based on circuit branch expansion which requires more components. The proposed topology has achieved smaller ripple with single switch and single inductor while maintaining high voltage gain. Recently, many more structures achieving higher gain were also reported [26]–[31], but they adopted at least two inductors or switches, or some are based on tapped inductor/transformer, which may complicate the circuit design and increase cost. This paper is organized as follows: Section II gives the general topology of basic HBC and discusses the operation principal. The steady-state analysis is given in Section III. Circuit perfor-

mance analysis such as components stress, voltage ripple and circuit comparison are presented in Section IV. Simulation and experimental results are given in Section V and the conclusion is drawn in Section VI.

II. PROPOSED GENERAL HBC TOPOLOGY AND ITS OPERATIONAL PRINCIPAL The proposed HBC is shown in Fig. 2. There are two versions of HBC, odd-order HBC and even-order HBC as shown in Fig. 2(a) and (b). The even-order topology integrates the input source as part of the output voltage, leading to a higher components utilization rate with respect to the same voltage gain. However, they share similar other characteristics and

WU et al.: NEW HBC FOR RENEWABLE ENERGY APPLICATIONS

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Fig. 4. Bipolar voltage multiplier. (a) Positive multiplier. (b) Negative multiplier.

two “complimentary” PWM voltage waveforms at port AO and port OB. Although the two voltage waveforms have their individual high voltage level and low voltage level, the gap between two levels is identical, which is an important characteristic of inductive switching core for interleaving operation. B. BVM

Fig. 2. HBC.

Proposed general HBC topology. (a) Odd-order HBC. (b) Even-order

Fig. 3.

Inductive three-terminal switching core.

circuit analysis method. Therefore, only even-order topology is investigated in this paper. A. Inductive Switching Core In a HBC topology, the inductor, switch and input source serve as an “inductive switching core,” shown as Fig. 3. It can generate

A BVM is composed of a positive multiplier branch and a negative multiplier branch, shown in Fig. 4(a) and (b). Positive multiplier is the same as traditional voltage multiplier while the negative multiplier has the input at the cathode terminal of cascaded diodes, which can generate negative voltage at anode terminal, shown in Fig. 4(b). By defining the high voltage level at input AO as VOA+ , the low voltage level as VOA− , and the duty cycle of high voltage level as D, the operational states of the even-order positive multiplier is derived as Fig. 5 and illustrated as following: 1) State 1 [0, DTs]: When the voltage at port AO is at high level, diodes Dia (i = 2k − 1, 2k − 3 . . . 3, 1) will be conducted consecutively. Each diode becomes reversely biased before the next diode fully conducts. There are K substates resulted as shown in Fig. 5(a). Capacitor Cia (i = 2, 4 . . . 2k) are discharged during this time interval. Assuming the flying capacitors get fully charged at steady state and diodes voltage drop are neglected, the following relationship can be derived: Vc1a = VAO+

(1)

Vcia = Vc(i+1)a (i = 2, 4, 6, ..., 2k − 2).

(2)

2) State 2[dTs, Ts]: When the voltage at port AO steps to low level, diode D2 k a is conducted first, shown as Fig. 5(b)(1). Then the diodes Dia (i = 2, 4, . . . 2k − 2) will be turned on one after another from high number to low. Each diode will be turned on when the previous one becomes blocked. Only diode D2k a is conducted for the whole time interval of [0, dTs], since capacitor C(2k −1)a has to partially provide the

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Fig. 5.


Operation modes of even-order BVM positive branch. (a) State 1[0, DTs]. (b) State 2[DTs,Ts].

load current during the whole time interval. Even though not all the diodes are conducted and blocked at the same time, the flying capacitors still have the following relationship by the end of this time interval: Vc2a = Vc1a − VAO−

(3)

Vcia = Vc(i+1)a (i = 3, 5, 7, . . . , 2k − 1).

(4)

According to charge balance principal, the total amount of electrical charge flowing into capacitors Cia (i = 2, 4, . . . 2k) should equal to that coming out from them in a switching period at steady state, therefore k DT S k TS i2ia dt = i2ia dt. (5) i=1

0

i=1

D TS

Thus, the capacitor group Cia (i = 2, 4 . . . 2k) can be replaced by an equivalent capacitor C2a(eq ) .The diode group Dia (i = 2, 4 . . . 2k) which provides the charging path for

C2a(eq ) is equivalent to a single diode C2a(eq ) . Similarly, the capacitor group Cia (i = 1, 3, . . . 2k − 1) can be replaced by an equivalent capacitor C1a(eq ) and diode group Dia (i = 1, 3, . . . 2k − 1) by D1a(eq ) . The final equivalent even-order positive multiplier branch is given as Fig. 6(a). A similar analysis yields the equivalent negative multiplier branch as shown in Fig. 6(b). According to (1)–(4), the voltage of equivalent capacitors C1a(eq ) ,C2a(eq ) can be expressed as following: Vc2a(eq ) = k(VAO+ − VAO− )

(6)

Vc1a(eq ) = (k − 1)(VAO + − VAO− ) + VAO+ .

(7)

For the negative branch shown in Fig. 6(b), the following results can be obtained based on similar analysis: Vc2b(eq ) = k(VOB+ − VOB− )

(8)

Vc1b(eq ) = (k − 1)(VOB+ − VOB− ) + VOB+

(9)


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According to KCL in Fig. 5(b), voltage ripple of capacitors Cia (i = 2, 4 . . . 2k) can be obtained ⎧ CΔVc2a = (i2k a(off ) + i2k −2a(off ) + . . . i4a(off ) ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ + i2a(off ) )D TS ⎪ ⎨ CΔVc4a = (i2k a(off ) + i2k −2a(off ) + . . . i4a(off ) )D TS ⎪ ⎪ ⎪ ⎪ ··· ⎪ ⎪ ⎪ ⎩ CΔVc2k a = i2k a(off ) D TS

(17) Fig. 6. Equivalent circuit. (a) Even-order positive multiplier. (b) Even-order negative multiplier.

where VOB+ is the high voltage level of input port OB and VOB− is the low voltage level. 3) Equivalent Capacitance Derivation: Assuming capacitors Cia (i = 1, 2, 3, . . . 2k) have the same capacitance C, in order to derive the equivalent capacitance of C2a(eq ) and C1a(eq ) in expression of C, a voltage ripple-based calculation method is proposed in this section. Assuming the peak to peak voltage ripple of the flying capacitors can be expressed as ΔVcia (i = 1, 2, 3 . . . 2k), the ripple of equivalent capacitor C2a(eq ) is ΔV , the following relationship can be approximated: ΔV = ΔVc2a + ΔVc4a + . . . ΔVc2k a .

(10)

In Fig. 5, assuming the average current of iia (i = 1, 2, 3 . . . 2k) during [0, dTs] is (i = 1, 2, 3 . . . 2k) i2ia(on) and the average current of iia (i = 1, 2, 3 . . . 2k) during [dTs, Ts] is iia(off ) (i = 1, 2, 3 . . . 2k), according to charge balance of capacitorsCia (i = 2, 4 . . . 2k), it can be derived that iia(on) DTS

= iia(off ) D TS (i = 2, 4, . . . 2k).

(11)

At the same time, state 1 gives iia(on) = i(i+1)a(on) (i = 2, 4, . . . 2k − 2).

(12)

State 2 gives iia(off ) = i(i+1)a(off ) (i = 1, 3, . . . 2k − 3).

(13)

where D = 1 − D. Based on the equations from (14) to (16), the equation group (17) can be reduced to the following expression: ⎧ CΔVc2a = (k − 1 + D)IO TS ⎪ ⎪ ⎪ ⎪ ⎨ CΔVc4a = (k − 2 + D)IO TS . (18) ··· ⎪ ⎪ ⎪ ⎪ ⎩ CΔVc2k a = (0 + D)IO TS Substituting (10) to (18), the following equation is derived: k(k − 1) CΔV = + kD IO TS . (19) 2 Meanwhile, the following equation can be derived based on discharging stage of equivalent capacitor C2a(eq ) : C2a(eq ) ΔV = IO DTS .

(20)

Based on (19) and (20), the equivalent capacitor C2a(eq ) can be expressed C2a(eq ) =

2D C. k(k − 1 + 2D)

(21)

Similarly, in order to derive the equivalent capacitance of C1a(eq ) , the following equation can be derived: ⎧ CΔVc1a = kIO TS ⎪ ⎪ ⎪ ⎪ ⎨ CΔVc3a = (k − 1)IO TS . (22) ⎪ · · · ⎪ ⎪ ⎪ ⎩ CΔVc2(k −1)a = IO TS At the same time, the following equation exists:

Based on the (11)–(13), the following relationship can be obtained:

C1a(eq ) ΔV = IO TS

(23)

where ΔV = ΔVc1a + ΔVc3a + . . . ΔVc(2k −1)a . Therefore, the expression of C1a(eq) is obtained

i2a(off ) = i4a(off ) = . . . i(2k −4)a(off ) = i(2k −2)a(off ) = i(2k −1)a(off ) .

(14)

Based on charge balance of capacitor C2k a , it can be derived that i2(k −1)a(off ) D TS = IO TS i2k a(off ) D TS = i2k a(on) DTS = Io DTS where Io =

Vo u t R

.

C1a(eq ) =

(24)

Because of the symmetry, the equivalent capacitance C1b(eq ) and C2b(eq ) is given as following:

(15) (16)

2 C. (k + 1)k

C1b(eq ) =

2 C (k + 1)k

(25)

C2b(eq ) =

2D C. k(k − 1 + 2D )

(26)

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Fig. 7.


Three operation states. (a) State 1[0, DTs]. (b) State 2[DTs, (D + D1)T s]. (c) State 3[(D + D1)T s, T s].

the inductive switching core analysis: VAO+ = Vin

(27)

VOB− = 0.

(28)

2) State 2[DTs,(D + D1)Ts]: As illustrated in Fig. 7(b), when S is turned off, the inductor current will free wheel through diodes D2a(eq ) and D1b(eq ) .The inductor is shared by two charging boost loops. In the top loop, capacitor C1a(eq ) is releasing energy to capacitor C2a(eq ) and load at the same time. In the bottom loop, input source charges capacitor C1b(eq ) through the inductor L. During this time interval, voltage generated at AO and OB is expressed as following based on inductor balance principal: Fig. 8.

Equivalent even-order HBC.

The derivation of voltage and equivalent value of the equivalent flying capacitors can facilitate the output voltage calculation and ripple estimation. C. Operation Principle of General Basic HBC Based on the simplification method discussed in previous section, the general even-order HBC in Fig. 2(b) can be simplified to an equivalent HBC circuit, shown as Fig. 8. Careful examination of the topology indicates that the two “boost” like subcircuits are intertwined through the operation of the active switch S. The total output voltage of HBC is the sum of the output voltage of two boost subcircuits plus the input voltage. Three operation states are described as Fig. 7. 1) State 1[0, DTs]: In Fig. 7(a), switch S is turned on and diodes D1a(eq ) , D2b(eq ) conduct while diodes D2a(eq ) and D1b(eq ) are reversely biased. The inductor L is charged by the input source. Meanwhile, capacitor C1a(eq ) is charged by input source and capacitor C2b(eq ) is charged by capacitor C2b(eq ) . At this interval, the following equations can be derived based on

D D1

(29)

Vin (D + D1 ) . D1

(30)

VAO+ = −Vin VOB+ =

3) State 3[(D + D1)Ts, Ts]: Under certain conditions, the circuit will work under DCM operation mode, thus the third state in Fig. 7(c) appeals. At this state, the switch S is kept off. The inductor current has dropped to zero and all the diodes are blocked. The capacitor C2a(eq ) and C2a(eq ) are in series with input source to power the load. During this time interval, voltage generated at port AO is zero while at OB is Vin . III. STEADY-STATE ANALYSIS A. Voltage Gain Derivation in CCM Mode In steady state, the CCM mode operation waveforms are given as Fig. 9(a). The waveforms of VAO and VOB are presented based on operation principal analysis previously. Under CCM condition, D1 = 1 − D = D . Based on (6) and (8), the equivalent voltage of C2a(eq ) and C2b(eq ) is obtained as Vc2b(eq ) = k

Vin D

(31)


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In Fig. 9(b), the inductor current can be expressed as following during state 2: IL = ID 2a(eq ) + ID 1b(eq ) .

(35)

According to charge balance principal of the circuit ID 2a(eq ) = ID 1b(eq ) = IO

(36)

where ID 2a(eq ) and ID 1b(eq ) are the average current in the whole switching period. As current waveforms of ID 2a(eq ) and ID 1b(eq ) should both have triangle shape, they will share same peak current value, which is half of the inductor peak current. Therefore 1 Vin DTS . (37) 2 L in a switching period is IO ,

ID 2a(eq )p−p = ID 1b(eq )p−p =

The average current of ID 2a(eq ) thus 1 Vin 1 1 D1 TS DTS = IO . 2 2 L TS

(38)

This can be simplified to D1 =

4IO L . Vin TS D

(39)

Substituting (37) to (32), the following equation can be derived: Vin2 D2 TS Vout = Vin + 2k Vin + . (40) 4IO L Solving the (38) gives the voltage gain in DCM mode

2 (2k + 1)2 + k 2D LT S R 2k + 1 + Vout . = Vin 2

(41)

C. BRM Mode Analysis In order to derive boundary condition for CCM and DCM mode, the average power balance is used Vin (IL + ID 1a(eq ) ) = Vout IO Fig. 9.

out . where ID 1a(eq ) =IO = V R Thus, the average current of IL under CCM condition is

Key waveforms. (a) CCM. (b) DCM.

Vc2a(eq )

Vin = k . D

(32)

(33)

B. Voltage Gain Derivation in DCM Mode Under DCM operation mode, the waveforms of voltage at input port AO, OB are shown in Fig. 9(b). Based on (6) and (8), the voltage gain can be expressed as Vout

D + D1 = Vin + 2kVin . D1

2k Vout . D R The current ripple of inductor is IL =

Therefore, the voltage ratio of a general 2kth-order HBC shown in Fig. 2(b) is derived as following: Vout 1 = 1 + 2k . Vin D

(42)

(34)

Vin DTS . 2L Therefore, the CCM condition is ΔiL =

Vin 2k Vout > DTS . D R 2L The criteria can be rearranged as 2L DD2 = Kcrit (D). > RTS 2k(D + 2k)

(43)

(44)

(45)

(46)

The curves of Kcrit (D) with k = 1, 2, 3 are shown in Fig. 10. It can be seen that when the voltage multiplier stage increases, it is easier to achieve CCM when other parameters are fixed.

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TABLE I COMPONENTS STRESS Vm a x

Ia v e

Vin D

2k I a D

Vin D

I0

D i b (i = 1, 3 . . . 2k − 1)

Vin D

I0

Cia

Vin

0

C i a (i = 3, 5 . . . 2k − 1)

Vin D

0

C i b (i = 1, 3 . . . 2k − 1)

Vin D

0

C i a (i = 2, 4 . . . 2k )

Vin D

0

C i b (i = 2, 4 . . . 2k )

Vin D

0

S

Ir m s 2k

IO √ D D

D i a (i = 1, 3 . . . 2k − 1) D i b (i = 2, 4 . . . 2k )

IO √ D

D i a (i = 2, 4 . . . 2k )

Fig. 10.

Fig. 11.

K c rit (D) with variation of k.

Current waveforms of diodes and switch for stress calculation.

IV. CONVERTER PERFORMANCE ANALYSIS A. Component Stress Analysis Detail analysis of components stress for the converter provides solid reference for components selection and optimization. The components stress under CCM mode is estimated in this section. 1) Diodes and Switch: According to the charge balance law of flying capacitors, all the diodes Dia (i = 1, 2, 3 . . . 2k) and Dib (i = 1, 2, 3 . . . 2k) have the same average current IO during one switching period. The average current during conduction state is used to calculate Irm s here. The current waveforms of diodes and switch are shown in Fig. 11. Their current stress and voltage stress are listed in Table I. 2) Capacitors: According to the analysis of BVM in Section II, the flying capacitors that are closer to inductive switching core have larger charging or discharging current, which exhibit larger voltage ripple. Their average charging and

IO √ D IO k k−

i−1 2

1 DD IO

1 DD

1 i−1 IO 2 DD D i IO + IO k− 2 D D D i IO k− + IO 2 D D

k−

Fig. 12. Voltage ripple cancellation with different duty cycle. (a) D = 0.8. (b) D = 0.5.

TABLE II COMPARISON OF NORMALIZED CAPACITOR VOLTAGE STRESS FOR CONVERTER Fig. 1

C1

C2

C3

C4

C5

Total

(a)

1/3

1/3

1/3

2/3

1

8/3

(b)

1/3 1 −D 3 −D

1/3 2 −D 3 −D

1/3 1 −D 3 −D

1/3

1/3

1

0

5/3 8 − 4D 3 −D

(d)

1/3

1/3

1/3

1/3

1/3

(e)

1/2

1/2

1

0

0

2

(f)

D 1+D

D 1+D

1

0

0

1 + 3D 1+D

(g)

D/2

1/2

1

0

0

3+D 2

(h)

1 −D 3 −D

1 3 −D

1 3 −D

1 3 −D

0

4 −D 3 −D

(c)

Note: C1–C4 are representing C1 a , C1 b , C2 a , C2 b for Fig. 1(h).

5/3


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TABLE III COMPARISON OF PROPOSED SECOND-ORDER HBC AND OTHER CONVERTERS

Fig. 1

Converters

(a)

Boost + Dickson multiplier [16]

(b)

Boost + Cockcroft Walton multiplier [16]

(c)

Super-lift converter [18]

(d)

Multilevel boost converter [21]

(e)

Cuk-derived converter [22]

(f)

Zeta-derived converter [22]

(g)

Modified voltage lift converter [23]

(h)

Proposed HBC

Voltage gain 3 1 −D 3 1 −D 3 −D 1 −D 3 1 −D 2 − 1 −D 1+D 1 −D 2 1 −D 3 −D 1 −D

Diodes

Capacitors

Ms stress norm = V s s t r e s s /V o u t

M rip p le

norm Vo u t Ts

= ΔVo u t /

RL C

5

5

1/3

D

5

5

1/3

3 + 3D

4

4

1/(3 – D)

D

5

5

1/3

3D

3

3

1/2

1 −D

3

3

1/(1+D)

1 −D

3

3

1/2

D

4

4

1/(3 – D)

|2D − 1|

B. Voltage Ripple Analysis The output voltage ripple is determined by the ripple of equivalent capacitor C2a(eq ) and C2b(eq ) , assuming the input source has a constant voltage. As the equivalent capacitance of C2a(eq ) and C2b(eq ) are given as (21) and (26), the voltage ripple of C2a(eq ) and C2b(eq ) can be presented as following: IO TS k(k − 1 + 2D) 2C IO TS k(k − 1 + 2D ). ΔVc2b(eq ) = 2C The final output ripple can be presented as following: ΔVc2a(eq ) =

Fig. 13.

Comparison of voltage gain of converters (a)–(h).

(47) (48)

IO TS k |2D − 1| .(49) C According to the (47), when the duty cycle D is 0.5, the theoretical output voltage ripple is zero. The ripple examples of D = 0.8 and 0.5 are compared in Fig. 12(a) and (b). The interleaving operation has led to ripple cancelation of the capacitors C2a(eq ) and C2b(eq ) . ΔVout = |ΔVc2a(eq ) − ΔVc2b(eq ) | =

C. Comparison of Proposed HBC With Previous Converters

Fig. 14.

Comparison of total capacitor normalized voltage stress in Table II.

discharging current can be used to estimate the RMS current, which is useful to evaluate power loss of each capacitor. The expressions of RMS current for each capacitor in a 2kth-order HBC are also given in Table I.

In order to distinguish the proposed HBC converter, a comparison is carried out between the second-order HBC converter and several previous published converters with single inductor and single switch shown in Fig. 1(a)–(h). All capacitors are assumed to have the same value C for easier comparison. The voltage gain, component count, as well as normalized switch stress and normalized output ripple are all listed for each topology in Table III. The absolute voltage gain curves for all topologies presented in Fig. 1 are sketched in Fig. 13. The proposed HBC has good gain boosting capability. However, it is difficult to judge the performance of each configuration merely based on the level of its gain curve, especially with consideration of different components count for different topologies. Most of the topologies can extend their gain by adding more stags with a larger

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TABLE IV PARAMETER SELECTED FOR PROTOTYPE BUILDING Name MOSEFT Inductor Diode

Capacitor

Switching frequency Load

Fig. 15.

Denomination

Value

S L D1 a D2 a D1 b D2 b C1 a C2 a C1 b C2 b fs R

250 V/40 A, 29 m Ω(IRFP4330) 500 μH 200 V/20 A,VF = 0.78 V(STH2002C)

250 V/100 μF, electrolytic capacitor

40 kHZ 722 Ω

Comparison of normalized output ripple of converters (a)–(h).

number of capacitors and diodes. Therefore, more details should be taken into consideration to evaluate topologies, such as total normalized capacitor voltage rating and normalized output voltage ripple. For the high gain dc–dc converters with single switch and inductor, a critical aspect to realize high power density and low cost is to decrease the physical size of capacitors. Diodes usually have comparably much smaller volume, whose effect to the power density is neglected in this comparison. The voltage rating and capacitance value are the primary factors that affect the size of each capacitor. In order to compare the density of each topology with same gain, the normalized voltage stresses of capacitors for each topology are calculated in Table II. The normalized voltage stress for a capacitor is defined by the actual voltage stress of the capacitor divided by the output voltage Vout . The total normalized capacitor voltage stress is the sum of all normalized capacitor voltage stress, which takes into account the capacitor number and voltage rating requirement. This parameter can be used to evaluate the size of high gain dc–dc converters with single switch and inductor. The total normalized capacitor voltage stresses of all topologies are sketched in Fig. 14 based on results in Table II, with variation of duty cycle. Compared with other listed topologies, the proposed second order HBC has lowest total capacitor voltage stress in a wide range of duty cycle. This result shows the superiority of proposed structure for high power density design. In addition to the normalized capacitor voltage stress comparison, the normalized output ripple comparison is given in Fig. 15 according to Table III. Among all the converters considered, the proposed HBC structure (h) has the lowest ripple in the duty cycle range of [1/3, 2/3]. When duty cycle ranges are higher than 2/3, only converter (e) and (f) show smaller ripple theoretically. However, under this condition, converter (e) and (f) exhibits much larger normalized total capacitor voltage stress and weaker gain boosting capability, as shown in Figs. 13 and 14. It should be pointed out that although the proposed HBC structure has the advantages in high power density and low cost design, it also has the intrinsic issue of uncommon ground

between source and load, which may limit its applications in areas where common ground are not required between input and output. Besides, due to direct connection between the input and output, the audio susceptibility may be an issue, which may require an input filter and fast control loop.

V. EXPERIMENTAL RESULTS In order to verify the feasibility of proposed converter and its performance, simulation and experimental results of a secondorder HBC converter in Fig. 1(h) are provided in this section. A prototype of 200 W 35 to 380 V second-order HBC was built in the lab. The specifications of the prototype are listed in Table IV. The experimental waveforms of drain-source voltage input current, input voltage and output voltage are given in Fig. 17(a). Unnoticeable overshoot at voltage Vds is derived because of the buffering function of capacitor C1a and C1b . The input current is pulsating without terminating to zero and no rush current is observed due to the operation frequency is chosen properly. The output voltage is boosted to 380 V and kept stable without high voltage rating filter capacitor. In Fig. 17(b), the voltage stress of four diodes is presented, which is relatively low and no voltage overshoot is observed. In Fig. 18, the experimental output voltage ripple is presented in contrast with that of capacitor C2a and C2b under different duty cycle conditions, with the output voltage maintained at 200 V to keep constant load current. According to the discussion in section IV-B, full ripple cancellation can be achieved under D = 0.5 condition. It is observed in Fig. 18(a) that output ripple is nearly zero when duty cycle is 0.5. When duty cycle is increased to 0.8 shown as Fig. 18(b), larger output ripple ΔVout is observed. The interleaved voltage ripple of C2a and C2b contributes the small output ripple for proposed HBC topology. Under the light load condition, the HBC may enter DCM operational mode easily according to discussions in Sections III-B and C. The experimental results of BRM and DCM conditions are given as Fig. 19(a) and (b). Waveforms of Vout , Vin , IL and Vds are presented. The efficiency curve of the prototype is tested


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Fig. 16.

Experimental waveforms. (a) V d s , Iin , V o u t , V in . (b) Diodes voltage: V d 2 a , V d 1 a , V d 1 b , V d 2 b .

Fig. 17.

Experimental waveforms of voltage ripples: Vc 2 a , Vc 2 b ,Vo u t and driving signal Vg s under (a) D = 0.5, (b) D = 0.8.

Fig. 19.

Efficiency curve with load variation (V in = 35 V, V o u t = 380 V).

VI. CONCLUSION

Fig. 18. Experimental waveforms of V o u t , V in , IL and V d s under (a) BRM condition and (b) DCM condition.

and shown in Fig. 19, with the load variation from 40 to 250 W. A peak efficiency of 95.44% is achieved.

A new HBC composed of an inductive switching core and BVM is proposed in this paper. The proposed converter has the collective advantages of the gain boosting technique from voltage multiplier and voltage regulation capability from boost converter, featuring in nature interleaved operation, wide regulation range, low component stresses, small output ripple, flexible gain extension, and high efficiency. Compared with other high gain boosting technologies such as tapped inductor, multiinductor/switch method or transformer-based method, the proposed topology has reduced the complexity which is suitable for mass production. Compared with other single switch and single inductor dc–dc converters, it has a better component

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utilization rate, smaller output ripple and lower component stress. This paper provides operation principle, design consideration, and overall comparison with many other similar topologies. A 200-W, 35 to 380 V second-order HBC prototype was constructed which achieved a peak efficiency of 95.44%. This converter is suitable for many renewable energy applications such as the front-end of PV system.

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[21] J. C. Rosas-Caro, J. M. Ramirez, F. Z. Peng, and A. Valderrabano, “A DC–DC multilevel boost converter,” IET Power Electron., vol. 3, no. 1, pp. 129–137, Jan. 2010. [22] E. Ismail and M. Al-Saffar, “A family of single-switch PWM converters with high step-up conversion ratio,” IEEE Trans. Circuits Syst. I, vol. 55, no. 4, pp. 1159–1171, May 2008. [23] S. Zhang, J. Xu, and P. Yang, “A single-switch high gain quadratic boost converter based on voltage-lift-technique,” in Proc. 10th Int. Power Energy Conf., 2012, pp. 71–75. [24] Y. J. A. Alcazar, D. de Souza Oliveira, F. L. Tofoli, and R. P. TorricoBascope, “DC–DC nonisolated boost converter based on the three-state switching cell and voltage multiplier cells,” IEEE Trans. Ind. Electron., vol. 60, no. 10, pp. 4438–4449, Oct. 2013. [25] W. L. W. Li and X. H. X. He, “An interleaved winding-coupled boost converter with passive lossless clamp circuits,” IEEE Trans. Power Electron., vol. 22, no. 4, pp. 1499–1507, Jul. 2007. [26] E. H. Ismail, M. A. Al-Saffar, A. J. Sabzali, and A. A. Fardoun, “High voltage gain single-switch non-isolated DC-DC converters for renewable energy applications,” in Proc. IEEE Int. Conf. Sustain. Energy Technol., Dec. 2010, pp. 1–6. [27] A. A. Fardoun and E. H. Ismail, “Ultra step-up DC–DC converter with reduced switch stress,” IEEE Trans. Ind. Appl., vol. 46, no. 5, pp. 2025– 2034, Sep. 2010. [28] Y. Zhao, X. Xiang, C. Li, Y. Gu, W. Li, and X. He, “Single-phase high step-up converter with improved multiplier cell suitable for half-bridgebased PV inverter system,” IEEE Trans. Power Electron., vol. 29, no. 6, pp. 2807–2816, Jun. 2014. [29] J.-K. Kim and G.-W. Moon, “Derivation, analysis, and comparison of nonisolated single-switch high step-up converters with low voltage stress,” IEEE Trans. Power Electron., vol. 30, no. 3, pp. 1336–1344, Mar. 2015. [30] Y. Zhang, J.-T. Sun, and Y.-F. Wang, “Hybrid boost three-level DC–DC converter with high voltage gain for photovoltaic generation systems,” IEEE Trans. Power Electron., vol. 28, no. 8, pp. 3659–3664, Aug. 2013. [31] L. H. S. C. Barreto, P. P. Praca, D. S. Oliveira, and R. N. A. L. Silva, “High-voltage gain boost converter based on three-state commutation cell for battery charging using pv panels in a single conversion stage,” IEEE Trans. Power Electron., vol. 29, no. 1, pp. 150–158, Jan. 2014. [32] B. Wu, S. Keyue, and S. Sigmond, “A new 3X interleaved bidirectional switched capacitor converter,” in Proc. IEEE Appl. Power Electron. Conf. Expo., 2014, pp. 1433–1439.

Bin Wu (S’14) was born in Zhejiang, China, in 1985. He received the B.S. degree in electrical engineering from Zhejiang University, Hangzhou, China, in 2008, and the M.S. degree in power electronics from Xi’an Jiaotong University, Xi’an, China, in 2011. He is currently working toward the Ph.D. degree in power electronics at the University of California, Irvine, CA, USA. His interests include switched capacitor converter, modeling, high gain dc–dc converter, electrical vehicle and renewable energy integration.

Shouxiang Li (S’14) received the B.S. degree in electrical engineering and automation from the Beijing Institute of Technology, Beijing, China, in 2011, and the M.S. degree in electrical engineering from the University of California, Irvine, CA, USA, in 2013. He is currently working toward the Ph.D. degree at the University of California, conducting his studies both in the Calit2 and the UCI Power Electronics Laboratory. From 2012 to 2013, he was an Intern in the PMU Group of Broadcom Corporation, Irvine. From 2013 to 2014, he was a Research Assistant at the UCI Power Electronics Laboratory. His research interests include switched capacitor converters, high-gain dc/dc converters.


Yao Liu received the B.S. degree in electrical engineering from North China Electric Power University, Beijing, China, in 2013, and the M.S. degree in electrical engineering from the University of California, Irvine, CA, USA, in 2015. He is currently working at the Mixed Signal Layout Design Group, Broadcom Corporation, Irvine. He has been a Research Assistant at the UCI Power Electronics Laboratory. His research interests include high gain dc–dc converters, renewable energy, and mixed signal design.

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Keyue Ma Smedley (S’87–M’90–SM’97–F’08) received the B.S. and M.S. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 1982 and 1985, respectively, and the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, CA, USA, in 1987 and 1991, respectively. She is currently a Professor at the Department of Electrical Engineering and Computer Science, University of California, Irvine (UCI), CA, USA, the Director of the UCI Power Electronics Laboratory, and a Cofounder of One-Cycle Control, Inc. Her research interests include highefficiency dc–dc converters, high-fidelity class-D power amplifiers, single-phase and three-phase PFC rectifiers, active power filters, inverters, V/VAR control, energy storage system, and utility-scale fault current limiters. She is an inventor of one-cycle control and the hexagram power converter. Her work has resulted in more than 160 technical publications, more than 10 U.S./international patents, two start-up companies, and numerous commercial applications. Dr. Smedley is a recipient of the UCI Innovation Award 2005. Her work with One-Cycle Control, Inc., has won the Department of the Army Achievement Award in the Pentagon in 2010.