A New Package of High-Voltage Cascode Gallium Nitride Device for High-Frequency Applications Fred C. Lee, Wenli Zhang, Xiucheng Huang, Zhengyang Liu, Weijing Du, and Qiang Li Center for Power Electronics Systems (CPES) Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 24060, USA Email: [email protected]
; [email protected]
reaching the full potential of this WBG semiconductor. A highperformance package with minimized impacts on the electrical and thermal properties of the GaN bare-die device has to be invented in order to compete with Si technology.
Abstract—Lateral gallium nitride (GaN)-based high-electronmobility transistor (HEMT) power devices have high current density, high switching speed, and low on-resistance in comparison to the established silicon (Si)-based semiconductor devices. Using efficient GaN HEMT devices switched at high frequency in power electronic systems could lead to an increase in power density as well as a reduction in the weight, size, and cost of the system. However, conventional packaging configurations often compromise the benefits provided by highperformance GaN HEMT devices. This undesirable packageinduced performance degradation is prominent in the cascode GaN device, where the combination of a high-voltage depletionmode GaN device and low-voltage enhancement-mode Si device is needed. In this work, a new package is introduced for highvoltage cascode GaN devices and is successfully demonstrated to make the device more suitable for megahertz (MHz) operation. This packaging prototype for cascode GaN devices is fabricated in a power quad flat no-lead (PQFN) format with the new features of a stack-die structure, embedded external capacitor, and flip-chip configuration. The parasitic ringing in hardswitching turn-off and switching losses in soft-switching transitions are both effectively reduced for this newly packaged device compared with a traditional package using the same GaN and Si devices. Improved thermal dissipation capability is also realized using this new package for better reliability.
The conventional lateral AlGaN/GaN heterostructure of the GaN HEMT results in an intrinsically normally-on device operated in depletion-mode, which is inconvenient for switching applications because a specific gate driver must be carefully designed with overdrive protection to safely switch the device . Different approaches have been demonstrated to suppress the two-dimensional electron gas under the specific gate structures of the developed enhancement-mode (normallyoff) lateral GaN HEMTs , –. The packaging of enhancement-mode GaN HEMT devices only includes the use of one chip, and it can be realized at the wafer level. The land grid array (LGA) packaging format has been adopted for the production of Efficient Power Conversion (EPC)’s commercial eGaN® devices. This chip-scale package (CSP) provides minimized package-related resistance and parasitic inductance as well as a minimal mounting footprint on the printed circuit board (PCB), which enables the high-speed switching of the eGaN® device with effectively reduced dynamic losses and ringing . GaN Systems has also developed a near chipscale package GaNPXTM for the high-voltage enhancementmode GaN transistor for high-frequency, high-efficiency power conversion applications. The GaN transistor is surrounded by high-temperature fiberglass materials. The terminals on the embedded GaN device are electrically connected to the exposed mounting pads through copper (Cu) plated vias providing extremely low inductance . Both packages introduced above are in a low-profile, wire-bondless structure. The fabrication of a high-performance enhancement-mode GaN HEMT is challenging due to their use of additional lowenergy ion implantation, precise plasma etching, or other advanced processing techniques. The production yield of consistent and reliable devices is affected accordingly. Furthermore, the performance of enhancement-mode GaN HEMTs is compromised compared with that of the equivalent depletion-mode GaN HEMT .
Keywords—cascode gallium nitride high-electron-mobility transistor (GaN HEMT); high frequency; stack-die packaging.
The emerging gallium nitride (GaN)-based wide bandgap (WBG) semiconductor devices have been developed for power conversion applications. The dominant type of commercial high-voltage (≥ 600 V rated) GaN power devices is the highelectron-mobility transistor (HEMT) fabricated in a lateral aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterojunction structure –. High-power-density GaN HEMT devices, which are more efficient than the incumbent silicon (Si) based devices, can be switched faster with lower switching losses. Moreover, such lateral GaN devices can be built on low-cost, large-diameter Si substrates. This promising GaN-on-Si technology has progressed rapidly and is considered to be able to replace the state-of-the-art Si technology , . However, the packaging of GaN HEMT devices has become one of the significant limiting factors to
Another approach to realize the normally-off functionality for the GaN HEMT in a lateral AlGaN/GaN heterostructure is to co-package one additional low-voltage, normally-off switch; e.g., a power Si metal-oxide-semiconductor field-effect
This work was supported by the Power Management Consortium (PMC) in Center for Power Electronics Systems (CPS), Virginia Tech.
978-1-4799-9883-8/15/$31.00 ©2015 IEEE
transistor (MOSFET), connected in series to the high-voltage, normally-on GaN HEMT –. This cascode arrangement not only enables the normally-off operation, observed from the terminal behavior of the packaged device, but also avoids the performance degradation of the GaN transistor. The other significant benefit of using the cascode GaN devices over other GaN devices operated in enhancement-mode is that the existing gate drivers with proven reliability for the Si-based devices can be easily applied because the drive characteristics are defined by the low-voltage Si MOSFET . The packaging of this normally-off device includes two chips, which may cause additional resistance, inductance, size, and thermal issues for the packaged cascode GaN device. Advanced packaging structures for GaN HEMT devices in the cascode configuration have been investigated for improving thermal reliability and electrical performance. Delphi and International Rectifier (IR) have demonstrated a wire-bondless, dual-side cooled package including a 600 V depletion-mode GaN device cascoded with a low-voltage, normally-off Si device. Both sides of the GaN and Si chips are sintered to the direct bonded copper (DBC) substrate for making interconnection and enabling double-side cooling . Another high-voltage GaN device in the cascode-configured package has been introduced by GaN Systems. The proprietary GaN HEMT with an “island” layout is either directly mounted on a Si-based CMOS driver device  or acts as a chip carrier for the Si MOSFET device . Low-resistance and -inductance interconnections between the GaN and Si devices are achieved by using Cu posts instead of bonding wires or ribbons, which is beneficial for increasing switching speed. Because the relatively high cost of manufacturing these new packages must be taken into consideration when compared to the standard packaging processes used in Si technology, the traditional packages, i.e., TO-220 and power quad flat no-lead (PQFN) packages, are still the mainstream packaging formats widely adopted for the high-voltage cascode GaN devices on the market –. Bonding wires are commonly used in these packages to form electrical interconnections among GaN HEMT, Si MOSFET and terminal leads.
PERFORMANCE EVALUATION OF CASCODE GAN DEVICE
The switching and thermal characteristics of a commercial high-voltage cascode GaN device from Transphorm  have been studied with an emphasis on the impact of the package on the performance, especially for MHz applications. Subsequently the packaging improvement approaches are proposed based on the performance evaluation and detailed analysis of this device. A. Influence of Package-Induced Parasitic Inductances A simulation model was developed and verified to be able to predict the high-frequency switching performance of the cascode GaN device and analyze the package-induced parasitic inductance in . The critical common-source inductance (CSI), which shows significant impacts on the switching transients, can be identified using this model. Figure 1(a) illustrates the internal wire-bonding diagram with all packageinduced parasitic inductors labeled for the commercial PQFNpackaged cascode GaN device. Two critical CSIs (Lint1 and Lint3) were identified as shown in Fig. 1(b).
Fig. 1. (a) Internal wire-bonding structure and (b) equivalent circuit diagram showing the package-induced parasitic inductors for a commercial highvoltage cascode GaN device in PQFN package.
This cascode GaN device is used as the top switch in a buck converter to evaluate its switching performance. Figure 2(a) presents the equivalent circuit of the designed buck converter. The gate of the GaN HEMT is vulnerable in high di/dt turn-off conditions based on the simulation result exhibited in Fig. 2(b). VGS_GaN is the superposition of VSD_Si with all voltages generated on the related parasitic inductors; i.e., Lint1, Lint2, and Lint3 in this case. It is demonstrated that although the VSD_Si is clamped at -30 V due to the avalanche mechanism of the Si MOSFET, the VGS_GaN is still exposed to the detrimental high-voltage spike induced by internal parasitic inductances. Such internal parasitic ringing is even worse when the switching frequency increases to the MHz-level, which can directly cause the GaN HEMT to fail.
In this study, the switching characteristics and thermal performance of a commercial cascode GaN device in a traditional PQFN package are firstly considered for megahertz (MHz) operation. Then, a new package of this normally-off GaN device configured in the same cascode structure is created. A 600 V lateral GaN HEMT is co-packaged with a 30 V vertical Si MOSFET in the stack-die structure with the optimized arrangement of bonding wires. A balancing capacitor is also integrated into the device package in order to compensate the junction capacitance mismatch between the GaN and Si devices. The flip-chip configuration is realized in this advanced package for easy and effective thermal management as well as better reliability. The whole packaging of the high-voltage cascode GaN device is still contained in a PQFN format with the new features listed above. Finally, this cascode GaN device in the newly developed package has demonstrated better switching and thermal performance than the equivalent commercial product packaged using the same GaN HEMT and Si MOSFET chips.
Fig. 2. (a) Equivalent circuit of buck converter using cascode GaN device as top switch (TS) and diode as bottom switch (BS); (b) simulation waveforms in 400 V/12 A turn-off condition. For the cascode GaN device investigated in this study, the avalanche voltage of the Si MOSFET is 30 V while the breakdown voltage of the GaN HEMT is 35V.
The package of the cascode GaN device has to be improved to eliminate the pre-defined critical CSIs for better switching performance and reliability. As shown in Fig. 3(a), a stack-die structure with new wire-bonding configuration has been proposed in order to minimize the negative impacts of parasitic inductances on the switching performance of the device. In this structure, Lint1 is eliminated by soldering the drain of the Si device directly on top of the source of the GaN device without using bonding wires. Lint3 is also excluded from the driving loop of the GaN HEMT by redirecting a bonding wire from the gate of the GaN HEMT to the source of the Si MOSFET. With this optimized internal interconnection configuration, no parasitic inductors are shared by more than one loop as illustrated in Fig. 3(b), which means all CSIs are eliminated. Thus the cascode GaN device packaged in this new format is expected to perform better at high-frequency switching.
Fig. 4. Experimental waveforms of a cascode GaN device without compensating capacitor (a) steady-state: the ZVS turn-on behavior has been “seen” from the main terminals; (b) detailed turn-off transition: VDS_Si reaches avalanche voltage at t2, while Vsw only rises to around 170 V. After t2, the drain-source junction capacitance of the GaN device (CDS_GaN) is continuously charged through the avalanched path of the Si device till Vsw reaches steadystate voltage at t3; (c) detailed turn-on transition: VDS_Si decreases to the threshold voltage of the GaN device at t2 while Vsw only drops to 280 V. The remaining energy stored in CDS_GaN is dissipated through the channel of the GaN device till Vsw reaches 0 at t3 .
Fig. 3. (a) Internal interconnection configuration; (b) equivalent circuit diagram showing the package-induced parasitic inductors for the device packaged in the new stack-die structure.
A simple but effective way to balance the mismatched junction capacitance between the Si MOSFET and GaN HEMT is to add an external capacitor in parallel with the drain-source terminals of the Si MOSFET. A properly selected capacitance should allow the GaN HEMT to achieve its steady-state voltage before the Si MOSFET reaches its avalanche voltage. Paralleling the capacitor between the drain-source terminals of the Si MOSFET will not increase its driving loss, and the turnoff loss is still very small due to the merits of the cascode structure . The circuit diagram of a cascode GaN device with the extra compensating capacitor is illustrated in Fig. 5(a). Although the junction capacitance mismatch is induced by the devices and not the package, the compensation can be made by integrating the capacitor within the new package, as shown in Fig. 5(b). Avoiding avalanche for the Si transistor and achieving true ZVS for the GaN transistor could be realized.
B. Effect of Junction Capacitance Mismatch Between GaN and Si Devices Soft-switching has been demonstrated to be critical for high-voltage cascode GaN devices in high-frequency, highefficiency applications. Achieving ZVS turn-on of the GaN HEMT can dramatically reduce the turn-on loss of the device with very small increase in turn-off loss . Furthermore, the junction capacitors of the Si MOSFET and GaN HEMT have to be equally matched to achieve high efficiency, especially under soft-switching conditions . The voltage distribution between the high-voltage GaN device and low-voltage Si device during the turn-off transition is mainly determined by the junction capacitor charges. In some circumstances, the Si MOSFET may achieve avalanche before the complete turn-off of the GaN HEMT. The GaN HEMT cannot realize true ZVS if the Si MOSFET reaches avalanche, even when the external waveform of the cascode device behaves like ZVS, as shown in Fig. 4. A detailed analysis of the principles of voltage distribution at turn-off and realization of true ZVS at turn-on for the cascode GaN HEMT device is introduced in . The avalanche of the Si MOSFET and the internal non-ZVS of the GaN HEMT cause additional power losses in every switching cycle. Both losses are proportional to the switching frequency and must be eliminated for MHz-frequency applications. Additionally, repetitive avalanche currents in the Si MOSFET could lead to a reduction of the lifetime and reliability of the cascode GaN device .
Fig. 5. (a) Circuit diagram of the cascode GaN device with a compensating capacitor (Cx) and other device junction capacitors; (b) illustration of the internal layout of the new package for the cascode GaN device with an integrated external capacitor. The capacitor is in the shaded area.
limitation of the PCB on heat dissipation is to adopt the flipchip packaging concept. The heat sink can be directly attached to the bottom Cu layer of the DBC substrate, and the device terminals (gate, source, and drain) are designed to be on the top side of the DBC for subsequent attachment to the circuit board. A three-dimensional (3D) model showing the flip-chip design of a cascode GaN device in stack-die structure (Figure 7) was built to analyze the thermal performance.
C. Evaluation of Thermal Performance Thermal management of the package is a critical factor to improving device performance and reliability for highfrequency, high-efficiency power conversion. GaN material has poor thermal conductivity, which makes heat removal difficult. The junction temperature rise and non-uniform power distribution in the GaN HEMT will lead to the formation of hotspots near the device channel, degradation of performance, and eventually device failure , . Moreover, the normally-on GaN HEMT used in this cascode device has been developed based on the GaN-on-Si substrate. The attempt of using highly thermally conductive but more expensive silicon carbide (SiC) substrate is excluded. Other thermal management solutions must be used to improve heat dissipation from the GaN HEMT at the package-level. A simulation model has been built using the finite element analysis (FEA) method to evaluate the thermal performance of the cascode GaN device packaged in a stack-die structure . Figure 6 represents the simulation results of temperature distribution of the packaged device in a stack-die structure with the PCB and heat sink attached to the bottom side of DBC substrate. Two primary heating sources, the GaN HEMT and the Si MOSFET, are overlapped on purpose. Most heat generated by the semiconductor devices has to transfer vertically from the top active chips to the DBC substrate, mounted PCB, and the bottom heat sink, successively. As observed in Fig. 6(b), it is apparent that a significant amount of heat accumulates at the ceramic layer of the DBC substrate and the PCB layer even though a series of thermal vias is designed in the circuit board to conduct heat from the device to the heat sink. Preliminary experimental results have demonstrated that the commercial device in the traditional PQFN exhibits better thermal performance than the cascode GaN device packaged in this format . A more efficient thermal management method must be developed for improving the reliability of the device in a stack-die structure.
Fig. 7. 3-D model of flip-chip design for the cascode GaN device in stackdie structure. The heat sink is attached to the bottom of the DBC substrate using thermal grease. Cu pillars are soldered on the top side of the DBC.
FABRICATION OF CASCODE GAN DEVICE IN NEW PACKAGE
The cascode GaN device designed in a stack-die structure featuring an embedded capacitor and flip-chip configuration is packaged in a low profile format similar to the conventional PQFN package. The device fabrication procedure includes three major steps: substrate preparation, device assembly, and encapsulation. A. Substrate Preparation Aluminum nitride direct-bonded-copper substrate (AlN– DBC; AlN 380 μm, Cu 170 μm), which has high strength and good thermal conductivity, was selected as the chip carrier for this power semiconductor assembly. First, 25-μm thick adhesive Kapton® tape as etching mask was applied entirely on both the top and bottom Cu surfaces of the DBC substrate. After laser patterning, the attached tapes were selectively subtracted according to the circuit layout. The exposed Cu areas have been then etched off by ferric chloride solution to form the circuitry on the DBC substrate. Next, oxygen plasma was used to remove impurities and contaminants from the Cu surfaces. Finally, the plasma-cleaned top Cu pads were electroplated with nickel (Ni) and gold (Au) successively, which helps to avoid the surface oxidation and facilitates the dieattachment and wire-bonding processes. The thickness of the Au-finished surface is in the range of 0.8 to 1.2 µm. The process flow of substrate preparation is displayed in Fig. 8.
Fig. 6. Temperature distribution of the cascode GaN device packaged in a stack-die structure and surface-mounted on PCB: (a) top view and (b) crosssectional view. Heat sink is attached to the other side of the PCB.
It is a common practice to maintain a continuous low thermal resistance path from the packaged semiconductor to the environment. A straightforward method to improve the thermal performance of the stack-die packaged cascode GaN device is to use aluminum nitride (AlN)-based DBC instead of low-cost alumina (Al2O3)-based DBC as substrate. The thermal conductivity of AlN is seven to eight times higher than that of Al2O3. However, heat still accumulates in the low thermally conductive PCB part. One approach which can minimize the
Fig. 8. Preparation procedure of DBC substrate.
B. Device Assembly A 600 V GaN HEMT and 30 V Si MOSFET bare dies were selected for the device assembly in the stack-die structure. They are the same devices used in the commercial cascode GaN device in the traditional PQFN package . The GaN die and a Cu spacer in the same thickness as the GaN chip were firstly attached on the substrate. The Cu spacer was used in order to level the position of Si device mounted directly on the GaN device. Then, a solder mask protecting the channel area and gate terminals was applied on the top surface of the GaN die with only the source and drain pads uncovered. Next, the Si die was soldered on top of the GaN die. The solder joint connects the drain terminal of the Si MOSFET to the source terminal of the GaN HEMT without wire-bonding. Because the top terminal pads of the GaN HEMT are coated with Au and the bottom drain terminal of the Si MOSFET is plated with silver, no further surface treatment is required for soldering the interfacing metals on these two devices. A piece of Au-plated Cu foil (200 μm thick) with preformed bends was also soldered simultaneously to make the electrical interconnection between the drain terminal of the GaN die and the designated area on the DBC substrate. The solder paste used in this process is a lead-free solder paste (Sn89Sb10.5Cu0.5) with a melting temperature of around 240 ºC. After device soldering, 50-μm Al wires were bonded between the semiconductors and the electrical pads on the DBC substrate according to the optimized wire-bonding configuration. The gate, Kelvin, and source electrodes on the substrate were wire bonded to the Si MOSFET, and additional Al wires for signal sensing were bonded to the GaN HEMT. Two additional wire-connections were also formed between the gate of the GaN HEMT and the source of the Si MOSFET. Figure 9(a) and (b) show the photos of device after die-attachment and wire-bonding, respectively.
Fig. 10. New features of the developed package for cascode GaN device.
C. Encapsulation A silicone casting compound (Duraseal 1533, Cotronics, Brooklyn, NY) was used to make a mold for encapsulating process. The fabricated cascode GaN device was placed into the mold cavity in 10 mm x 10 mm x 3 mm dimensions. First the cavity was filled with an epoxy-based encapsulant (E60NC, Loctite, Rocky Hill, CT) to cover all components in the package and then cured for one day at room temperature. After the encapsulated device was released from the mold, the extra parts of the soldered Cu pillars were truncated and ground to be flush with the surface of the cured epoxy encapsulant. Figure 11 presents the key steps of the encapsulation process. This packaged device has the same terminal arrangement and a similar size as the commercial PQFN-packaged device mentioned above.
Fig. 11. Process flow of encapsulation.
Fig. 9. (a) Zoomed-in image of stack-die configuration and (b) cascode GaN device with stack-die structure and optimized wire-bonding configuration.
EXPERIMENTAL VERIFICATION AND DISCUSSION
The cascode GaN device in the new package was mounted on the same circuit boards used for the performance evaluation of the commercial device. Therefore, the influence of parasitics induced by the PCB layouts on the experimental results is excluded. Any potential performance improvement is solely determined by the different packaging structures.
One additional compensating capacitor and multiple Cu pillars (1 mm diameter) were attached to the DBC substrate through another soldering reflow process. The solder paste used in this step is of lead-tin (Pb-Sn) eutectic composition (Pb37Sn63) which has a lower melting point of 183 oC compared to the one used for the device assembly. Therefore, solder joints formed in the previous stack-die attachment process will not reflow during this soldering step. The embedded capacitor was arranged in parallel to the drain-source terminals of the Si MOSFET (the same as the gate-source terminals of the GaN HEMT) as designed. A zoomed-in image of the new package with integrated capacitor and attached Cu pillar terminals is shown in Fig. 10.
Figure 12 shows the experimental waveforms of the cascode GaN device in the new stack-die structure under 400 V/15 A turn-off conditions. The VGS_GaN is well controlled under its breakdown voltage (-35 V) without voltage overshoot during the turn-off transition. The significant parasitic ringing which is observed on the device in a traditional package is suppressed due to the elimination of CSIs in the new package. The new stack-die packaging structure with optimized wirebonding configuration has been proven to dramatically
packaged with this extra capacitor is about 1.5 W (16% loss reduction) at 1 MHz switching frequency, which can match with the estimated losses induced by the avalanche of the Si MOSFET and internal non-ZVS of the GaN HEMT . Such avalanche and internal switching losses and their impacts on the device reliability become more considerable at even higher frequency (> 5 MHz) operation. Adding the external capacitor in the package to compensate the junction capacitance mismatch between the Si and GaN devices has significant benefits for the device used for high-efficiency, high-frequency applications.
improve the device switching performance and reliability which makes this device more suitable for MHz operation.
The thermal performance of the cascode GaN device in new flip-chip packaging format has been analyzed using the same FEA simulation model. The simulation results are illustrated in Fig. 14. Compared with the results shown in Fig. 6, it can be observed that the improved packaging design in flip-chip configuration demonstrates a maximum temperature reduction of around 23 oC less than the original package using the stack-die structure. The accumulated heat in the ceramic layer of the DBC substrate and PCB material (shown in Fig. 6) is smoothly dissipated through the heat sink which is directly attached to the DBC substrate (demonstrated in Fig. 15). The stack-die packaged cascode GaN device in this flip-chip configuration can handle more power loss and induced heat than the device in a normal PQFN format.
Fig. 12. Experimental turn-off waveforms of the cascode GaN device in new stack-die packaging structure. The device was mounted on the same testing board for the performance evaluation of commercial product.
The function of the embedded capacitor (800 pF) in the new package was verified using the same boost converter running in CRM. The experimental waveforms of the cascode GaN device with the junction-capacitance-balancing capacitor are demonstrated in Fig. 13. In contrast with the results shown in Fig. 4, VDS_Si only rises to 26 V at t2, while Vsw has already reached the steady-state voltage 380 V during the turn-off transition. This confirms that adding the capacitor into the device package can effectively compensate the junction capacitance mismatch, and thus avoid the Si MOSFET reaching avalanche. At turn-on, Vsw drops to nearly 0 V when VDS_Si decreases to the threshold voltage at t2. The true ZVS turn-on of the GaN HEMT in the cascode structure is realized using this method.
Fig. 14. Temperature distribution of stack-die packaged cascode GaN device in flip-chip configuration: (a) top view and (b) cross-sectional view. The heat sink is attached directly to the bottom Cu layer of the DBC substrate. For a more clear comparison, the temperature scale (minimum and maximum temperatures) uses the same setup as shown in Fig. 6. The Cu pillars are not shown in the images because very little heat is transferred through that path..
Experimental results also demonstrate that the thermal performance of the device in this new package is better than the commercial device in a PQFN package. A thermocouple with a fine tip was used to locate the hot spot on the outer surface of both packaged devices with encapsulation. The maximum temperature measured for the newly packaged device is about 84 oC which is 10 oC lower than that monitored on the commercial device under the same experimental setup and driving condition. The thermal dissipation capability of the cascode GaN device in the stack-die structure has been improved using flip-chip design, which is favorable for further pushing the switching frequency of the device.
Fig. 13. Experimental waveforms of the cascode GaN device with an integrated compensating capacitor (a) steady-state: ZVS turn-on behavior is observed from the main terminals. It is similar to the waveform captured using the commercial device; (b) detailed turn-off transition; (c) detailed turnon transition.
A high-performance package is highly desirable to take full advantage of the superior characteristics (e.g., low onresistance, high breakdown voltage, fast switching capability) of GaN HEMT devices for high-frequency, high-power-
The embedded capacitor does not impact the driving loss of the device. Moreover, the total power saving of the device
density, and high-efficiency power conversion. Packaging of a depletion-mode GaN HEMT with an enhancement-mode Si MOSFET in the simple cascode structure would allow a normally-off device exhibiting the low power-loss and high threshold-voltage properties provided by the GaN and Si devices, respectively. The package for high-voltage cascode GaN devices has to be carefully designed to minimize the critical parasitic inductances and facilitate efficient heat extraction for high-frequency (≥ 1 MHz) applications. To overcome the packaging challenge induced by high switching speeds, a new package design has been developed to better utilize the high-performance GaN HEMT devices. First of all, the package-related common-source-inductances are all eliminated in the new package using a stack-die configuration together with rearrangement of the wire-bonding structure, which significantly improves the device switching performance and stability when operated at high frequencies. Secondly, the integration of an external capacitor into the device package provides a simple and effective solution to avoid avalanche of the low-voltage Si device during turn-off, and achieves true ZVS turn-on for the packaged cascode device. The resultant benefits of switching-loss reduction and reliability improvement are more notable at MHz-level switching speeds. Moreover, this advanced package demonstrates an enhanced thermal dissipation capability when compared to a traditional package. The newly developed package also provides the GaN device with robust protection from the environment and ease of handling. The long-term thermal cycling tests and mechanical stress analysis using FEA tool will be conducted to validate the reliability of the device packaged in this work. Looking into the future, it is likely that power GaN technology will advance continuously. The associated packaging technology thus needs to progress simultaneously to be able to effectively support the new high-current/power-density GaN devices.
  
The authors would like to thank Transphorm for providing GaN HEMT device samples used in this research work.
M.A. Khan, A. Bhattarai, J.N. Kuznia, and D.T. Olson, “High Electron Mobility Transistor Based on a GaN–AlxGa1-xN Heterojunction,” Appl. Phys. Lett., vol. 63, no. 9, pp. 1214–1515, 1993. Y. Wu, D. Kapolnek, J.P. Ibbetson, P. Parikh, B.P. Keller, and U.K. Mishra, “Very–High Power Density AlGaN/GaN HEMTs,” IEEE Trans. Electron Devices, vol. 48, no. 3, pp. 586–590, March, 2001. U.K. Mishra, P. Parikh, and Y. Wu, “AlGaN/GaN HEMTs – An Overview of Device Operation and Applications,” Proc. IEEE, vol. 90, no. 6, pp. 1022–1031, June, 2002. W. Saito, Y. Takada, M. Kuraguchi, K. Tsuda, I. Omura, T. Ogura, and H. Ohashi, “High Breakdown Voltage AlGaN–GaN Power–HEMT Design and High Current Density Switching Behavior,” IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2528–2531, December, 2003. W. Saito, T. Nitta, Y. Kakiuchi, Y. Saito, K. Tsuda, I. Omura, and M. Yamaguchi, “Suppression of Dynamic On–Resistance Increase and Gate Charge Measurements in High–Voltage GaN–HEMTs with Optimized Field–Plate Structure,” IEEE Trans. Electron Devices, vol. 54, no. 8, pp. 1825–1830, August, 2007. P. Roussel, “Will GaN–on–Si Displace Si and SiC in Power Electronics,” in Proc. CS MANTECH Conf., 2011, pp. 37–38.
T. Uesugi and T. Kachi, “Which are the Future GaN Power Devices for Automotive Applications, Lateral Structures or Vertical Structures,” in Proc. CS MANTECH Conf., 2011, pp. 307–310. T. MacElwee, J. Roberts, H. Lafontaine, I. Scott, G. Klowak, and L. Yushyna, “Characterization and Performance of D–mode GaN HEMT Transistor Used in a Cascode Configuration,” ECS Transactions, vol. 58, no. 4, pp. 167–177, 2013. Y. Uemoto, M. Hikita, H. Ueno, H. Matsuo, H. Ishida, M. Yanagihara, T. Ueda, T. Tanaka, and D. Ueda, “Gate Injection Transistor (GIT) – A Normally–Off AlGaN/GaN Power Transistor Using Conductivity Modulation,” IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3393– 3399, December, 2007. Y. Cai, Y. Zhou, K.M. Lau, and K.J. Chen, “Control of Threshold Voltage of AlGaN/GaN HEMTs by Fluoride–Based Plasma Treatment: From Depletion Mode to Enhancement Mode,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2207–2215, September, 2006. H. Kambayashi, Y. Satoh, Y. Niiyama, T. Kokawa, M. Iwami, T. Nomura, S. Kato, T.P. Chow, “Enhancement–Mode GaN Hybrid MOS– HFETs on Si Substrates with Over 70 A Operation,” in Proc. ISPSD, 2009, pp. 21–24. Efficient Power Conversion, Application Note: AN009, Assembling eGaN® FETs. GaN Systems, http://gansystems.com/ganpx_packaging_new.php T. McDonald and M.A. Briere, “Stacked Composite Device Including a Group III–V Transistor and a Group IV Lateral Transistor,” U.S. Patent 2012/0256188 A1, October 11, 2012. A. Lidow, D.M. Kinzer, and S. Sridevan, “Hybrid Semiconductor Device Having a GaN Transistor and a Silicon MOSFET,” U.S. Patent 8,368,120 B2, February 5, 2013. M. Rose, J. Sonsky, and P. Rutter, “Cascoded Semiconductor Devices,” U.S. Patent 2014/0145208 A1, May 29, 2014. H.S. Lee, T. McDonald, and L. Marlino, “GaN on Silicon-based Power Switch in a Sintered, Dual-side Cooled Package,” Power Electronics Technology, vol. 39, no. 1, p. 35, 2013. J. Roberts, “Lateral GaN Transistors – A Replacement for IGBT Devices in Automotive Applications,” in Proc. PCIM Europe, 2014, pp. 310–317. Transphorm, http://www.transphormusa.com/products RFMD, http://www.rfmd.com/product-category/gan-power-conversiondevices T. Stubbe, R. Mallwitz, R. Rupp, G. Pozzovivo, W. Bergner, O. Häberlen, and M. Kunze, “GaN Power Semiconductors for PV Inverter Applications – Opportunities and Risks,” in Proc. CIPS, 2014, pp. 1–6. Transphorm, https://www.transphormusa.com/sites/default/files/public/TPH3006LD %20v14%20R4_0.pdf Z. Liu, X. Huang, F.C. Lee, and Q. Li, “Package Parasitic Inductance Extraction and Simulation Model Development for the High–Voltage Cascode GaN HEMT,” IEEE Power Electron., vol. 29, no. 4, pp. 1977– 1985, April, 2014. Z. Liu, X. Huang, W. Zhang, F.C. Lee, and Q. Li, “Evaluation of High– Voltage Cascode GaN HEMT in Different Packages,” in Proc. APEC, 2014, pp. 168–173. X. Huang, W. Du, Z. Liu, F.C. Lee, and Q. Li, “Avoiding Si MOSFET Avalanche and Achieving True Zero–Voltage–Switching for Cascode Devices,” in Proc. ECCE, 2014, pp. 106–112. R.J. Trew, D.S. Green, and J.B. Shealy, “AlGaN/GaN HFET Reliability,” IEEE Microw. Mag., vol. 10, no. 4, pp. 116–127, June, 2009. S. Cheng and P. Chou, “Novel Packaging Design for High–Power GaN– on–Si High Electron Mobility Transistors (HEMTs),” Int. J. Therm. Sci., vol. 66, pp. 63–70, 2013. S. She, W. Zhang, X. Huang, W. Du, Z. Liu, F.C. Lee, and Q. Li, “Thermal Analysis and Improvement of Cascode GaN HEMT in Stack– Die Structure,” in Proc. ECCE, 2014, pp. 5709–5715.