A New Package of High-Voltage Cascode Gallium ... - IEEE Xplore

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new package is introduced for high-voltage cascode GaN devices and is successfully demonstrated to make the device more suitable for megahertz (MHz) ...

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2418572, IEEE Transactions on Power Electronics

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REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < of enhancement-mode GaN HEMT devices only includes the use of one chip, and it can be realized at the wafer level. The land grid array (LGA) packaging format has been adopted for the production of Efficient Power Conversion (EPC)’s commercial eGaN® devices. This chip-scale package (CSP) provides minimized package-related resistance and parasitic inductance as well as a minimal mounting footprint on the printed circuit board (PCB), which enables the high-speed switching of the eGaN® device with effectively reduced dynamic losses and ringing [12]. GaN Systems has also developed a near chip-scale package GaNPXTM for the highvoltage enhancement-mode GaN transistor for high-frequency, high-efficiency power conversion applications. The GaN transistor is surrounded by high-temperature fiberglass materials. The terminals on the embedded GaN device are electrically connected to the exposed mounting pads through copper (Cu) plated vias providing extremely low inductance [13]. Both packages introduced above are in a low-profile, wire-bondless structure. These high-current-density packaged GaN HEMT devices can be easily surface-mounted on the circuit board. In addition, some GaN device manufacturers still package the enhancement-mode GaN HEMT devices into a conventional wire-bonding configuration [14]. The fabrication of a high-performance enhancement-mode GaN HEMT is challenging due to their use of additional low-energy ion implantation, precise plasma etching, or other advanced processing techniques. The production yield of consistent and reliable devices is affected accordingly. Furthermore, the performance of enhancement-mode GaN HEMTs is compromised compared with that of the equivalent depletionmode GaN HEMT [8]. Another approach to realize the normally-off functionality for the GaN HEMT in a lateral AlGaN/GaN heterostructure is to co-package one additional low-voltage, normally-off switch; e.g., a power Si metal-oxide-semiconductor fieldeffect transistor (MOSFET) with high threshold voltage, connected in series to the high-voltage, normally-on GaN HEMT [15]–[17]. This cascode arrangement not only enables the normally-off operation, observed from the terminal behavior of the packaged device, but also avoids the performance degradation of the GaN transistor. The other significant benefit of using the cascode GaN devices over other GaN devices operated in enhancement-mode is that the existing gate drivers with proven reliability for the Si-based devices can be easily applied because the drive characteristics are defined by the low-voltage Si MOSFET [18]. The disadvantage of applying the cascode configuration is also obvious. The packaging of this normally-off device includes two chips, which may cause additional resistance, inductance, size, and thermal issues for the packaged cascode GaN device. Advanced packaging structures for GaN HEMT devices in the cascode configuration have been investigated for improving thermal reliability and electrical performance. Delphi and International Rectifier (IR) have demonstrated a wirebondless, dual-side cooled package including a 600 V depletion-mode GaN device cascoded with a low-voltage, normally-off Si device. Both sides of the GaN and Si chips are

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sintered to the direct bonded copper (DBC) substrate for making interconnection and enabling double-side cooling. The cascode GaN device with sintered packaging interconnects has been proven to have a longer expected working life than the GaN device in a typical wire-bonded package [18]. Another high-voltage GaN device in the cascode-configured package has been introduced by GaN Systems. The proprietary GaN HEMT with an “island” layout is either directly mounted on a Si-based CMOS driver device [8] or acts as a chip carrier for the Si MOSFET device [19]. Low-resistance and -inductance interconnections between the GaN and Si devices are achieved by using Cu posts instead of bonding wires or ribbons, which is beneficial for increasing switching speed. This stacked packaging configuration leads to a packaged cascode GaN device with high current density and low inductance. Because the relatively high cost of manufacturing these new packages must be taken into consideration when compared to the standard packaging processes used in Si technology, the traditional packages, i.e., TO-220 and power quad flat no-lead (PQFN) packages, are still the mainstream packaging formats widely adopted for the high-voltage cascode GaN devices on the market [20]–[22]. Bonding wires are commonly used in these packages to form electrical interconnections among GaN HEMT, Si MOSFET and terminal leads. In this study, the switching characteristics and thermal performance of a commercial cascode GaN device in a traditional PQFN package are firstly considered for megahertz (MHz) operation. Then, a new package of this normally-off GaN device configured in the same cascode structure is created. A 600 V lateral GaN HEMT is co-packaged with a 30 V vertical Si MOSFET in the stack-die structure with the optimized arrangement of bonding wires. A balancing capacitor is also integrated into the device package in order to compensate the junction capacitance mismatch between the GaN and Si devices. The flip-chip configuration is realized in this advanced package for easy and effective thermal management as well as better reliability. The whole packaging of the high-voltage cascode GaN device is still contained in a PQFN format with the new features listed above. Finally, this cascode GaN device in the newly developed package has demonstrated better switching and thermal performance than the equivalent commercial product packaged using the same GaN HEMT and Si MOSFET chips. II. PERFORMANCE EVALUATION OF CASCODE GAN DEVICE The switching and thermal characteristics of a commercial high-voltage cascode GaN device from Transphorm [20] have been studied with an emphasis on the impact of the package on the performance, especially for megahertz (MHz) applications. Subsequently the packaging improvement approaches are proposed based on the performance evaluation and detailed analysis of this device. A. Influence of Package-Induced Parasitic Inductances A simulation model was developed and verified to be able to predict the high-frequency switching performance of the cascode GaN device and analyze the package-induced

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2418572, IEEE Transactions on Power Electronics

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REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < B. Effect of Junction Capacitance Mismatch Between GaN and Si Devices Soft-switching has been demonstrated to be critical for high-voltage cascode GaN devices in high-frequency, highefficiency applications. Achieving ZVS turn-on of the GaN HEMT can dramatically reduce the turn-on loss of the device with very small increase in turn-off loss [25]. Furthermore, the junction capacitors of the Si MOSFET and GaN HEMT have to be equally matched to achieve high efficiency, especially under soft-switching conditions [26]. The voltage distribution between the high-voltage GaN device and low-voltage Si device during the turn-off transition is mainly determined by the junction capacitor charges. In some circumstances, the Si MOSFET may achieve avalanche before the complete turn-off of the GaN HEMT. The GaN HEMT cannot realize true ZVS if the Si MOSFET reaches avalanche, even when the external waveform of the cascode device behaves like ZVS, as shown in Fig. 4. A detailed analysis of the principles of voltage distribution at turn-off and realization of true ZVS at turn-on for the cascode GaN HEMT device is introduced in [26].

Fig. 4. Experimental waveforms of a cascode GaN device without compensating capacitor: (a) Steady-state: the ZVS turn-on behavior has been “seen” from the main terminals. Vsw is the terminal voltage across the cascode GaN device and iL is the inductor current; (b) Detailed turn-off transition: VDS_Si reaches avalanche voltage at t2, while Vsw only rises to around 170 V. After t2, the drain-source junction capacitance of the GaN device (CDS_GaN) is continuously charged through the avalanched path of the Si device till Vsw reaches steady-state voltage at t3; and (c) Detailed turn-on transition: VDS_Si decreases to the threshold voltage of the GaN device at t2 while Vsw only drops to around 280 V. The remaining energy stored in CDS_GaN is dissipated through the channel of the GaN device till Vsw reaches 0 V at t3 [26]. The cascode GaN device was mounted on a 1 MHz 180 V/380 V critical current mode (CRM) boost converter.

The avalanche of the Si MOSFET and the internal non-ZVS of the GaN HEMT cause additional power losses in every switching cycle. Both losses are proportional to the switching frequency and must be eliminated for MHz-frequency applications. Additionally, repetitive avalanche currents in the Si MOSFET could lead to a reduction of the lifetime and reliability of the cascode GaN device [15].

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Fig. 5. (a) Circuit diagram of the cascode GaN device with a compensating capacitor (Cx) and other device junction capacitors; and (b) Illustration of the internal layout of the new package for the cascode GaN device with an integrated external capacitor. The capacitor is in the shaded area.

A Si MOSFET with a large junction capacitance can be selected to pair with the GaN HEMT considering the balance of junction capacitance. However, the total gate charge of the Si MOSFET will also increase, which will increase the driving loss significantly at high-frequency operation. Moreover, the increase of gate-to-drain capacitance will prolong the turn-off transition and increase the switching loss for the Si MOSFET. A simple but effective way to balance the mismatched junction capacitance between the Si MOSFET and GaN HEMT is to add an external capacitor in parallel with the drain-source terminals of the Si MOSFET. A properly selected capacitance should allow the GaN HEMT to achieve its steady-state voltage before the Si MOSFET reaches its avalanche voltage. Paralleling the capacitor between the drainsource terminals of the Si MOSFET will not increase its driving loss, and the turn-off loss is still very small due to the merits of the cascode structure [26]. The circuit diagram of a cascode GaN device with the extra compensating capacitor is illustrated in Fig. 5(a). Although the junction capacitance mismatch is induced by the devices and not the package, the compensation can be made by integrating the capacitor within the new package, as shown in Fig. 5(b). Avoiding avalanche for the Si transistor and achieving true ZVS for the GaN transistor could be realized by this method. C. Evaluation of Thermal Performance Thermal management of the package is a critical factor to improving device performance and reliability for highfrequency, high-efficiency power conversion. GaN semiconductors have poor thermal conductivity, which makes heat removal difficult for this material. The junction temperature rise and non-uniform power distribution in the GaN HEMT will lead to the formation of hotspots near the device channel, degradation of performance, and eventually device failure [27], [28]. Moreover, the normally-on GaN HEMT used in this cascode device has been developed based on the GaN-on-Si substrate. The attempt of using highly thermally conductive but more expensive silicon carbide (SiC) substrate is excluded due to the promising future of GaN-on-Si technology for power electronics. Other thermal management solutions must be used to improve heat dissipation from the GaN HEMT at the package-level. A simulation model has been built using the finite element analysis (FEA) method to evaluate the thermal performance of

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2418572, IEEE Transactions on Power Electronics

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < the cascode GaN device packaged in a stack-die structure [29]. Table I lists the thermal conductivities of all materials used in the thermal model, all of which are considered to be isotropic and temperature independent. Additionally, all interfaces between different materials are assumed to be perfectly bonded without any defects. In order to further simplify the thermal simulation model and ensure the established model is in agreement with the actual physical system, further assumptions are made: (1) all devices work in thermal equilibrium, and the temperature distribution of the model reaches steady state; (2) heat only transfers in conduction and convection methods, and the internal heat radiation is ignored; and (3) contact thermal resistance is neglected. TABLE I THERMAL CONDUCTIVITY OF MAIN COMPONENTS USED IN THE STACK-DIE PACKAGING CONFIGURATION Material

Si

GaN

Cu

Al

Thermal conductivity (W/m·K)

45

130

397

207

Al2O3 AlN Solder PCB 20

150

50

0.5

Figure 6 represents the simulation results of temperature distribution of the packaged device in a stack-die structure with the PCB and heat sink attached to the bottom side of DBC substrate. Two primary heating sources, the GaN HEMT and the Si MOSFET, are overlapped on purpose. The junction temperature (Tj) rating of the GaN HEMT is limited by the Tj of the Si MOSFET due to the adjacent heat transfer, whereas in a side-by-side arrangement the Tj of the GaN device can be higher than that of the Si device. Most heat generated by the semiconductor devices has to transfer vertically from the top active chips to the DBC substrate, mounted PCB, and the bottom heat sink, successively. As observed in Fig. 6(b), it is apparent that a significant amount of heat accumulates at the ceramic layer of the DBC substrate and the PCB layer even though a series of thermal vias is designed in the circuit board to conduct heat from the device to the heat sink. Preliminary experimental results have demonstrated that the commercial device in the traditional PQFN exhibits better thermal performance than the cascode GaN device packaged in this format [29]. A more efficient thermal management method must be developed for improving the reliability of the device in a stack-die structure.

Fig. 6. Temperature distribution of the cascode GaN device packaged in a stack-die structure and surface-mounted on PCB: (a) Top view; and (b) Crosssectional view. Heat sink is attached to the other side of the PCB.

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It is a common practice to maintain a continuous low thermal resistance/impedance path from the packaged semiconductor to the environment. A straightforward method to improve the thermal performance of the stack-die packaged cascode GaN device is to use aluminum nitride (AlN)-based DBC instead of low-cost alumina (Al2O3)-based DBC as substrate. The thermal conductivity of AlN is seven to eight times higher than that of Al2O3. However, heat still accumulates in the low thermally conductive PCB part. One approach which can minimize the limitation of the PCB on heat dissipation is to adopt the flip-chip packaging concept. The heat sink can be directly attached to the bottom Cu layer of the DBC substrate, and the device terminals (gate, source, and drain) are designed to be on the top side of the DBC for subsequent attachment to the circuit board. The bottom Cu attached to the heat sink is insulated from the top terminals by the middle AlN ceramic. A three-dimensional (3D) model showing the flip-chip design of a cascode GaN device in stack-die structure (Figure 7) was built to analyze the thermal performance.

Fig. 7. 3-D model of flip-chip design for the cascode GaN device in stack-die structure. The heat sink is attached to the bottom of the DBC substrate using thermal grease. Cu pillars are soldered on the top side of the DBC as interconnection terminals.

III. FABRICATION OF CASCODE GAN DEVICE IN NEW PACKAGE The cascode GaN device designed in a stack-die structure featuring an embedded capacitor and flip-chip configuration is packaged in a low profile format similar to the conventional PQFN package. As presented in Fig. 8, the packaged device with encapsulation can be easily surface-mounted on the testing board using the solder reflow technique. The device fabrication procedure includes three major steps: substrate preparation, device assembly, and encapsulation.

Fig. 8. Photos of packaged cascode GaN device with new features: (a) Internal structure; and (b) Device in an epoxy encapsulation, top surface ready for attaching heat sink and bottom surface for surface-mounting on the PCB.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2418572, IEEE Transactions on Power Electronics

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < A. Substrate Preparation Aluminum nitride direct-bonded-copper substrate (AlN– DBC; AlN 380 μm, Cu 170 μm), which has high strength and good thermal conductivity, was selected as the chip carrier for this power semiconductor assembly. First, 25-μm thick adhesive Kapton® tape as etching mask was applied entirely on both the top and bottom Cu surfaces of the DBC substrate. After laser patterning, the attached tapes were selectively subtracted according to the circuit layout. The exposed Cu areas have been then etched off by ferric chloride solution to form the circuitry on the DBC substrate. Next, oxygen plasma was used to remove impurities and contaminants from the Cu surfaces. Finally, the plasma-cleaned top Cu pads were electro-plated with nickel (Ni) and gold (Au) successively, which helps to avoid the surface oxidation and facilitates the die-attachment and wire-bonding processes. The thickness of the Au-finished surface is in the range of 0.8 to 1.2 µm. The process flow of substrate preparation is displayed in Fig. 9.

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the designated area on the DBC substrate. The solder paste used in this process is a lead-free solder paste (Sn89Sb10.5Cu0.5) with a melting temperature of around 240 ºC. After device soldering, 50-μm Al wires were bonded between the semiconductors and the electrical pads on the DBC substrate according to the optimized wire-bonding configuration. The gate, Kelvin, and source electrodes on the substrate were wire bonded to the Si MOSFET, and additional Al wires for signal sensing were bonded to the GaN HEMT. Two additional wireconnections were also formed between the gate of the GaN HEMT and the source of the Si MOSFET. Figure 10(a) and (b) show the photos of device after die-attachment and wirebonding, respectively.

Fig. 9. Preparation procedure of DBC substrate for die-attachment and wirebonding. The AlN-DBC substrate was purchased from Stellar Ceramics, Millbury, MA. A CO2 laser system (Resonetics, Nashua, NH) was used to cut the Kapton® tape and substrate. The extra Cu has been etched off using a bench-top etching machine (BTD-201B; Kepro Circuit Systems, St. Louis, MI). An electro-plating station (Universal Plater, Gold Plating Services, Kaysville, UT) was used to add Ni and Au layers on top of the Cu surface.

B. Device Assembly A 600 V GaN HEMT and 30 V Si MOSFET bare dies were selected for the device assembly in the stack-die structure. They are the same devices used in the commercial cascode GaN device in the traditional PQFN package [23]. The GaN die and a Cu spacer in the same thickness as the GaN chip were firstly attached on the substrate. The Cu spacer was used in order to level the position of Si device mounted directly on the GaN device. Then, a solder mask protecting the channel area and gate terminals was applied on the top surface of the GaN die with only the source and drain pads uncovered. Next, the Si die was soldered on top of the GaN die. The solder joint connects the drain terminal of the Si MOSFET to the source terminal of the GaN HEMT without wire-bonding. Because the top terminal pads of the GaN HEMT are coated with Au and the bottom drain terminal of the Si MOSFET is plated with silver, no further surface treatment is required for soldering the interfacing metals on these two devices. A piece of Au-plated Cu foil (200 μm thick) with preformed bends was also soldered simultaneously to make the electrical interconnection between the drain terminal of the GaN die and

Fig. 10. (a) Zoomed-in image of stack-die configuration; and (b) Cascode GaN device with stack-die structure and optimized wire-bonding configuration. The soldering process was done using a reflow belt furnace (Sikama, Santa Barbara, CA). A thin-wire wedge bonder (Bondjet BJ820, Hesse Mechatronics, Fremont, CA) was used for Al wire bonding.

Fig. 11. New features of the developed package for high-voltage cascode GaN device.

One additional compensating capacitor and multiple Cu pillars (1 mm diameter) were attached to the DBC substrate through another soldering reflow process. The solder paste

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2418572, IEEE Transactions on Power Electronics

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < used in this step is of lead-tin (Pb-Sn) eutectic composition (Pb37Sn63) which has a lower melting point of 183 oC compared to the one used for the device assembly. Therefore, solder joints formed in the previous stack-die attachment process will not reflow during this soldering step. The embedded capacitor was arranged in parallel to the drainsource terminals of the Si MOSFET (the same as the gatesource terminals of the GaN HEMT) as designed. A zoomedin image of the new package with integrated capacitor and attached Cu pillar terminals is shown in Fig. 11. C. Encapsulation A silicone casting compound (Duraseal 1533, Cotronics, Brooklyn, NY) was used to make a mold for encapsulating process. The fabricated cascode GaN device was placed into the mold cavity in 10 mm x 10 mm x 3 mm dimensions. First the cavity was filled with an epoxy-based encapsulant (E60NC, Loctite, Rocky Hill, CT) to cover all components in the package and then cured for one day at room temperature. After the encapsulated device was released from the mold, the extra parts of the soldered Cu pillars were truncated and ground to be flush with the surface of the cured epoxy encapsulant. Figure 12 presents the key steps of the encapsulation process. This packaged device has the same terminal arrangement and a similar size as the commercial PQFN-packaged device mentioned above.

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packaging structure with optimized wire-bonding configuration has been proven to dramatically improve the device switching performance and reliability which makes this device more suitable for MHz operation.

Fig. 13. Turn-off waveforms of the cascode GaN device in new stack-die packaging structure: (a) Experimental result; and (b) Simulation result comparison to the device in the traditional package. The device was mounted on the same testing board for the performance evaluation of commercial product. Note: the stack-die packaged device used for this test does not include the capacitance matching capacitor.

The function of the embedded capacitor (800 pF) in the new package was verified using the same boost converter running in CRM. The experimental waveforms of the cascode GaN device with the junction-capacitance-balancing capacitor are demonstrated in Fig. 14. In contrast with the results shown in Fig. 4, VDS_Si only rises to 26 V at t2, while Vsw has already reached the steady-state voltage 380 V during the turn-off transition. This confirms that adding the capacitor into the device package can effectively compensate the junction capacitance mismatch, and thus avoid the Si MOSFET reaching avalanche. At turn-on, Vsw drops to nearly 0 V when VDS_Si decreases to the threshold voltage at t2. The true ZVS turn-on of the GaN HEMT in the cascode structure is realized using this method.

Fig. 12. Process flow of encapsulation.

IV. EXPERIMENTAL VERIFICATION AND DISCUSSION The cascode GaN device in the new package was mounted on the same circuit boards used for the performance evaluation of the commercial device. Therefore, the influence of parasitics induced by the PCB layouts on the experimental results is excluded. Any potential performance improvement is solely determined by the different packaging structures. Figure 13(a) shows the experimental waveforms of the cascode GaN device in the new stack-die structure under 400 V/15 A turn-off conditions. The VGS_GaN is well controlled under its breakdown voltage (-35 V) without voltage overshoot during the turn-off transition. The significant parasitic ringing which is observed on the device in a traditional package is suppressed due to the elimination of CSIs in the new package. The comparison of simulation waveforms for the VGS_GaN obtained from different packaged devices is presented in Fig. 13(b). The new stack-die

Fig. 14. Experimental waveforms of the cascode GaN device with an integrated compensating capacitor (a) Steady-state: ZVS turn-on behavior is observed from the main terminals. It is similar to the waveform captured using the commercial device; (b) Detailed turn-off transition; and (c) Detailed turnon transition.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2418572, IEEE Transactions on Power Electronics

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < The embedded capacitor does not impact the driving loss of the device. Moreover, the total power saving of the device packaged with this extra capacitor is about 1.5 W (16% loss reduction) at 1 MHz switching frequency, which can match with the estimated losses induced by the avalanche of the Si MOSFET and internal non-ZVS of the GaN HEMT [27]. Such avalanche and internal switching losses and their impacts on the device reliability become more considerable at even higher frequency (> 5 MHz) operation. Adding the external capacitor in the package to compensate the junction capacitance mismatch between the Si and GaN devices has significant benefits for the device used for high-efficiency, highfrequency applications. Although adding such capacitor will slightly slow down the turn-on and turn-off transitions, the energy stored in this capacitor can be recycled if the cascode device is operated at the soft-switching application. Therefore, the negative impact of integrating the capacitor into the package is negligible. The thermal performance of the cascode GaN device in new flip-chip packaging format has been analyzed using the same FEA simulation model. The simulation results are illustrated in Fig. 15. Compared with the results shown in Fig. 6, it can be observed that the improved packaging design in flip-chip configuration demonstrates a maximum temperature reduction of around 23 oC less than the original package using the stackdie structure. The accumulated heat in the ceramic layer of the DBC substrate and PCB material (shown in Fig. 6) is smoothly dissipated through the heat sink which is directly attached to the DBC substrate (demonstrated in Fig. 15). The stack-die packaged cascode GaN device in this flip-chip configuration can handle more power loss and induced heat than the device in a normal PQFN format.

Fig. 15. Temperature distribution of stack-die packaged cascode GaN device in flip-chip configuration: (a) Top view; and (b) Cross-sectional view. The heat sink is attached directly to the bottom Cu layer of the DBC substrate. The thickness and properties of the solder material and thermal grease are the same as used in the other simulation. For a more clear comparison, the temperature scale (minimum and maximum temperatures) uses the same setup. The Cu pillars are not shown in the images because very little heat is transferred through that path.

Experimental results also demonstrate that the thermal performance of the device in this new package is better than the commercial device in a PQFN package. A thermocouple with a fine tip was used to locate the hot spot on the outer surface of both packaged devices with encapsulation. The maximum temperature measured for the newly packaged device is about 84 oC which is 10 oC lower than that monitored on the commercial device under the same

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experimental setup and driving condition. The thermal dissipation capability of the cascode GaN device in the stackdie structure has been improved using flip-chip design, which is favorable for further pushing the switching frequency of the device. V. CONCLUSIONS A high-performance package is highly desirable to take full advantage of the superior characteristics (e.g., low onresistance, high breakdown voltage, fast switching capability) of GaN HEMT devices for high-frequency, high-powerdensity, and high-efficiency power conversion. Packaging of a depletion-mode GaN HEMT with an enhancement-mode Si MOSFET in the simple cascode structure would allow a normally-off device exhibiting the low power-loss and high threshold-voltage properties provided by the GaN and Si devices, respectively. The package for high-voltage cascode GaN devices has to be carefully designed to minimize the critical parasitic inductances and facilitate efficient heat extraction for high-frequency (≥ 1 MHz) applications. To overcome the packaging challenge induced by high switching speeds, a new package design has been developed to better utilize the high-performance GaN HEMT devices. First of all, the package-related common-source-inductances are all eliminated in the new package using a stack-die configuration together with rearrangement of the wire-bonding structure, which significantly improves the device switching performance and stability when operated at high frequencies. Secondly, the integration of an external capacitor into the device package provides a simple and effective solution to avoid avalanche of the low-voltage Si device during turn-off, and achieves true ZVS turn-on for the packaged cascode device. The resultant benefits of switching-loss reduction and reliability improvement are more notable for MHz operation. Moreover, this advanced package demonstrates an enhanced thermal dissipation capability when compared to a traditional package. The newly developed package also provides the GaN device with robust protection from the environment and ease of handling. However, the reliability issues of this stack-die packaged cascode GaN device needs to be further identified, for example, the possible failure caused by the de-attachment of the solder layer between the GaN HEMT and the Si MOSFET at the high temperature. The long-term thermal cycling tests and mechanical stress analysis using FEA tool will be conducted to validate the reliability of the device packaged in this work. Also, the cascode GaN device packaged in this structure requires more time and cost to fabricate compared to the one packaged in a traditional PQFN format, but its benefits are prominent for high-frequency operation and may outweigh the disadvantages. Looking into the future, it is likely that power GaN technology will advance continuously; for example, there are ongoing research efforts on the development of vertical GaN-based transistors on a free-standing GaN substrate with high blocking voltage [30], [31]. The associated packaging technology thus needs to progress simultaneously to be able to effectively support the new high-current/power-density GaN devices.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2418572, IEEE Transactions on Power Electronics

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < ACKNOWLEDGMENT The authors would like to thank Transphorm for providing GaN HEMT device samples used in this research work. REFERENCES [1]

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Wenli Zhang received the B.S. and M.S. degrees in materials science and engineering from Beijing University of Technology, Beijing, China, in 2003 and 2006, respectively, and the Ph.D. degree from University of Kentucky, Lexington, Kentucky, in 2011, in the area of advanced ceramic materials and processing. He is currently a Research Assistant Professor working at the Center for Power Electronics Systems at Virginia Tech. His research interests include piezoelectric and magnetic ceramics, LTCC materials and technology, highdensity packaging and integration of power electronics modules. Xiucheng Huang (S’12) was born in Zhejiang, China, in 1986. He received the B.S. and M.S. degree in electrical engineering from Zhejiang University, Hangzhou, China, in 2008 and 2011, respectively. He is currently working toward the Ph.D. degree at the Center for Power Electronics Systems, Virginia Tech. His main research interests include high-frequency high-power-density power conversion, soft-switching technique and power architecture. Zhengyang Liu (S’12) received the B.S. degree in electrical engineering from Zhejiang University, Hangzhou, China, in 2011. He is currently working toward the Ph.D. degree at the Center for Power Electronics Systems, Virginia Tech. His research interests include high-frequency power conversion techniques and wide band-gap power semiconductor devices.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2418572, IEEE Transactions on Power Electronics

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < Fred C. Lee (S’72–M’74–SM’87–F’90–LF’12) received the B.S. degree from the National Cheng Kung University, Tainan, Taiwan, in 1968, and the M.S. and Ph.D. degrees from Duke University, Durham, NC, in 1972 and 1974, respectively, all in electrical engineering. He is currently a University Distinguished Professor at Virginia Tech, Blacksburg, where he is also the Director of the Center for Power Electronics Systems, a National Science Foundation Engineering Research Center (NSF ERC) established in 1998. Over the ten-year NSF ERC Program, CPES has been cited as a model ERC for its industrial collaboration and technology transfer, as well as education and outreach programs. He holds 72 U.S. patents and has published 252 journal articles and more than 640 refereed technical papers. During his tenure at Virginia Tech, he has supervised to completion 75 Ph.D. and 83 Master’s students. His research interests include high-frequency power conversion, distributed power systems, renewable energy, power quality, high-density electronics packaging and integration, and modeling and control. Dr. Lee received the William E. Newell Power Electronics Award in 1989, the Arthur E. Fury Award for Leadership and Innovation in Advancing Power Electronic Systems Technology in 1998, and the Ernst-Blickle Award for achievement in the field of power electronics in 2005. He has served as president of the IEEE Power Electronics Society during 1993–1994. He was named to the National Academy of Engineering in 2011. In 2012, he was elected to Academia Sinica in Taiwan and inducted into Virginia Tech Faculty Entrepreneur Hall of Fame.

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Shuojie She E-mail: sheshuojie@emails.bjut.edu.cn Mailing address: College of Electronic Information and Control Engineering, Pingleyuan 100, Chaoyang District, Beijing 100124, China Phone: 86-10-67392125 Fax: 86-10-67392125 Weijing Du E-mail: weijing@vt.edu Mailing address: 674 Whittemore Hall, Blacksburg, Virginia 24061, USA Phone: 540-808-9323 Fax: 540-231-6390 Qiang Li E-mail: lqvt@vt.edu Mailing address: 671 Whittemore Hall, Blacksburg, Virginia 24061, USA Phone: 540-231-6225 Fax: 540-231-6390

Shuojie She received the B.S. degree in electrical engineering from Beijing University of Technology, Beijing, China, in 2009. He is currently working toward the Ph.D. degree in Reliability Physics Lab, Beijing University of Technology. From September 2013 to August 2014, he was a Visiting Scholar at the Center for Power Electronics Systems, Virginia Tech. His main research interests include power devices, reliability of semiconductor devices and integrated circuits, and electronics packaging thermal design. Shuojie She Weijing Du was born in Shanxi, China, in 1985. She received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, Zhejiang University, Hangzhou, China, in 2008 and 2013. She is currently a Visiting Scholar at the Center for Power Electronics Systems, Virginia Tech. Her current research interests include high-frequency high-density power converters and gallium nitride device applications.. Qiang Li (M’11) received the B.S. and M.S. degrees in power electronics from Zhejiang University, Zhejiang, China, in 2003 and 2006, respectively, and the Ph.D. degree from Virginia Tech, Blacksburg, Virginia, in 2011. He is currently an Assistant Professor at the Center for Power Electronics Systems, Virginia Tech. His research interests include high-density electronics packaging and integration, high-frequency magnetic components, and highfrequency power conversion.

* Wenli Zhang E-mail: wzhang11@vt.edu Mailing address: 669 Whittemore Hall, Blacksburg, Virginia 24061, USA Phone: 540-231-8209 Fax: 540-231-6390 * Corresponding Author Xiucheng Huang E-mail: xiucheng@vt.edu Mailing address: 674 Whittemore Hall, Blacksburg, Virginia 24061, USA Phone: 540-231-4722 Fax: 540-231-6390 Zhengyang Liu E-mail: lzy@vt.edu Mailing address: 674 Whittemore Hall, Blacksburg, Virginia 24061, USA Phone: 540-808-3724 Fax: 540-231-6390 Fred C. Lee E-mail: fclee@vt.edu Mailing address: 648 Whittemore Hall, Blacksburg, Virginia 24061, USA Phone: 540-231-7716 Fax: 540-231-6390

0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.