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Jun 19, 2015 - Modern switching converters for medium input voltage [1, 2] have been ... multilevel converters [7–15] to improve circuit efficiency. ... the load power into several sub-circuits with low current rating of power semiconductors and.

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS Int. J. Circ. Theor. Appl. 2016; 44:874–892 Published online 19 June 2015 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.2111

A new parallel ZVS converter with less power switches and low current stress components Bor-Ren Lin*,† and Chung-Wei Chu Department of Electrical Engineering, National Yunlin University of Science and Technology, 123, section 3, university road, Douliu City, Yunlin 640, Taiwan

SUMMARY A new direct current (DC)/DC converter with parallel circuits is presented for medium voltage and power applications. There are five pulse-width modulation circuits in the proposed converter to reduce current stress at low voltage side for high output current applications. These five circuits share the same power switches in order to reduce switch counts. To reduce the converter size, conduction loss, and voltage stress of power semiconductors, the series connections of power metal-oxide-semiconductor field-effect transistor (MOSFET) with high switching frequency instead of insulated gate bipolar transistor (IGBT) with low switching frequency are adopted. Thus, the voltage stress of MOSFETs is clamped at half of input voltage. The switched capacitor circuit is adopted to balance input split capacitor voltages. Asymmetric pulse-width modulation scheme is adopted to generate the necessary switching signals of MOSFETs and regulate output voltage. Based on the resonant behavior at the transition interval of power switches, all MOSFETs are turned on under zero voltage switching from 50% load to 100% load. The circuit configuration, operation principle, converter performance, and design example are discussed in detail. Finally, experimental verifications with a 1.92 kW prototype are provided to verify the performance of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd. Received 27 November 2014; Revised 23 April 2015; Accepted 24 May 2015 KEY WORDS:

analog circuit; pulse-width modulation; DC/DC converter; ZVS; efficiency; power converter

1. INTRODUCTION Modern switching converters for medium input voltage [1, 2] have been developed for DC traction system, rapid transit systems, or medium power applications with three-phase alternating current (AC) input. Multilevel converters [3–6] have developed to lessen voltage stress of power devices and increase the switching frequency so that the converter size can be reduced. However, power devices in these topologies are operated at hard switching, and the switching losses are increased if the high switching frequency is adopted. Therefore, soft switching techniques were proposed for multilevel converters [7–15] to improve circuit efficiency. In [7–11], the auxiliary circuits are adopted in three-level converter with asymmetric or phase-shift pulse-width modulation (PWM) to achieve zero voltage switching (ZVS) or zero current switching for power switching or extend the ZVS load range. In [14], three-level converters with resonant circuit were developed to have ZVS on power devices and zero current switching on rectifier diodes. The variable switching frequency is adopted to control DC voltage gain and regulate output voltage. The ripple current at output capacitor is much larger than that of the conventional three-level converter. Three-level resonant converters with duty cycle control were presented in [15] to have soft switching on power devices *Correspondence to: Bor-Ren Lin, Department of Electrical Engineering, National Yunlin University of Science and Technology, 123, section 3, university road, Douliu City, Yunlin 640, Taiwan. † E-mail: [email protected] Copyright © 2015 John Wiley & Sons, Ltd.

A NEW PARALLEL ZVS CONVERTER WITH LESS POWER SWITCHES

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with fixed switching frequency. However, these control schemes have high circuit efficiency if the duty cycle is close to half of switching period. If the input voltage is increased, then the duty cycle is decreased and the conduction losses are increased. Thus, the converter cannot be maintained at high circuit efficiency at different loads or input voltage cases. For medium voltage and load current applications, parallel three-level converters are needed if the high load usually adopted to distribute the load power into several sub-circuits with low current rating of power semiconductors and passive components. However, parallel topologies normally need several control units to individually control each sub-circuit. Hence, there are too many power switches and control units in conventional parallel converters. A new soft switching PWM DC/DC converter is presented in this paper to achieve the functions of the following: (1) less switch counts compared with the conventional parallel three-level DC/DC converters; (2) ZVS turn-on for all power switches; (3) small size, light weight, and low current stress of passive components; (4) low voltage stress of power switches; and (5) the balanced input split capacitor voltages. In order to reduce the component size to meet the compact size demands for medium power applications, the high-frequency link DC/DC converter with parallel topology is used in the proposed converter. The proposed converter includes five DC/DC sub-circuits with shared power switches to distribute the total power into each sub-circuit. Hence, total switch counts are reduced compared with the conventional parallel converters, and each circuit only has one-fifth of the total power rating. The voltage and current stress of passive components at low voltage side can be reduced. Asymmetric PWM (APWM) scheme is adopted to generate the properly gating signals of all power switches to achieve ZVS operation. Two half-bridge legs are adopted at high voltage side to decrease the voltage stress of each power switch at one-half of the input voltage. Two balance capacitors are adopted in the proposed converter to automatically balance input split capacitor voltages. Finally, experiments are presented for a 1.92 kW prototype circuit converting 800 V input to an output voltage 24 V/80 A for industry power supplies or battery chargers.

2. PROPOSED CONVERTER AND OPERATIONAL PRINCIPLE 2.1. Conventional circuit configurations The conventional half-bridge ZVS converters with asymmetrical PWM are shown in Figure 1(a) and (c). The primary side can be connected between the center point of the half-bridge leg and ground point or positive voltage point as shown in Figure 1(a) and (b), respectively. Similarly, the other half-bridge ZVS converter is shown in Figure 1(c) with the primary side connected between the center point of the half-bridge circuit and input split capacitors C1 and C2. The primary side current is flowing through capacitors C1 and C2, and the current stress of C1 and C2 is less than that of capacitor C in Figure 1(a) and (b). For medium power or high current applications, the parallel connection of several sub-circuits is usually adopted at input or output side. However, more power switches are used in the parallel converter for medium power applications. Figure 1(d) shows the proposed half-bridge converter with three sub-circuits and less switch counts compared with the conventional parallel half-bridge converter. Three sub-circuits have the same circuit characteristics to provide medium power to load side. 2.2. Proposed circuit configuration For medium input voltage applications such as DC traction systems or three-phase AC/DC converters, input voltage of DC/DC converters will be higher than 750 V. Thus, the voltage stress of power switches in the proposed converter shown in Figure 1(d) should be greater than 800 V. Power MOSFETs with high voltage stress have large turn-on resistance, and the conduction loss on MOSFETs is increased. To solve this problem, the series half-bridge circuits are proposed in Figure 2. The voltage stress of MOSFETs is clamped at Vin/2 so that MOSFETs with 600 V voltage stress can be used in the proposed converter for 750 V input applications. The circuit components at high voltage side have input voltage Vin, input split capacitors C1–C4, power MOSFETs S1–S4 with their body diodes and parallel capacitors Cr1–Cr4, DC blocking capacitors C5–C8, resonant inductors Lr1–Lr5, and transformers T1–T5. At low voltage and high current side, five center-tapped rectifiers Copyright © 2015 John Wiley & Sons, Ltd.

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Figure 1. Circuit configuration of half-bridge zero voltage switching (ZVS) converters with 400 V input voltage: (a) half-bridge ZVS converter with low voltage side connection, (b) half-bridge ZVS converter with high voltage side connection, (c) half-bridge ZVS converter with split capacitors, and (d) proposed halfbridge ZVS converter with three circuit cells.

Figure 2. Circuit configuration of the proposed zero voltage switching converter with medium input voltage.

are connected in parallel to reduce the current stress of transformer windings, rectifier diodes D1–D10, and output filter inductors Lo1–Lo5. Five ZVS circuits are adopted in the proposed converter to share load current. Circuits 1, 2, and 4 are based on the half-bridge topology with split capacitors. Circuits 3 and 5 are based on half-bridge topology with transformer connected to high voltage side and ground point, respectively. Power MOSFETs S1 and S3 the have same PWM waveforms with duty cycle δ. However, MOSFETs S2 and S4 have same PWM waveforms with duty cycle (1  δ). The components S1–S4, C1–C4, C6, and C7 establish a switched capacitor circuit [16]. Therefore, input split capacitor voltages are balanced, vC1 + vC2 = vC3 + vC4 = vC6 + vC7 = Vin/2. Asymmetric PWM is adopted to generate PWM signals S1–S4 and regulate output voltage at the desired voltage level. Copyright © 2015 John Wiley & Sons, Ltd.

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A NEW PARALLEL ZVS CONVERTER WITH LESS POWER SWITCHES

2.3. Operation analysis In the proposed converter, asymmetric PWM scheme is used to control output voltage. The following assumptions are presumed to simplify the circuit analysis. Transformers T1–T5 have the same magnetizing inductances Lm1 = Lm2 = Lm3 = Lm4 = Lm5 = Lm and same turns ratio n = np/ns1 = np/ns2. MOSFETs S1–S4 have the same output capacitances Cr1 = Cr2 = Cr3 = Cr4 = Cr. Voltage across C1 and C2 is equal to Vin/2, and voltage across C3 and C4 equals Vin/2. DC blocking capacitances are C5 = C8 = 2C1 = 2C2 = 2C3 = 2C4 = 2C6 = 2C7 = Cc. Resonant inductances are identical Lr1 = Lr2 = Lr3 = Lr4 = Lr5 = Lr. The output inductances are identical Lo1 = Lo2 = Lo3 = Lo4 = Lo5 = Lo. The main PWM waveforms of the proposed converter are given in Figure 3. The corresponding equivalent circuits for each operation mode are shown in Figure 4. Before time t0, S2 and S4 are in the off-state and diodes D1–D10 are all conducting. 2.3.1. Mode 1 [t0  t1]. Mode 1 begins at t0 when diode currents of D2, D4, D5, D8, and D10 are decreasing to zero. The voltage stresses of S2 and S4 are equal to vC1 + vC2 and vC3 + vC4, respectively. In this mode, vC6 + vC7 = vC1 + vC2. However, vC6 + vC7 = vC3 + vC4 in mode 5. It can be derived that vC1 + vC2 = vC3 + vC4 = vC6 + vC7 = Vin/2 in steady state. Thus, the voltage stresses of S2 and S4 are equal to Vdc/2. Because Lm> > Lr, the output inductor currents iLo1–iLo5 are approximately given as iLo1 ðt Þ ¼ iLo1 ðt 0 Þ þ

 1 t vC1  V o dt; Lo ∫t0 n

iLo2 ðt Þ ¼ iLo2 ðt 0 Þ þ

 1 t vC2  V o dt Lo ∫t0 n

(1)

iLo3 ðt Þ ¼ iLo3 ðt 0 Þ þ

 1 t vC5  V dt; o Lo ∫t0 n

iLo4 ðt Þ ¼ iLo4 ðt 0 Þ þ

 1 t vC7  V dt o Lo ∫t0 n

(2)

  1 t V in =2  vC8  V o dt iLo5 ðt Þ ¼ iLo5 ðt 0 Þ þ ∫ n Lo t 0

(3)

In this mode, the primary side currents iLr1, iLr2, iLr4, and iLr5 increase and iLr3 decreases. Power is transferred from input voltage Vin to output load Ro in this mode.

Figure 3. Key waveforms of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd.

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Figure 4. Operation modes of the proposed converter in a switching cycle: (a) mode 1, (b) mode 2, (c) mode 3, (d) mode 4, (e) mode 5, (f) mode 6, (g) mode 7, and (h) mode 8. Copyright © 2015 John Wiley & Sons, Ltd.

Int. J. Circ. Theor. Appl. 2016; 44:874–892 DOI: 10.1002/cta

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Figure 4. (Continued) Copyright © 2015 John Wiley & Sons, Ltd.

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2.3.2. Mode 2 [t1  t2]. Mode 2 begins at time t1 when S1 and S3 are turned off. In this mode, iLr1(t1) > 0, iLr2(t1) > 0, iLr3(t1) < 0, iLr4(t1) > 0, and iLr5(t1) > 0. Thus, Cr1 and Cr3 are charged and Cr2 and Cr4 are discharged rapidly so that iLr1–iLr5 and iLo1–iLo5 are almost constant in this mode. 2.3.3. Mode 3 [t2  t3]. Mode 3 begins at t2 when vCr1 = vC1 = vC5, vCr2 = vC2 = vC6, vCr3 = vC3 = vC7, and vCr4 = vC4 = vC8. The primary and secondary winding voltages of T1–T5 equal zero voltage. In this mode, D1–D10 are conducting, iD1, iD3, iD6, iD7, and iD9 decrease, and iD2, iD4, iD5, iD8, and iD10 increase. The output inductor voltages vLo1 = vLo2 = vLo3 = vLo4 = vLo5 = Vo and the inductor currents iLo1–iLo5 all decrease. Because iLr1(t2) > 0, iLr2(t2) > 0, iLr3(t2) < 0, iLr4(t2) > 0, and iLr5(t2) > 0, Cr1 and Cr3 are continuously charged and Cr2 and Cr4 are continuously discharged. Cr2 and Cr4 can be discharged to zero voltage at t3 if the energy stored in Lr1–Lr5 is greater than the energy stored in Cr1–Cr4. 2.3.4. Mode 4 [t3  t4]. Mode 4 begins at time t3 when vCr2 = vCr4 = 0, vCr1 = vC1 + vC2, and vCr3 = vC3 + vC4. Because iLr1(t3) > 0, iLr2(t3) > 0, iLr3(t3) < 0, iLr4(t3) > 0, and iLr5(t3) > 0, the anti-parallel diodes of S2 and S4 are conducting. Therefore, S2 and S4 can be turned on at this moment to achieve ZVS. In this mode, rectifier diodes D1–D10 are still conducting. The inductor voltages vLr1 = vC2, vLr2 = vC4, vLr3 = vC1 + vC2  vC5, vLr4 = vC6, vLr5 = vC8, and vLo1 = vLo2 = vLo3 = vLo4 = vLo5 = Vo. Therefore, iLr3 increases, and iLr1, iLr2, iLr4, iLr5, and iLo1–iLo5 all decrease in this mode. 2.3.5. Mode 5 [t4  t5]. Mode 5 begins at time t4 when iD1, iD3, iD6, iD7, and iD9 are decreased to zero ampere. Thus, D1, D3, D6, D7, and D9 are turned off. The voltage stresses of S1 and S3 are equal to vC1 + vC2 and vC3 + vC4, respectively. The voltage across C6 and C7 is equal to vC3 + vC4. Because Lm> > Lr, the output inductor currents iLo1–iLo5 are approximately given as iLo1 ðt Þ ¼ iLo1 ðt 4 Þ þ

  1 t vC2 1 t vC4  V  V ð t Þ ¼ i ð t Þ þ dt; i dt o Lo2 Lo2 4 o Lo ∫t4 n Lo ∫t4 n

   1 t V in =2  vC5 1 t vC6  V o dt; iLo4 ðt Þ ¼ iLo4 ðt 4 Þ þ ∫  V o dt iLo3 ðt Þ ¼ iLo3 ðt 4 Þ þ ∫ n Lo t 4 Lo t4 n

iLo5 ðt Þ ¼ iLo5 ðt 4 Þ þ

 1 t vC8  V o dt ∫ Lo t4 n

(4)

(5)

(6)

In this mode, the primary side currents iLr1, iLr2, iLr4, and iLr5 decrease and iLr3 increases. Power is transferred from input voltage Vin to output load Ro in this mode. 2.3.6. Mode 6 [t5  t6]. Mode 6 starts at time t5 when S2 and S4 are turned off. Because iLr1(t5) < 0, iLr2(t5) < 0, iLr3(t5) > 0, iLr4(t5) < 0, and iLr5(t5) < 0, Cr1 and Cr3 are discharged and Cr2 and Cr4 are charged linearly so that all inductor currents are almost constant in this time interval. 2.3.7. Mode 7 [t6  t7]. Mode 7 starts at time t6 when vCr1 = vC1 = vC5, vCr2 = vC2 = vC6, vCr3 = vC3 = vC7, and vCr4 = vC4 = vC8. Thus, the secondary voltages of T1–T5 are equal to zero voltage so that diodes D1–D10 are conducting, iD1, iD3, iD6, iD7, and iD9 increase, and iD2, iD4, iD5, iD8 and iD10 decrease in this mode. The output inductor voltages vLo1–vLo5 are equal to Vo so that inductor currents iLo1–iLo5 are decreasing. Because iLr1(t6) < 0, iLr2(t6) < 0, iLr3(t6) > 0, iLr4(t6) < 0, and iLr5(t6) < 0, Cr1 and Cr3 are continuously discharged. Cr1 and Cr3 can be discharged to zero voltage if the energy stored in Lr1–Lr5 is greater than the energy stored in Cr1–Cr4. 2.3.8. Mode 8 [t7  t0 + Ts]. Mode 8 starts at time t7 when vCr1 = vCr3 = 0, vCr2 = vC1 + vC2, and vCr4 = vC3 + vC4. Because iLr1(t7) < 0, iLr2(t7) < 0, iLr3(t7) > 0, iLr4(t7) < 0, and iLr5(t7) < 0, the antiparallel diodes of S1 and S3 are conducting. S1 and S3 can be turned on at this moment to achieve ZVS. Because diodes D1–D10 are still conducting, the inductor voltages can be obtained as vLr1 = vC1, vLr2 = vC3, vLr3 = vC5, vLr4 = vC7, vLr5 = vC3 + vC4  vC8 and vLo1 = vLo2 = vLo3 = vLo4 = vLo5 = Vo. Thus, iLr1, iLr2, iLr4, and iLr5 increase and iLr3 and iLo1–iLo5 decrease in this mode. At time t0 + Ts, iD2, iD4, Copyright © 2015 John Wiley & Sons, Ltd.

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A NEW PARALLEL ZVS CONVERTER WITH LESS POWER SWITCHES

iD5, iD8, and iD10 are decreased to zero ampere. Then the circuit operations of the proposed converter in a switching cycle are completed.

3. CONVERTER PERFORMANCE ANALYSIS There are eight operating modes in the proposed converter for every switching cycle. The transfer power from input voltage to output load through five PWM circuits is related to duty cycle of power MOSFETs. Each circuit provides one-fifth of rated output power. The duty cycle of S1 and S3 is δ and the duty cycle of S2 and S4 is 1  δ. In general, the charge/discharge times of Cr1–Cr4 in modes 2, 3, 6, and 7 are less than the time interval in the other modes. To simplify the system analysis in steady state, only modes 1, 4, 5, and 8 are considered in the following. Based on the volt–second balance on (Lr1 and Lm1), (Lr2 and Lm2), (Lr3 and Lm3), (Lr4 and Lm4), and (Lr5 and Lm5) in steady state, the average capacitor voltages VC1–VC8 can be derived as V C1 ¼ V C3 ¼ V C5 ¼ V C7 ¼ ð1  δÞV in =2

(7)

V C2 ¼ V C4 ¼ V C6 ¼ V C8 ¼ δV in =2

(8)

From (7) and (8), it can be obtained that VC1 + VC2 = VC3 + VC4 = VC6 + VC7 = Vin/2. In mode 4, the inductor current variations ΔiLr1–ΔiLr5 are equal to 2Io/(5n). The time interval in mode 4 is given in (9). Δt 34 ¼ t 4  t 3 ≈

2I o Lr 2I o Lr 2I o Lr 2I o Lr 2I o Lr 4I o Lr ¼ ¼ ¼ ¼ ¼ 5nvC2 5nvC4 5nðvC1 þ vC2  vC5 Þ 5nvC6 5nvC8 5nδV in

(9)

In mode 4, S2, S4, and D1–D10 are conducting so that no power is delivered from input voltage to output load. The duty loss in mode 4 is obtained in (10). δloss;4 ¼

Δt 34 4I o Lr f s ¼ Ts 5nδV in

(10)

Similarly, the duty loss in mode 8 can be expressed in (11). δloss;8 ¼

Δt 70 2I o Lr f s 4I o Lr f s ¼ ¼ Ts 5nvC1 5nð1  δÞV in

(11)

In operation mode 1, vLo1 ≈ vC1/n  Vo, vLo2 ≈ vC3/n  Vo, vLo3 ≈ vC5/n  Vo, vLo4 ≈ vC7/n  Vo, and vLo5 = (vC3 + vC4  vC8)/n-Vo. In operation mode 4, vLo1 = vLo2 = vLo3 = vLo4 = vLo5 = Vo. In operation mode 5, vLo1 ≈ vC2/n  Vo, vLo2 ≈ vC4/n  Vo, vLo3 ≈ (vC1 + vC2  vC5)/n  Vo, vLo4 ≈ vC6/n  Vo and vLo5 = vC8/n  Vo. In operation mode 8, vLo1 = vLo2 = vLo3 = vLo4 = vLo5 = Vo. Based on the volt–second balance on Lo1–Lo5, the DC voltage gain of the proposed converter in steady state is obtained in (12). Vo ¼

V in 4Lr I o f s δ ð1  δ Þ   Vf n 5n2

(12)

where Vf is the voltage drop on diode of D1–D10. Applying the current–second balance on capacitances C1–C8, the average magnetizing currents of Lm1–Lm5 can be obtained. I Lm1 ¼ I Lm2 ¼ I Lm4 ¼ I Lm5 ¼ Copyright © 2015 John Wiley & Sons, Ltd.

ð1  2δÞI o 5n

(13)

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I Lm3 ¼

ð2δ  1ÞI o 5n

(14)

The ripple currents on Lm1–Lm5 are illustrated as ΔiLm

  V C1 δ  δloss;8 T s δð1  δÞV in T s  4Lr I o =ð5nÞ ¼ ¼ Lm 2Lm

(15)

The ripple current on Lo1–Lo5 are expressed as 

ΔiLo

V C1 =n  V o  V f ¼ Lo



 δ  δloss;8 T s

h ¼

ð1δÞð12δÞV in 2n

r Iof s þ 4L5n 2

i

 of s δ  5nV4Linr ðI 1δ Þ Ts

Lo

(16)

The average diode currents are expressed as I D1 ¼ I D3 ¼ I D6 ¼ I D7 ¼ I D9 ≈δI o =5

(17)

I D2 ¼ I D4 ¼ I D5 ¼ I D8 ¼ I D10 ≈ð1  δÞI o =5

(18)

The voltage stresses of D1–D6 are expressed as 2V C2 δV in ¼ n n

(19)

2V C1 ð1  δÞV in ¼ n n

(20)

vD1;stress ¼ vD3;stress ¼ vD6;stress ¼ vD7;stress ¼ vD9;stress ≈

vD2;stress ¼ vD4;stress ¼ vD5;stress ¼ vD8;stress ¼ vD10;stress ≈

The root-mean-square (rms) currents of S1–S4 are approximately expressed as iS1;rms ¼ iS3;rms ≈

ð1  δÞI o pffiffiffi δ n

(21)

δI o pffiffiffiffiffiffiffiffiffiffiffi 1δ n

(22)

iS2;rms ¼ iS4;rms ≈

The voltage stresses of S1–S4 are equal to Vin/2. At t1, iLr1–iLr5 are approximately given as iLo1;max ð1  2δÞI o δð1  δÞV in T s  4Lr I o =ð5nÞ iLr1 ðt 1 Þ ¼ iLr2 ðt 1 Þ ¼ iLr4 ðt 1 Þ ¼ iLr5 ðt 1 Þ≈iLm1;max þ ≈ þ n 5n 4Lm   Io ð1  δÞð1  2δÞV in 4Lr I o f s 4Lr I o f s Ts δ  þ þ þ 5n 2n2 5n3 5nV in ð1  δÞ 2Lo (23) Copyright © 2015 John Wiley & Sons, Ltd.

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A NEW PARALLEL ZVS CONVERTER WITH LESS POWER SWITCHES

iLr3 ðt 1 Þ≈iLm3;min 

iLo3;max ð2δ  1ÞI o δð1  δÞV in T s  4Lr I o =ð5nÞ ≈  4Lm n 5n   Io ð1  δÞð1  2δÞV in 4Lr I o f s 4Lr I o f s Ts   þ δ 5n 2n2 5n3 5nV in ð1  δÞ 2Lo

(24)

At t5, iLr1–iLr5 are approximately expressed as iLo1;min ð1  2δÞI o δð1  δÞV in T s  4Lr I o =ð5nÞ iLr1 ðt 5 Þ ¼ iLr2 ðt 5 Þ ¼ iLr4 ðt5 Þ ¼ iLr5 ðt5 Þ≈iLm1;min  ≈  n 5n 4Lm   ð1  δÞð1  2δÞV in 4Lr I o f s Io 4Lr I o f s Ts δ  þ þ 5n 2n2 5n3 5nV in ð1  δÞ 2Lo (25)

iLr3 ðt 5 Þ≈iLm3;max þ

iLo3;min ð2δ  1ÞI o δð1  δÞV in T s  4Lr I o =ð5nÞ ≈ þ n 5n 4Lm   (26) Io ð1  δÞð1  2δÞV in 4Lr I o f s 4Lr I o f s Ts δ  þ  þ 5n 2n2 5n3 5nV in ð1  δÞ 2Lo

Capacitors Cr2 and Cr4 can be discharged to zero voltage if the energy stored in Lr1–Lr5 at time t1 is greater than the energy stored in Cr1–Cr4 in modes 2 and 3. The ZVS condition of S2 and S4 can be given in (27). Lr ≥

2C r ðV in =2Þ2 i2Lr1 ðt 1 Þ

2

þ ½0:5iLr4 ðt 1 Þ þ

i2Lr3 ðt 1 Þ

C r V 2in =2 þ i2Lr4 ðt 1 Þ=4 þ i2Lr3 ðt 1 Þ C r V 2in =2 ¼ 2 iLr2 ðt 1 Þ þ i2Lr4 ðt 1 Þ=4 þ i2Lr5 ðt 1 Þ ¼

i2Lr1 ðt 1 Þ

(27)

Similarly, the ZVS condition of S1 and S3 can be obtained in (28). Lr ≥

2C r ðV in =2Þ2 i2Lr1 ðt 5 Þ

2

þ ½0:5iLr4 ðt 5 Þ þ

i2Lr3 ðt 5 Þ

C r V 2in =2 þ i2Lr4 ðt 5 Þ=4 þ i2Lr3 ðt 5 Þ C r V 2in =2 ¼ 2 iLr2 ðt 5 Þ þ i2Lr4 ðt 5 Þ=4 þ i2Lr5 ðt 5 Þ ¼

i2Lr1 ðt 5 Þ

(28)

Thus, the final ZVS condition of S1–S4 can be obtained in (29).

 C r V 2in =2 C r V 2in =2 Lr ≥ max 2 ; iLr2 ðt 1 Þ þ i2Lr4 ðt 1 Þ=4 þ i2Lr5 ðt 1 Þ i2Lr2 ðt 5 Þ þ i2Lr4 ðt 5 Þ=4 þ i2Lr5 ðt 5 Þ

(29)

4. EXPERIMENTAL VERIFICATION In this section, a design procedure and experimental verification are provided to verify the performance of the proposed converter. A laboratory prototype with 1.92 kW rated power was constructed. The electric specifications of the prototype are Vin = 750–800 V, Vo = 24 V, Io = 80 A, and switching frequency fs = 100 kHz. The assumed maximum duty cycle of S1 and S3 is equal to Copyright © 2015 John Wiley & Sons, Ltd.

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0.4 at Vin,min = 750 V and full load. The maximum duty cycle losses in modes 4 and 8 are assumed 0.15 under full load. δloss;T ¼ δloss;4 þ δloss;8 ¼

4Lr I o; full f s 4Lr Po; full f s ≈  < 0:15 5nV in;min δmax ð1  δmax Þ 5 V in;min δmax ð1  δmax Þ 2

(30)

4.1. Resonant inductances From (30), the necessary resonant inductances of Lr1–Lr5 are given in (31).  2 5 V in;min δmax ð1  δmax Þ ≈32μH Lr ≤ 0:15 4Po;full f s

(31)

Thus, the selected resonant inductances are Lr1 = Lr2 = Lr3 = Lr4 = Lr5 = Lr = 32 μH in this prototype circuit. 4.2. Turns ratio of T1–T5 In (12), the voltage drop Vf is neglected to obtain the turns ratio of T1–T5. The turns ratio of T1–T5 are approximately expressed as

n≈

5δmax ð1  δmax ÞV in;min þ

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 25δ2max ð1  δmax Þ2 V 2min  80V o I o Lr f s  10V o

≈6:1

(32)

The selected primary and secondary winding turns of T1–T5 are np = 61 turns and ns = 10 turns. The magnetizing inductances of T1–T5 are 2 mH. 4.3. Power switches S1–S4 From (12), the duty cycles of S1–S4 at Vin = 750 and 800 V at full load are derived in (33) and (34), respectively.

δ750V;100% ≈

δ800V;100% ≈

1

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 16Lr I o;100% f s o 1  V4nV  5nV in;min in;min 2

1

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 16Lr I o;100% f s o 1  V4nV  5nV in;max in;max 2

≈0:4

(33)

≈0:342

(34)

The rms currents and voltage stresses of S1–S4 are expressed in (35)–(37). 

iS1;rms ¼ iS3;rms

 1  δ800V ;100% I o;100% pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ δ800V;100% ≈ 5A n

iS2;rms ¼ iS4;rms ¼

δ750V;100% I o;100% pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1  δ750V;100% ≈ 4:1A n

V S1;stress ¼ … ¼ V S4;stress ¼ V in;max =2 ¼ 400V Copyright © 2015 John Wiley & Sons, Ltd.

(35)

(36)

(37)

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A NEW PARALLEL ZVS CONVERTER WITH LESS POWER SWITCHES

Power MOSFETs IRFP460 (VDS = 500 V, ID,rms = 20 A, RDS,on = 0.27 Ω, and Coss = 480 pF at 25 V) are adopted for S1–S4. 4.4. Power diodes D1–D10 and capacitances From (17)–(20), the average currents and voltage stresses of D1–D10 are obtained as I D1 ¼ I D3 ¼ I D6 ¼ I D7 ¼ I D9 ≈δ750V;100% I o;100% =5 ¼ 6:4A

(38)

  I D2 ¼ I D4 ¼ I D5 ¼ I D8 ¼ I D10 ≈ 1  δ800V;100% I o;100% =5 ¼ 10:528A

(39)

vD1; stress ¼ vD3; stress ¼ vD6; stress ¼ vD7; stress ¼ vD9; stress ¼

δ750V;100% V in;min ≈49:2V n



vD2;stress ¼ vD4;stress ¼ vD5;stress ¼ vD8;stress ¼ vD10;stress

 1  δ800V;100% V in;max ≈86:3V ¼ n

(40)

(41)

Fast recovery diodes KCU30A30 (VRRM = 300 V and IF = 30 A) are adopted for D1–D10. The selected DC blocking capacitances C1 = …. = C8 = 68 nF and Co = 3000 μF.

Figure 5. Measured pulse-width modulation waveforms of S1–S4 at full load and (a) Vin = 750 V and (b) Vin = 800 V. Copyright © 2015 John Wiley & Sons, Ltd.

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4.5. Output inductances Lo1–Lo5 The ripple current ratio on output inductors Lo1–Lo5 is assumed to be 20%. From (16), the output inductances Lo1–Lo5 are derived in (42). Lo ¼

ð1δ800V ;100% Þð12δ800V;100% ÞV in;max 2n

þ

4Lr I o;100% f s 5n2

0:2I Lo1

! 4Lr I o;100% f s   T s ≈17μH  δ800V;100%  5nV in;max 1  δ800V;100%

(42) The selected output inductances are Lo1 = Lo2 = Lo3 = Lo4 = Lo5 = Lo = 20 μH in this prototype circuit. 4.6. ZVS conditions of S1 and S4 The prototype circuit is designed to have ZVS operation at least from 50% to 100% load at minimum input voltage. The duty cycle at 50% load and minimum input voltage is derived as

δ750V;50% ≈

1

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 16Lr I o;50% f s o 1  V4nV  5nV in;min in;min 2

≈0:32

(43)

The output capacitance Coss of MOSFET IRFP460 at 25 V is 480 pF. The equivalent output capacitance Cr of S1–S4 at Vin = 750 V is approximately equal to

Figure 6. Measured results of gate voltage, drain voltage, and drain current of power switches (a) S1 and S3 at 50% load with Vin = 750 V; (b) S2 and S4 at 50% load with Vin = 750 V; (c) S1 and S3 at 50% load with Vin = 800 V; and (d) S2 and S4 at 50% load with Vin = 800 V. Copyright © 2015 John Wiley & Sons, Ltd.

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A NEW PARALLEL ZVS CONVERTER WITH LESS POWER SWITCHES

4 C r ≈ C oss;25 3

sffiffiffiffiffiffiffiffiffiffi 25 ≈165pF vS1;ds

(44)

From (23)–(26), the inductor currents iLr1(t1)–iLr5(t1) and iLr1(t5)–iLr5(t5) at 50% load and δ50% = 0.32 are obtained in (45) and (46). iLr1;50% ðt 1 Þ ¼ iLr2;50% ðt 1 Þ ¼ iLr3;50% ðt 1 Þ ¼ iLr4;50% ðt 1 Þ ¼ iLr5;50% ðt 1 Þ ð1  2δ50% ÞI o;50% δ50% ð1  δ50% ÞV in;min T s  4Lr I o;50% =ð5nÞ I o;50% þ þ ≈ 5n 5n 4Lm ð1  δ50% Þð1  2δ50% ÞV in;min 4Lr I o;50% f s þ þ 2n2 5n3   4Lr I o;50% f s Ts ≈1:97A δ50%  5nV in;min ð1  δ50% Þ 2Lo

(45)

Figure 7. Measured results of the inductor currents iLr1–iLr5 at full load and (a) Vin = 750 V and (b) Vin = 800 V. Copyright © 2015 John Wiley & Sons, Ltd.

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iLr1;50% ðt 5 Þ ¼ iLr2;50% ðt 5 Þ ¼ iLr3;50% ðt 5 Þ ¼ iLr4;50% ðt 5 Þ ¼ iLr5;50% ðt 5 Þ ð1  2δ50% ÞI o;50% δ50% ð1  δ50% ÞV in;min T s  4Lr I o;50% =ð5nÞ I o;50%   5n 5n 4Lm ð1  δ50% Þð1  2δ50% ÞV in;min 4Lr I o;50% f s þ þ 2n2 5n3   4Lr I o;50% f s Ts ≈  1A δ50%  5nV in;min ð1  δ50% Þ 2Lo



(46)

Figure 8. Measured gate voltage vS1,gs and DC capacitor voltages vC1–vC8 at full load and (a) Vin = 750 V and (b) Vin = 800 V. Copyright © 2015 John Wiley & Sons, Ltd.

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A NEW PARALLEL ZVS CONVERTER WITH LESS POWER SWITCHES

From (29), the necessary resonant inductance to have ZVS turn-on on S1–S4 is obtained as

 C r V 2in =2 C r V 2in =2 ¼ 20:625μH Lr ≥ max 2 ; iLr2 ðt 1 Þ þ i2Lr4 ðt 1 Þ=4 þ i2Lr5 ðt 1 Þ i2Lr2 ðt 5 Þ þ i2Lr4 ðt 5 Þ=4 þ i2Lr5 ðt 5 Þ

(47)

The actual adopted resonant inductor Lr = 32 μH in (31) meets the ZVS condition of S1–S4 at least from 50% to 100% load. A laboratory prototype with the circuit parameters obtained from the design example in the previous section was implemented, and experimental verification is provided in this section. Figure 5 shows the measured PWM waveforms of S1–S4 under different input voltage and full load. S1 and S3 have the same PWM waveforms, and S2 and S4 have the same PWM waveforms. The duty cycle of S1 and S3 at Vin = 750 V condition is greater than the duty cycle at Vin = 800 V condition. The test results of gate voltage, drain voltage, and drain current of S1–S4 at 50% load and different input voltages are illustrated in Figure 6. The drain voltage is decreased to zero before power MOSFET is turned on. Therefore, power MOSFETs S1–S4 are all turned on under ZVS from 50% load. Figure 7 gives the test results of primary inductor currents iLr1–iLr5 at full load and different input voltages. It is clear from Figure 7 that five inductor currents iLr1–iLr5 balanced each other under different input voltages. When S1 and S3 are turned on, iLr1, iLr2, iLr4, and iLr5 increase and iLr3 decreases. On the other hand, iLr1, iLr2, iLr4, and iLr5 decrease and iLr3 increases when S1 and S3 are turned off and S2 and S4 are turned on. Figure 8 shows the measured waveforms of gate voltage and DC blocking capacitor voltages at full load and different input voltages. It is clear that capacitor voltages vC1, vC3, vC5, and vC7

Figure 9. Measured capacitor voltages vCr1 + vCr2, vCr3 + vCr4, and vCr6 + vCr7 at full load and (a) Vin = 750 V and (b) Vin = 800 V. Copyright © 2015 John Wiley & Sons, Ltd.

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are balanced and capacitor voltages vC2, vC4, vC6, and vC8 are balanced well. Figure 9 gives the measured capacitor voltages vCr1 + vCr2, vCr3 + vCr4, and vCr6 + vCr7 at full load with different input voltages. From Figure 9, it is clear that these three voltages are balanced, vCr1 + vCr2 = vCr3 + vCr4 = vCr6 + vCr7 = Vin/2. Figure 10(a) shows the measured gate voltage vS1,gs, diode currents iD1 and iD2, and output inductor current iLo1 at full load and Vin = 750 V. The measured output inductor currents iLo1–iLo5 and the total

Figure 10. Measured the secondary side currents at full load and Vin = 750 V: (a) vS1,gs, iD1, iD2, and iLo1 and (b) iLo1–iLo5 and iLo1 + iLo2 + iLo3 + iLo4 + iLo5.

Figure 11. Measured circuit efficiency of the proposed converter and the conventional parallel three-level converter. Copyright © 2015 John Wiley & Sons, Ltd.

Int. J. Circ. Theor. Appl. 2016; 44:874–892 DOI: 10.1002/cta

A NEW PARALLEL ZVS CONVERTER WITH LESS POWER SWITCHES

891

Figure 12. Measured load current, load voltage, and input split capacitor voltages under load variation between 30 and 80 A.

output inductor current iLo1 + iLo2 + iLo3 + iLo4 + iLo5 at full load are given in Figure 10(b). From the measured results in Figure 10(b), five output inductor currents iLo1–iLo5 are balanced. Figure 11 shows the measured circuit efficiencies of the proposed converter and the conventional three-level parallel converter under the same input voltage and load currents. It is clear that the proposed converter has better circuit efficiency from 50% load to full load. Below the 50% load, the circuit efficiency of the proposed converter is less than the conventional parallel three-level converter due to the larger magnetizing current in the proposed converter. Figure 12 shows the measured the output voltage variation, load current, and input split capacitor voltages under the load current variation between 30 and 80 A. The type 2 voltage controller is adopted to keep the output voltage at the desire voltage level. The gate drivers with the isolated pulse transformers are used to drive the power switches.

5. CONCLUSION A new DC/DC converter with five APWM circuits is presented for medium voltage and high load current applications. The series half-bridge circuits are adopted to limit the voltage stress of MOSFETs at Vin/2. Switching capacitor circuit is used to balance input spilt capacitor voltages. Five APWM circuits with the same power switches are adopted at the primary side to reduce the switch counts. Each circuit provides one-fifth of load power to secondary side so that the current stress of passive components and transformer windings are reduced. Compared with the conventional parallel three-level DC/DC converter, the proposed converter has less power MOSFETs counts. APWM scheme is adopted to generate switching signals of MOSFETs. Based on the resonant behavior by output capacitances of MOSFETs and resonant inductances at the transition interval, all MOSFETs can be turned on at ZVS form 50% load to full load. The system analysis, converter performance, and design example of the proposed converter are discussed in detail. Finally, experimental verifications are provided to verify the effectiveness of the converter. ACKNOWLEDGEMENT

This project is supported by the National Science Council of Taiwan under grant NSC 102-2221-E-224-022MY3. REFERENCES 1. Song BM, McDowell R, Bushnell A, Ennis J. A three-level DC-DC converter with wide-input voltage operations for ship-electric-power-distribution systems. IEEE Transactions on Plasma Science 2004; 32(5):1856–1863. 2. Cheok AD, Kawamoto S, Matsumoto T, Obi H. High power AC/DC and DC/AC inverter for high speed train. In Proceedings of TENCON 2000 (Vol. 1), Kuala Lumpur, 2000; 423–428. Copyright © 2015 John Wiley & Sons, Ltd.

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Copyright © 2015 John Wiley & Sons, Ltd.

Int. J. Circ. Theor. Appl. 2016; 44:874–892 DOI: 10.1002/cta

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