A new SOI monolithic capacitive sensor for ... - Semantic Scholar

Sensors and Actuators A 123–124 (2005) 36–43

A new SOI monolithic capacitive sensor for absolute and differential pressure measurements P.D. Dimitropoulos a,∗ , C. Kachris b , D.P. Karampatzakis b , G.I. Stamoulis b b

a Theon Sensors, MEMS Division, 7 Stratigi Str., 154 51, N. Psychico, Athens, Greece University of Thessaly, Department of Computer and Telecomunications Engineering, 37 Glavani Str. 38221, Volos, Greece

Received 13 September 2004; received in revised form 22 February 2005; accepted 3 March 2005 Available online 28 April 2005

Abstract In the present work, a new monolithic capacitive pressure sensor is being introduced. The sensor is manufactured according to a custom, 15-step SOI process. The process primarily offers great flexibility as far as sensor design is concerned. Absolute or differential pressure sensing is possible by simply arranging proper sensor package. Measurement sensitivity and span are easily regulated over a wide range of values by setting one-single design parameter. Attention is paid to avoid p–n junction formation in order to improve the sensor robustness against temperature increase and allow high-temperature post-processing without doping profile degradation. The presented design allows the implementation of an ordinary p-well CMOS post-process. Sensitivity of 2 mV/kPa, within a span of 180 kPa (2%) and a bandwidth of 25 kHz, is achievable by means of a CMOS switched-capacitor ASIC that is developed and presented here. Significant care has been taken for the ASIC performance to depend as less as possible on CMOS process and transistor-parameter variations that increase due to poor uniformity of the transistor substrate. Moreover, a state-of-the-art design is implemented for the circuit to provide robustness against parasitic capacitances connected in parallel with sensing capacitors. Implementation of additional analog signal processing improves the aforementioned accuracy at a significant extend. The sensors main applications include medical devices such as sphygmomanometers and respirators that require high reliability and biocompatibility. © 2005 Elsevier B.V. All rights reserved. Keywords: Pressure sensor; Capacitive sensor; Monolithic sensor; CMOS

1. Introduction Integrated pressure sensors appeared as commercial products a decade and a half ago and have since then found numerous automotive, aerospace, industrial and biomedical applications [1–4]. The function of the vast majority of such systems is based on the effect of piezoresistivity [5] mainly due to the following facts. Firstly, piezoresistive sensors do not require the formation of sealed cavities to function. This fact simplifies sensor manufacturing at a great extend as well as established bulk and surface micromachining processes ∗

Corresponding author. Tel.: +30 21 06 728610; fax: +30 21 06 728624. E-mail addresses: [email protected], [email protected] (P.D. Dimitropoulos), [email protected] (C. Kachris), [email protected] (D.P. Karampatzakis), [email protected] (G.I. Stamoulis). 0924-4247/$ – see front matter © 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.sna.2005.03.041

can be employed to release elastic silicon diaphragms [6,7]. Secondly, piezoresistors can be developed by means of standard CMOS processes on such silicon diaphragms [8]. However, piezoresistive sensors suffer from serious temperature instability due to (a) the inherit dependence of piezoresistivity coefficients on temperature and (b) mismatch of temperature coefficient of resistance [9–11]. Further drawbacks related with the piezoresistive sensor fundamentals include repeatability errors and high-power consumption. Capacitive pressure sensors overcome such difficulties exhibiting excellent temperature stability, repeatability and ultra-low power consumption [12]. Unfortunately, the development of sealed cavities, incorporating a pair of insulated conductors is required for such sensors to function. Although there is a series of surface micromachining techniques that enable sealed cavity formation, few of them can be effectively

P.D. Dimitropoulos et al. / Sensors and Actuators A 123–124 (2005) 36–43

combined with standard IC manufacturing processes for the development of integrated microsystems [13–16]. In case of CMOS pre-processing, sensor manufacturing must incorporate low-temperature steps only. On the other hand, in case of CMOS post-processing, sensing device must be able to withstand high-temperature manufacturing steps. There are very few processes, where effective mixing of IC and sensor developing steps is possible [17,18]. Anyway, monolithic integration of sensor and IC is almost mandatory, as wire-bond parasitic capacitances evoke errors that are usually higher than the sensor signal itself. In the present work, we present a new integrated pressure sensor made of a pair of SOI wafers according to a 15-step process; SOI technologies do provide significant advantages in surface micromachining [19]. The proposed design allows p-well CMOS post-processing. A switched-capacitor ASIC used for sensor signal conditioning is also presented here. Robust IC design is employed in order to cope with increased transistor-parameter variation, raised by poor substrate uniformity. Sensitivity of 2 mV/kPa, within a pressure span of 180 kPa (2%) and a bandwidth of 25 kHz, is achievable. The presented system (Integrated Sensor & IC) can be employed as it is in absolute and/or differential pressure-sensing applications. Moreover, a slight differentiation of the proposed process-flow permits the development of Touch-Mode capacitive pressure sensors [20] with increased linearity. The presented process-flow that is based on standard IC manufacturing steps as well as the VLSI ASIC have been originally developed by the authors and presented here. System prototypes have been manufactured by XFAB semiconductors in Erfurt, Germany [21].

2. Sensor design and fabrication The sensor is made of two SOI wafers, A and B with custom dimensions, which are wafer bonded and subsequently grinded, etched and polished. Both wafers contain a 3 ␮m thick device layer (DL) that is separated from the bulk (B) by a 0.1 ␮m thick burried SiO2 (BO) layer. The device layers of both wafers are doped (n-type), at the level of 1017 cm−3 , by thermal diffusion and subsequent implantation of P atoms for the upper (UC) and lower (LC) sensing capacitor conductors to be formed. Extensive post-annealing is required, in order to obtain uniformity in the electrical properties of the device layers as the DL layer of wafer B serves as transistor substrate during CMOS post-processing. The BO layers of wafers A and B serve as diffusion barriers that protect doping profiles during high-temperature post-processing steps such as thermal oxidation, wafer bonding and transistor formation. Next, a 1 ␮m thick SiO2 layer (TO) is developed on the surface of wafer A by thermal oxidation. The preparation of wafers A and B is presented in Fig. 1. The sensor cavity is subsequently formed by patterning that thermal oxide (TO) with isotropic wet etching. The cavity, the dimensions of which are regulated according to the

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Fig. 1. Preparation of SOI wafers A and B.

final sensor specifications within the range of 50–250 ␮m, has rectangular shape. Afterwards, the cavity is sealed by wafer bonding of wafers A and B, as presented in Fig. 2. The bulk of wafer B is thinned by polishing and selective wet etching down to its burried oxide layer, which acts as an etch-stop. The BO layer of wafer B is also selectively wet-etched away for the n+ -doped (DL) layer of wafer B to emerge, which serves as the UC of the sensing capacitor and as transistor substrate. The DL of wafer B is further processed by the development of a 3 ␮m deep trench that serves as electrical isolation and diffusion barrier between the UC and the rest of the DL of wafer B. The trench is formed by anisotropic KOH etching of DL layer that extends down to the TO layer, which acts as an etch-stop. Wet anisotropic etching has been chosen instead of anisotropic RIE due to the smoothness of the profile achieved that helps in subsequent lithographic and metallization steps. The major disadvantage of that choice is the increase of lateral trench dimensions that force the overall dye dimensions to enlarge. The TO layer is subsequently etched for the contact (CI) to the lower sensing capacitor to be formed, as shown in Fig. 3. Further dye processing includes anisotropic wet KOH back-etching for the BO layer of wafer A to emerge and second sensing membrane to be formed, as presented in Fig. 3. The BO oxide serves as etch-stop. That membrane serves as an additional pressure input (P-input I) that can be employed in order to sense the pressure in the back side of the dye in case of differential pressure-sensing applications. In this sense, KOH back-etching step is optional depending on further system design. The BO oxide of wafer A is not being removed for two reasons, namely: (a) a protective layer is maintained on the membrane of wafer A and (b) thickness and bowing, due to stress-mismatch of both membranes is kept approximately equal for the pressure-to-capacitance

Fig. 2. Wafers A and B after bonding.

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Fig. 3. The pressure sensor after the process-flow.

conversion sensitivity of both inputs (P-input I and II) to remain the same; on the membrane of wafer B, a protective SiN layer is deposited by PECVD during the last process step. Finally a standard p-well CMOS process is being employed where DL layer of wafer B serves as the transistor n-substrate. Well formation, transistor development, contact PI and PII formation, metallization and passivation follow routine CMOS procedures. However, the uniformity of electrical properties of transistor n-substrate is poor. In order to surpass this difficulty, a special analog ASIC has been developed, the performance of which appears fairly robust against transistor-parameter variations. A 3D solid model of the device is presented in Fig. 4 for clarity. Calibration data for sensors with membrane, as lateral dimensions D × D, where D = 200 ␮m is presented in Fig. 5. Calibration data has been derived by means of extensive Finite Element Modeling by means of CoventorWare tools. The sensitivity of both pressure inputs is approximately equal with SP = ∂C/∂P ≈ 1.32 fF/kPa at P = 100 kPa and D = 200 ␮m and is approximately proportional to SP ∼ D4 , that is in fair agreement with theory [22]. Maximum possible pressure is FSP = 200 kPa at D = 200 ␮m. Further pressure increase forces membranes to touch. The analog ASIC is designed in a way to provide protection against short circuits of this kind. In a process, alternative (TO) oxide with 0.1 ␮m thickness is deposited onto DL layer of wafer B and is not patterned. The thickness of TO layer of wafer A is reduced to 0.5 ␮m. The latter TO layer is patterned to form sensor cavity as described previously. In this way, a Touch Mode capacitive pressure sensor is being developed that exhibits increased linearity and immunity in hash environments.

Fig. 4. A 3D model of the pressure sensor: vertical cut.

Fig. 5. Calibration data for sensor with rectangular membrane where D = 200 ␮m: (a) capacitance change vs. pressure applied at P-input I and II and (b) deflection of input I and II membranes. Data has been derived by extensive FEM modeling by means of CoventorWare Tools.

3. Analog signal processing ASIC In the present project, one of the toughest issue to cope with has been the design of the analog ASIC intended to be post-manufactured by means of a standard p-well CMOS process where DL layer of wafer B serves as the transistor n-substrate. The ASIC meets a series of important specifications that allow its function along with the sensing capacitors, namely: (a) it must enable differential and/or absolute pressure-sensing capabilities and provide with short-circuit protection in case of over pressure, (b) it should consume the lowest possible power in order to enable wireless sensing applications; for this low-voltage design is mandatory, (c) it must provide with temperature immunity over the extended range of −50 to +150 ◦ C, (d) it should employ as less transistors as possible in order to reduce overall dye dimensions, (e) it must compensate for parasitic capacitances connected in parallel with sensing capacitors; the parasitic capacitances can evoke errors as large as the sensor signal and (f) its performance must depend as less as possible on transistor-parameter variations raised due to poor electricalproperty uniformity of transistor substrate. The sensor signal is sampled and pre-amplified by the switched-capacitor CMOS ASIC that is presented in


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Fig. 6. The pre-amplification ASIC stage.

Fig. 6. The ASIC is based on a CMOS charge-transfer amplifier connected in common-gate configuration in order to take advantage of the low-impedance input “seen” in the source terminal of the MOS transistors [23]. The transistor dimensions are equal and play minor role in the ASIC performance as long as their aspect ratio is kept higher than W/L ≥ 1; the aspect ratio employed in the design is 0.5. The ASIC contains 20 CMOS switches consisting of a pair of complementary transistors as presented in Fig. 7. Complementary design is important as switch charge-injection [24] may raise important error. The switches are controlled by two non-overlapping, two-phase clock signals, namely: (a) CP1 and (b) CP2. The even and odd phases of these signals are denoted with the addition of letter E and O, respectively. The switching phase sequence is presented in Table 1. For differential pressure-sensing applications, capacitor C4 is manufactured as shown in Fig. 8(a); it is sensitive in pressure applied on both dye sides (P-input I and II). Capacitors C2 and C3 are manufactured as presented in Fig. 8(b); they are sensitive in pressure applied on the upper sensor side

(P-input II). Capacitors C1 and C5 –C8 are manufactured as shown in Fig. 8(c); they are insensitive in applied pressure. For absolute sensing applications, capacitor C4 is also manufactured as presented in Fig. 8(c). In Fig. 8, contacts and trenches are omitted for simplicity. All capacitors have the same zero-pressure capacitance that is C0 ≈ 5 pF. Capacitors C7 and C8 and the four corresponding switches form a

Fig. 7. Switch.


40 Table 1 Switching sequence Phase

CP1E

CP1O

CP2E

CP2O

Action

0 1 2

OFF OFF ON

ON ON OFF

ON OFF OFF

OFF ON ON

Capacitors C1 –C6 are reset Capacitors C1 –C4 are pre-charged Capacitors C5 –C6 are charged

Sample & Hold circuit that is connected to a pair of analog current conveyors [25] that are presented elsewhere [26]. Significant care has been taken during current conveyor design, in order to maximize its dynamic range in case of low-voltage applications. Positive and negative supply voltage, denoted, respectively, with VDD and VSS are set at −VSS = VDD = 1.6 V. The transistor gate terminals are connected to the analog ground. In this way, the transistors function approximately as switches that are controlled by their source-terminal voltage. PMOS transistors are on as long as their source-terminal voltage is higher than VSP ≥ VTP where VTP denotes their threshold voltage. Similarly, NMOS transistors are on as long as VSN ≤ −VTN . During phase 0, capacitors C1 –C6 are reset, meaning that their charge is set at the value of Ci VDD . During phase 1, capacitors C1 –C4 are pre-charged. The MOS transistors conduct current that pre-charges capacitors C1 –C4 until the voltage at PMOS and NMOS source-terminals becomes VTP and −VTN , respectively. The current required to pre-charge the capacitors, during phase 1 is fed through transistor drain-terminals to analog ground. At the end of phase 2, capacitors C1 –C6 are fully charged. The voltage of their conductors connected to PMOS and NMOS source-terminals remains at VTP and −VTN , respectively, whereas the voltage of their conductors connected to power supplies becomes VDD and VSS , respectively. During phase 2, transistor drainterminals are connected to C5 and C6 capacitors. In this way,

charges Q5 and Q6 are pumped, respectively, to these capacitors forcing their voltage, denoted respectively with V5 and V6 , to rise. Q1 (nTs ) = C0 VDD Q2 (nTs ) = (C0 + C2 (nTs ))VDD Q3 (nTs ) = (C0 + C3 (nTs ))(−VSS ) = (C0 + C3 (nTs ))VDD Q4 (nTs ) = (C0 + C4 (nTs ))(−VSS ) = (C0 + C4 (nTs ))VDD Q5 (nTs ) = Q1 (nTs ) − Q3 (nTs ) = −C3 (nTs )VDD Q6 (nTs ) = Q2 (nTs ) − Q4 (nTs ) = (C2 (nTs ) − C4 (nTs ))VDD

(1a)

(1b) (1c)

Q5 (nTs ) 2C0 Q6 (nTs ) V6 (nTs ) = 2C0

(2a)

1 Q5 (nTs ) V7 ((n − 1)Ts ) + 2 2C0 1 Q6 (nTs ) V8 (nTs ) = V8 ((n − 1)Ts ) + 2 2C0

(2b)

V5 (nTs ) =

V7 (nTs ) =

1 V0 ((n − 1)Ts ) 2 C4 (nTs ) − C2 (nTs ) − C3 (nTs ) VDD + 2C0

V0 (nTs ) = V7 (nTs ) − V8 (nTs ) =

(2c)

Fig. 8. Capacitors C1 –C4 .

Charges, Qi (t) and voltages, Vi (t) are calculated in Eqs. (1) and (2), respectively, where the index denotes the corresponding capacitor. Voltages V7 and V8 subtraction is performed by the current conveyors. The ASIC output signal V0 (t) is a discrete-time pulse amplitude modulated (PAM) waveform at frequency fs = 1/Ts = 50 kHz that is the sensor sampling rate and the frequency of CP1 and CP2 clock signals. Capacitance change C2 and C3 depends on pressure PII , applied on the upper side of the chip (P-input II), whereas capacitance change C4 depends on pressure PI + PII , applied on both chip sides (P-input I and II). Eq. (2) shows that the Sample & Hold sub-circuit (capacitors C7 and C8 ) combined with capacitors C5 and C6 form a discrete-time low-pass filter with cut-off frequency fLP = 0.5 fs = 25 kHz. This filter determines the bandwidth of the system. Typical system output is presented in Fig. 9. The curve denoted with positive pressure is derived for C2 = C3 = C4 = C (100 kPa) ≈100 fF that corresponds to PI = 100 kPa and PII = 0 kPa. The negative


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Fig. 9. Typical sensor response. Data has been derived by means of Cadence Analog Artist EDA tools.

Fig. 10. ASIC output vs. capacitance change. Data has been derived by means of Cadence Analog Artist EDA tools.

pressure curve is derived for C2 = C3 = 0 and C4 = C (100 kPa) that corresponds to PI = 0 kPa and PII = 100 kPa. Finally, the differential pressure curve is derived for C2 = C3 = C (100 kPa) and C4 = 2C (100 kPa) that corresponds to PI = PII = 100 kPa. System response versus capacitance change C(P) is presented in Fig. 10. Data in Figs. 9 and 10 have been derived by means of Cadence Analog Artist EDA tools. Points between C (0 kPa) ≈ 0 fF and C (100 kPa) ≈ 100 fF have been tested. Curves denoted with positive pressure, negative pressure and differential pressure correspond to pressure applied on P-input I, II and both inputs as in Fig. 9. The response V0 (C) is linear with sensitivity SV = ∂V0 /∂C = 1.53 mV/fF. The result is in fair agreement with (2). According to the previous result, the overall system sensitivity can be calculated as S = SP SV ≈2 mV/kPa. The system voltage span, FSV , is limited by the corresponding current-conveyor span at the level of FSV = ±450 mV at −VSS = VDD = 1.6 V (or

|V7 |, |V8 | < 450 mV) that corresponds to pressure span of approximately FS = ±180 kPa (or |PI |,|PII | < 180 kPa). System consumption is measured to be P = 15 ␮W at −VSS = VDD = 1.6 V. Temperature variation for Ci = 0 is presented in Fig. 11. Data in Fig. 11 has been derived by means of Cadence Analog Artist EDA tools Temperature error is significantly smaller than the error evoked by system noise. System actual layout is presented in Fig. 12. The fact that the four MOS transistors work basically as switches, controlled by their source-terminal voltage, increases the system immunity against process variations. The only critical NMOS and PMOS device-parameter is the threshold voltage, VTN and VTP , respectively. Due to the fact that transistor source-terminal voltage is kept constant during phase 1 and 2, when charge pumping occurs, provides compensation for parasitic capacitances connected between source-terminals and analog ground. The whole ASIC design is symmetric (balanced) in order: (a) to enable

Fig. 11. Temperature variation for PI = PII = 0. Data has been derived by means of Cadence Analog Artist EDA tools.

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Fig. 12. Actual system layout.

differential pressure sensing and to compensate for, (b) transistor threshold-voltage variations, (c) transistor mobility and dimension mismatches, (d) switch charge-injection and (e) temperature variation. Two additional inputs named VOFF+ and VOFF– are included in the ASIC for offset and parameter-mismatch regulation. 4. Conclusion A custom SOI process has been presented for the fabrication of capacitive sensors for absolute or differential pressure measurements. Due to the absence of p–n parasitic junctions, the sensor enables extended temperature working range. The insertion of diffusion barriers along with the low-doping level allows CMOS IC post-processing on the remaining DL layer of wafer B. A switched-capacitor ASIC used for sensor signal conditioning has also been developed. Robust IC design has been employed in order to compensate for increased transistor-parameter variation, raised by poor substrate uniformity. Sensitivity of 2 mV/kPa, within a pressure span of 180 kPa (2%) and a bandwidth of 25 kHz, is achievable. The proposed design shows excellent temperature and offset stability. The presented system (Integrated Sensor & IC) can be employed as it is in absolute and/or differential pressuresensing applications. Both process-flow and VLSI ASIC have been originally developed by the authors and presented here. System prototypes have been manufactured by XFAB semiconductors in Erfurt, Germany.

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Biographies Panos D. Dimitropoulos was born in 1973 in Athens, Greece. He received his BS, MS and PhD degrees by the National Technical University of Athens (NTUA) in electrical and computer engineering in 1997, 1999 and 2002, respectively. Since March 2003, he has been working

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with THEON Sensors s.a. as senior engineer on microsystem design and development. He is currently leading a project for the development of monolithic mechanical sensors on silicon. Since January 2003, he has been adjunct professor with the Department of Computer and Telecommunications Engineering of the University of Thessaly, teaching basic and advanced Analog CMOS VLSI circuit design. His current research interests include magnetic and mechanical microelectronic sensor design and development, VLSI circuit design for analog and mixed-mode sensorsignal processing and system modeling. He has been involved in numerous research projects for microsystem development and has been the author of 15 publications in the field of microelectronic sensors, system modeling, signal processing and VLSI circuit design. Christopher Kachris was born in Athens, Greece in 1978. He received his BS and his MS from the Electronic and Computer Engineer Department, Technical University of Crete in 2001 and 2003, respectively. From 2003 to 2004, he worked in Ellemedia Technologies developing network processors for broadband networks. Currently, he is towards the PhD degree in the University of Thessaly. His interests include reconfigurable logic, network processors and wireless sensor networks. Dimitris P. Karampatzakis was born in Drama, Greece in 1978. He received his BS from the Electronic and Computer Engineer Department, Technical University of Crete in 2002.Currently, he is towards the PhD degree in the University of Thessaly. His interests include low power CAD tools, power grid analysis and optimization, transistor level power analysis and optimization and VLSI design verification. George I. Satamoulis graduated with a PhD from the University of Illinois at Urbana-Champaign in 1994. He was a visiting assistant professor at the University of Iowa until 1995 when he joined Intel Corp. where he worked on power estimation and power reduction for the Pentium III, Pentium 4, Itanium and Pentium M processors. In 2001, he became an assistant professor at the Technical University of Crete. Since 2003, he is an associate professor at the Department of Computer and Communications Engineering of the University of Thessaly.