A New Technique to Measure the Jitter - Semantic Scholar

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Abstract1. In this paper we present a new process to measure the jitter of a telecommunication system. To understand better the new proposed technique we ...
A New Technique to Measure the Jitter António D. Reis1,2, José F. Rocha1, Atílio S. Gameiro1, José P. Carvalho2 1

Dep. de Electrónica e Telecomunicações / Instituto de Telecomunicações, Universidade de Aveiro, 3810 Aveiro, Portugal 2 Dep. de Fisica, Universidade da Beira Interior Covilhã, 6200 Covilhã, Portugal

Abstract1 In this paper we present a new process to measure the jitter of a telecommunication system. To understand better the new proposed technique we show others classical measurer systems. The obtained results are coherent with the well known theoretical formula of the analog PLL based on an ideal multiplier and also with the practical results obtained experimentally. I. INTRODUCTION To test the new technique proposed we used the setup of Fig.1. We need an electronic circuit for which the theoretical formulas are well known. Thus we can compare the results measured by the new technique with the ones theoretical 2 2 obtained by the formula σφ =NoBl/A and experimentally. We can also compare the results measured by this new process with the ones experimentally obtained by others classical measurers. Thus we compared this results with the experimental ones obtained by [1] for the analog PLL.

The output can be expressed in terms of the inputs by the following equation y(t) = x(t) . z(t) = √2Acos(w1t+φ1) . √2Bcos(w1t+φ2) = ABsin2w1t + ABsin(φ1-φ2) The term of high frequency will be eliminated by the low pass filter and then we have y(t) = ABsin(φ1-φ2) considering φ2=0 we have y(t) = ABsinφ1 Thus we can see that there is no linear zone, however for little phase variations we can consider sinφ1≅φ1 and then y(t) = ABφ1 then the slope at the origin is dy(t)/dt=AB It is necessary a filter, although no critical, with a cutoff frequency low enough to eliminate the high frequency but at same time sufficiently high to do not distort the more fast phase variations of the jitter. However there isn’t ideal filters. We can observe that this method has a reduced linear zone and its output dynamic range is no linear and no monotone, as result we only can measure jitter of low amplitudes. If the input signals are not sinusoidal other harmonics must be taken in account.

B. Exor and filter

Fig.1 Setup to measure the jitter

The jitter measurer of Fig.3 is based on a Exor gate which detects the phase difference between the two inputs

The setup shown above permits to obtain the synchronizer jitter curve as function of the input noise. II. JITTER MEASURER TYPES

A. Ideal multiplier and filter The jitter measurer of Fig.2 multiplies two sinusoidal input signals producing an output signal with two terms. The first term possess a frequency and phase equal to the sum of the inputs, whereas the second term possess a frequency and a phase equal to the difference of the two inputs. Also the amplitude of the two output terms is equal to the middle of the product of the input amplitudes.

Fig.2 Multiplier

1’2

UA - UBI

Fig.3 Exor Thus we can see a linear zone in its all dynamic range but monotone only in π radians. As result we only can measurer jitter with lower amplitudes than π radians, where the linear zone is monotone. For calibration the characteristic curve is V=(1/π)φ then the inverse will be φ=πV φ=180V.

C. RS flip flop and filter The jitter measurer of Fig.4 is based on a RS flip-flop which detects the phase difference between the two inputs.

Fig.4 RS flip flop

This circuit has a monotone linear zone in its all dynamic range of 2π radians. Thus the monotone zone is equal to the dynamic range. As result we can measure the jitter with amplitudes of 2π radians. This circuit can be calibrated easily observing the output variation (maximum and minimum values) over 2π. This slope is constant in all dynamic range. This circuit is almost ideal since its linear zone is monotone in all its dynamic range, however there is no ideal filter and then the high frequency can not be totally eliminated by the filter nor the jitter can pass through the filter without any attenuation. Fig.5 shows that there is some spectral components of the high term that lays in the bandwidth of the filter which can false the results being measured as jitter.

Fig.5 There is significant spectral lines at low frequency

E. New proposed RS flip flop with converter The jitter measurer of Fig.8 is based on a RS flip flop which detects the phase difference between the two inputs then a sampling and holder converts the detected phase variation in amplitude variation which is the jitter histogram.

Fig.8 RS flip flop with converter This method has a monotone linear zone in its all dynamic range. So we can measurer jitter amplitudes of 2π radians. This jitter measurer is easily calibrated due to its linearity and monotony as the flip flop RS. The new proposed jitter measurer has a sampling and hold circuit that functions as an ideal filter eliminating completely the high frequency error pulse without attenuating the jitter. Fig.9 illustrates the operation of the jitter measurer based on a RS flip flop with a converter of phase in amplitude.

We can reduce the spectral power inside the band pass of the filter diminishing the duty cycle of the pulse error as happen with the two D flip flops with reset.

D. Two D flip flops with AND gate and filter The jitter measurer of Fig.6 is based on two flip flops with reset which detects the phase difference between the two inputs. The monotone zone is equal to the dynamic range of 4π radians.

Fig.6 Two D flip flops with reset This circuit presents an error signal with low duty cycle and consequently a great quantity of energize at high frequencies which can be easily eliminated by the filter. Fig.7 shows as the diminution of the duty cycle increases the spectral energize in the high frequencies of the error pulse.

Fig.7 There is shift of spectral lines for high frequencies For calibration the flip flop characteristic curve is V=(1/2π)φ then the inverse will be φ=2πV φ=360V. This equation is valid for the flip flop RS and for the two D flip flops with reset.

Fig.9 Waveforms at the RS flip flop with converter The jitter histogram is then sampled and posteriorly processed by an appropriate program giving the average, the variance of the jitter, the jitter standard deviation UIRMS and the jitter standard deviation peak to peak UIPP. We used sequences of 10000 bits but only the last 9000 are processed. -3 The sampling period of 10 implies a ratio of 1000 samples per bit but only one from 100 to 100 is processed. The program, which process the jitter histogram, was initially written in C language and after in MATLAB. s=size(y); n=s(1); m=mean(y) b=y-m; c=sumsqr(b); vv2=c/n; vr2=vv2*4*pi^2 dpr=sqrt(vr2); dpui=dpr/(2*pi) dpv=sqrt(vv2); TP=1; dpu=dpv/TP; A=max(y); B=min(y); dpuipp=abs(A-B)/TP; This program has a general application, particularly in the presented classical measurer types.

III. TESTS AND RESULTS

C. Loop parameters dimensioning

A. The well known circuit based on a PLL To test our new jitter measurer we used the well known analog PLL of Fig.10, this phase comparator is based on an ideal multiplier. This circuit was used as reference since its 2 2 theoretical formula σφ =NoBl/A is well known and there is also credible experimental results to compare with our results obtained by the new jitter measurer.

The synchronizer will operate in the linear regime, so the output jitter must be small enough to allow that linear operation of the loop. This analog PLL will be the reference for posterior comparisons with others synchronizers. For this comparisons all the loops must be designed to give identical linearized transfer functions. Almost all parameters are pre-fixed, one exception is the amplification factor Ka which acts on the root locus controlling the desired characteristics of the loop. Now we will present the 1st and 2 order loop dimensioning for the analog Phase Lock Loop. In both cases we consider a normalized operation frequency fo=1Hz, an external noise bandwidth Bn=5Hz and a loop noise bandwidth Bl=0.02Hz. nd

Fig.10 Analog Phase Lock Loop This Phase Lock Loop (PLL) has a phase comparator Kf, an amplification factor Ka, a loop filter F(s) and a Voltage Controlled Oscillator (VCO) Ko.

B. Sampling and precision The continuous signals in the time need previously to be sampled before to be processed digitally by a computer. Fig.11 illustrates this sampling process showing as the spectral noise density No can be related with the noise standard deviation σn and the sampling period ∆τ.

Fig.11 Sampling process The spectral power density No/2 is the power inside 1Hz. 2 Fig.12 relates No with the variance σn and with the sampling period ∆τ. Considering a constant source of No/2 passing through a bandwidth filter of 1/2∆τ. So the power inside 1Hz 2 2 (No/2) will be σn multiplied by ∆τ which gives No=2∆τσn .

Fig.12 Illustration of the power spectral density Fig.13 shows the relation between No and σn which depends on the considered case: unilateral or bilateral.

Fig.13 Unilateral and bilateral cases (factor 2) 2

The spectral noise density is D(w)=No=2∆τσn for unilateral 2 2 case and D(w)=No/2=σn ∆τ for bilateral case -> No=2∆τσn . 2 2 We consider the bilateral case and σφ =NoBl/A = 2 2 2∆τσn Bl/A for the following dimensioning.

- 1st order loop st

In the 1 order loop the filter F(s) does not influence the loop characteristics, but only eliminates the high frequency perturbation terms produced by the phase detector. So F(s)=0.5Hz is 25 times higher than Bl=0.02Hz. In this loop the transfer function is G( s ) KdKo (1) = H(s) = 1 + G ( s ) s + KdKo and the loop noise bandwidth is KfKo KdKo = 0.02Hz (2) Bl = = Ka 4 4 For the analog synchronizer Km=1, A=B=1/2, Ko=2π, then 2 KmABKo =0.02Hz --> Ka = 0.08 Ka (3) 4 π

- 2nd order loop 1 + sT 2 is sT 1 sKdKo( T 2 / T1) + KdKo / T1 (4) H(s) = s + sKdKo( T 2 / T1) + KdKo / T1 sA + B = 2 (5) s + s2ξWn + Wn 2 and the loop noise bandwidth is ξWn  1  Bl = (6) 1 + 2  4ξ 2  Taking (ξ=1, Bl=0.02 and Kd=1/2π) and solving the above equations we obtain for F(s) 1 + s63 F(s) = (7) s977 So we have 2 1 --> Ka = (8) Kd=KaKf= Ka(1)(1 / 2)(1 / 2) = 2π π This dimensioning process utilized here can be generalized for others synchronizers. The transfer function with F(s) =

D. Results Tab.1 shows the output jitter variance Vrs2 and standard deviation dpui2 as function of the input noise standard deviation σn. Others intermediate inputs can be considered and so the output jitter can also be expressed as function of one of the intermediate inputs. Tab.1 Output jitter versus input noise standard deviation

IV. CONCLUSIONS We tested the well known analog PLL with the new jitter measurer. For low noise quantities the circuit operates in the linear mode for which it was designed and then the jitter behavior is 2 2 described by the theoretical formula σφ =NoBl/A . Thus the results measured by the new proposed technique is according with the theoretical and experimental results. For higher noise quantities the circuit can no more be considered in the linear mode then the above theoretical formula is only one approach. Thus the results measured by the new process are identical to the ones obtained experimentally by Rosenkranz [1] but there is some difference with the ones obtained theoretically. We saw that the results measured by the new technique are identical to the experimental ones for low and high noise quantities. Then we conclude that the new proposed technique can measure the jitter correctly and credibly since its result is coherent with the theoretical and experimental ones. V. ACKNOWLEDGMENTS The first author, Antonio D. Reis is thankful to the program PRODEP for financial support. VI. REFERENCES [1] – Werner Rosenkranz, “Phase Locked Loops with limiter phase detectors in the presence of noise”, IEEE Transactions on Communications com-30. October 1982.

Fig.14 illustrates graphically the jitter variance measured by the new technique as a function of the jitter variance given by 2 2 the theoretical formula σφ =NoBl/A .

Fig.14 Simulated RMS jitter versus theoretical RMS jitter The graphic shows that for input theoretical jitter quantities Vrt20.1 the results measured by the new technique are only identical to the experimental results obtained by Rosenkranz [1] but begins to be slightly different from the theoretical ones.