A New Topology of Cascaded Multilevel Converters ... - IEEE Xplore

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

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A New Topology of Cascaded Multilevel Converters With Reduced Number of Components for High-Voltage Applications Javad Ebrahimi, Student Member, IEEE, Ebrahim Babaei, Member, IEEE, and Goverg B. Gharehpetian, Senior Member, IEEE

Abstract—In this paper, a new topology of a cascaded multilevel converter is proposed. The proposed topology is based on a cascaded connection of single-phase submultilevel converter units and full-bridge converters. Compared to the conventional multilevel converter, the number of dc voltage sources, switches, installation area, and converter cost is significantly reduced as the number of voltage steps increases. In order to calculate the magnitudes of the required dc voltage sources, three methods are proposed. Then, the structure of the proposed topology is optimized in order to utilize a minimum number of switches and dc voltage sources, and produce a high number of output voltage steps. The operation and performance of the proposed multilevel converter is verified by simulation results and compared with experimental results of a single-phase 49-level converter, too. Index Terms—Full-bridge topology and high-voltage application, multilevel converter, power conversion, submultilevel converter.

I. INTRODUCTION ULTILEVEL converters have been introduced as static high-power converters for medium- to high-voltage applications such as large electric drives, dynamic voltage restorers, reactive power compensations, and FACTS devices [1]–[5]. The multilevel converters synthesize a desired stepped output voltage waveform by the proper arrangement of the power semiconductor devices from several lower dc voltage sources. The main advantage of multilevel converters is the use of mature medium power semiconductor devices, which operate at reduced voltages. As a result, the switching losses and voltage stress on power electronic devices are reduced. Also, the output voltage has small voltage steps, which results in good power quality, low-harmonic components, and better electromagnetic compatibility. Multilevel converters have obtained more and more attention in recent years and new topologies with a wide

M

Manuscript received December 9, 2010; revised March 5, 2011; accepted March 28, 2011. Date of current version November 18, 2011. This work was supported by the Iran Renewable Energy Organization (SUNA). Recommended for publication by Associate Editor B. Wu. J. Ebrahimi and G. B. Gharehpetian are with the Electrical Engineering Department, Amirkabir University of Technology, Tehran 15914, Iran (e-mail: [email protected]; [email protected]). E. Babaei is with the Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz 51664, Iran ([email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2011.2148177

variety of control strategies have been developed [6]–[9]. There are three different basic multilevel converter topologies: neutral point clamped (NPC) or diode clamped [10], flying capacitor (FC) or capacitor clamped [11], and cascaded H-bridge (CHB) [12]. The main drawback of the NPC topology is unequal voltage sharing between the series connected capacitors, which leads to dc-link capacitor unbalancing and requires a great number of clamping diodes for a high number of voltage levels [6]. Also, the maximum voltage across the switches is closest to the switching node. Therefore, the three-level NPC converter has been commercialized in industry as a standard topology. The FC multilevel converter, and its derivative, the stacked multilevel (SM) converter [13] and [14], use flying capacitors as clamping devices. These topologies have several attractive properties compared to NPC converters, including the advantage of transformerless operation and have redundant phase leg states that allow the switching stresses to be equally distributed among semiconductor switches [15] and [16]. But, these converters require an excessive number of storage capacitors for a high number of voltage steps. A double FC multicell converter has been presented in [17]. This topology has been implemented by adding two low-frequency switches to the conventional configuration of the FC multilevel converter. The main advantages of the presented converter, in comparison with the FC multilevel and SM converters, are the doubling of the rms value of the output voltage and the number of output voltage steps and the canceling of the midpoint of the dc source. But two additional switches must operate at the peak of the output voltage. This restricts high-voltage applications of this converter. The CHB topologies are a good solution for high-voltage applications due to the modularity and the simplicity of control. But, in these topologies, a large number of separated voltage sources are required to supply each conversion cell. To reduce the number of separate dc voltage sources for high-voltage applications, new configurations have also been presented; however, a capacitor-voltage balancing algorithm is required [18] and [19]. Multilevel converters have some particular disadvantages. They need a large number of power semiconductor switches, which increase the cost and control complexity and tend to reduce the overall reliability and efficiency. Although low-voltagerated switches can be utilized in a multilevel converter, each switch requires a related gate driver and protection circuit. This may cause the overall system to be more expensive and complex.

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The researchers have strived in [20] to introduce a new topology for multilevel converters with a reduced number of components compared to conventional multilevel converters. This topology consists of series connected submultilevel converter blocks. In order to create the output voltage with a constant number of steps, there are different structures with different number of components. Therefore, the converter structure can be optimized for various objectives. This increases the design flexibility. But, the converter needs a large numbers of bidirectional switches and the blocking voltage of bidirectional switches is also high. To overcome aforementioned disadvantages, a new topology with reduced number of switches and dc voltage sources has been presented in [21]. Also, the structures based on similar concepts have been presented in [22]. In these topologies, the dc source is formed by connecting a number of half-bridge submodules. The main drawback of these topologies is the utilization of unidirectional switches, which operate at high output voltage in single-phase applications. Also, the design flexibility is lost in these topologies. As mentioned, the presented topologies in [20] and [21] utilize switches, which operate at the peak of the output voltage. Therefore, a bulky and costly interface transformer needs to be used for high-voltage applications. This paper proposes a new modular and simple topology for cascaded multilevel converters that produces a large number of steps with a low number of power switches and components. Three different procedures for calculating required magnitudes of dc voltage sources are proposed. In addition, the structure of the proposed topology is optimized for various aims. A comparison analysis with two recently presented topologies is also provided. Finally, a design example of the proposed multilevel converter is included.

Fig. 1. of v o .

(a) Proposed submultilevel topology and (b) typical output waveforms

TABLE I VALUES OF v o FOR DIFFERENT STATES OF THE SWITCHES

II. PROPOSED TOPOLOGY Fig. 1 shows the proposed topology for a submultilevel converter, which consists of the basic unit and a full-bridge converter. The basic unit consists of n dc voltage sources. Each dc voltage source is connected to the output by two switches and can produce a zero or positive polarity voltage. As shown in Fig. 1, each switch is composed of an insulated gate bipolar transistor (IGBT) with an antiparallel diode. Both switches, Si and S¯i (for i = 1, 2, . . . , n), are complementary controlled on the entire operation cycle. The basic unit produces a staircase voltage waveform with positive polarity. The output voltage of the basic unit can be equal to each dc voltage source or binary, ternary, . . . , or n’nary combinations of the dc voltage sources. Therefore, the maximum number of output voltage steps for vo is equal to 2n − 1. The output side of the basic unit is connected to a single-phase full-bridge converter, which alternates the input voltage polarity and provides a positive or negative staircase waveform at the output. The full-bridge switches, T1 , T¯1 , T2 , and T¯2 , are also complementary controlled. The typical output waveforms of vo and vo are shown in Fig. 1(b). Table I gives the values of voltages vo and vo for different states of the switches S1 , S2 , . . . , Sn , T1 , and T2 . For simplicity, the on-state

voltage drops of the switches have been neglected. As can be seen, 2n +1 − 1 different values can be obtained for vo . It can be mentioned that there are different switching states to generate the zero-voltage level at the output voltage. In Table I, one state is presented. The proposed multilevel converter topology is constituted by a cascade connection of submultilevel converters as shown in Fig. 2. The structure of the first, second, . . . and kth basic unit have 2n1 , 2n2 , . . . , and 2nk switches, respectively. The

EBRAHIMI et al.: NEW TOPOLOGY OF CASCADED MULTILEVEL CONVERTERS

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are presented. To produce a specific number of output steps, the number of dc voltage sources is decreased from the first- to the third proposed method. But, the variety of magnitudes of dc voltage sources is increased. This is one of the important problems for asymmetric structures of multilevel converters. It is noticeable that for all proposed methods, any number of output voltage steps (even and odd) can be produced. A. First Proposed Method In this method, all the dc voltage sources in each unit are equal. The first dc voltage source V11 is considered as the base value for the per-unit system as follows: Vbase = V11 = Vdc . Fig. 2.

Proposed multilevel converter topology.

full-bridge converters provide positive or negative stepped voltage waveforms between the output terminals. The overall output voltage of the proposed cascaded multilevel converter is the sum of output voltages of the submultilevel converters as follows: vo = vo1 + vo2 + · · · + vok .

(1)

The different output voltage levels can be determined by combinations of switching states of each unit. If proper values for the dc voltage sources are selected, then the output i voltage of Vij ) and the converter can be obtained between (− ki=1 nj =1 k n i (+ i=1 j =1 Vij ). If the number of dc voltage sources in basic units is considered equal to 1, then there is no need for switches in basic units. In this state, the dc voltage source is directly connected to the full-bridge converter. In other words, this topology is equivalent to the CHB converter. Although the latter topology requires multiple dc sources, but these may be suitable for the cases, which have possible combination of photovoltaic panels, fuel cells, or energy storage devices, such as capacitors or batteries. When ac voltage is available, multiple dc sources can be generated using isolated transformers and rectifiers [20]. It is important to mention that this topology requires less dc voltage sources considering variety and number compared to topologies presented in [20] and [21]. This is a great advantage in practice, as it will be shown in the following sections.

Then, the normalized values of the dc voltage sources for producing all steps in the output must be chosen using the following procedure: For unit 1: V1i = V11 = Vdc ,

To provide a large number of output steps without increasing the number of inverters, asymmetric structures can be used. In [23] and [24], dc voltage sources in conventional cascaded multilevel inverters have been proposed to be chosen according to a geometric progression with a factor of 2 or 3. In fact, a proper choice of voltage asymmetry among cells can produce a different combination of voltage levels and eliminate redundancies. For the proposed topology, in order to have unequal values for vo and produce linear steps, three different methods for the determination of magnitudes of the dc voltage sources

i = 2, . . . , n1 .

(3)

For unit 2: V2i = V21 = V11 + 2

n1

V1j = (2n1 + 1)Vdc , i = 2, . . . , n2 .

j =1

(4) For unit 3: V3i = V31 = V11 + 2

n1

V1j + 2

j =1

n2

V2j

j =1

= (2n1 + 1)(2n2 + 1)Vdc ,

i = 2, . . . , n3 .

(5)

i = 2, . . . , nm .

(6)

In general, for the mth unit: Vm i = Vm 1 = V11 + 2

nj m −1

Vj l

j =1 l=1

=

m −1

(2nj + 1)Vdc ,

j =1

The maximum output voltage Vo m ax is obtained as follows: Vo m ax =

ni k i=1 j =1

III. DETERMINATION OF THE MAGNITUDES OF THE DC VOLTAGE SOURCES

(2)

Vij =

k

(ni × Vi1 ).

(7)

i=1

The number of output voltage steps can be determined by the following equation: Nstep,1 =

k

(2ni + 1)

i=1

= (2n1 + 1) × (2n2 + 1) × · · · × (2nk + 1).

(8)

B. Second Proposed Method In the second method, the normalized values of dc voltage sources in each unit of the proposed topology are proposed to be chosen according to the following procedure:

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For unit 1: V11 = Vdc

(9)

V1i = 2V11 = 2Vdc ,

i = 2, . . . , n1 .

(10)

For unit 2: V21 = V11 + 2

n1

V1i = (4n1 − 1)Vdc

(11)

A. Optimal Structure for Maximum Number of Voltage Steps With Constant Number of Switches

(12)

The desirable objective in a multilevel converter is to obtain the maximum number of steps for minimum number of switches. If the number of switches Nswitch is constant in the proposed topology, then, the maximum number of output voltage step should be determined. Suppose that the proposed topology consists of a series of k submultilevel converters and each of these has ni dc voltage sources (i = 1, 2, . . . , k), then, we have

i=1

V2i = 2V21 = 2(4n1 − 1)Vdc ,

i = 2, . . . , n2 .

In general, for the mth unit: Vm 1 = V11 + 2

ni m −1

Vij =

i=1 j =1

Vm i = 2 Vm 1 = 2

m −1

m −1

(4ni − 1)Vdc

(13)

i=1

(4nj − 1)Vdc ,

i = 2, . . . , nm . (14)

j =1

Nswitch = 2(n1 + n2 + · · · + nk ) + 4k.

The maximum output voltage is obtained as follows: Vo m ax =

ni k

Vij =

i=1 j =1

k

[(2 ni − 1) × Vi1 ].

(15)

i=1

The number of generated steps in the output voltage is expressed by the following equation: Nstep,2 =

k

(4ni − 1).

k=

Vij =

i=1 j =1 i−1

Vm i = 2

Vm 1 ,

(2n i +1 − 1)Vdc

(17)

i=1

i = 2, . . . , nm .

Vo m ax =

Vij =

i=1 j =1

k

The value of n must be determined. Considering (8), (16), (20), and (22), the maximum number of voltage steps with three methods can be, respectively, calculated as follows: Nstep,1 = (2n + 1)k Nstep,2 = (4n − 1)k (24)

Considering (23) and (24), it is clear that we have Nstep,1 = [(2n + 1)1/(2n +4) ]N s w i t c h

[(2n i − 1) × Vi1 ].

(19)

i=1

k

(23)

(18)

The number of output voltage steps can be determined by the following equation: Nstep,3 =

Nswitch . 2n + 4

Nstep,3 = (2n +1 − 1)k .

The peak value of the output voltage is obtained as follows: ni k

(22)

From (21) and (22), it is clear that we have

The third method for the determination of magnitudes of dc voltage sources is in binary fashion in each unit, which results in an exponential increase in the number of overall output steps. For the mth unit, the dc voltage sources are determined according to the following equation: Vm 1 = V11 + 2

To determine the dc voltage sources for three proposed methods, the numbers of voltage steps are given by (8), (16), and (20). Considering these equations and (21), the product of the numbers (whose summation is constant) will be maximized, when the following equation is valid: n1 = n2 = · · · = nk = n.

C. Third Proposed Method

m −1

(21)

(16)

i=1

ni m −1

the number of submultilevel converters and components can be chosen in order to obtain an optimal structure for each special objective. This leads to the reduction in the cost, weight, and installation area of the converter. In this section, these optimal structures are investigated.

(2n i +1 − 1)

(20)

i=1

IV. OPTIMAL STRUCTURES In the proposed topology, there are different submultilevels arrangements for a specified number of dc voltage sources to obtain different number of steps at the output voltage and utilizing a different number of switches. It is worthwhile to notice that

Nstep,2 = [(4n − 1)1/(2n +4) ]N s w i t c h Nstep,3 = [(2n +1 − 1)1/(2n +4) ]N s w i t c h .

(25)

Fig. 3 shows the variation of (2n + 1)1/(2n +4) , (4n − 1)1/(2n +4) , and (2n +1 − 1)1/(2n +4) versus n. It is evident that the maximum number of voltage steps for the first and second methods is obtained for n = 2. This means that a structure consisting of two dc voltage sources (i.e., four switches) in each basic unit can provide maximum step voltages for vo with a minimum numbers of switches. For the third method, the maximum is theoretically obtained for n = ∞. This means that a structure consisting of one basic unit with available switches is desirable for a constant number of switches.


Fig. 3. Variation of (2n + 1)1 / (2 n + 4 ) , (4n − 1)1 / (2 n + 4 ) , and (2 n + 1 − 1)1 / (2 n + 4 ) versus n.

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Fig. 5. Variation of (2n + 4)/ ln(2n + 1), (2n + 4)/ ln(4n − 1), and (2n + 4)/ ln(2n + 1 − 1) versus n.

voltage source provides a maximum number of voltage steps for vo with a minimum number of dc sources. It is necessary to note that the proposed topology is basically a conventional cascaded multilevel converter. C. Optimal Structure for Minimum Number of Switches With Constant Number of Voltage Steps Fig. 4. n.

Variation of (2n +

1)1 / n ,

(4n

− 1)1 / n ,

and

(2 n + 1

− 1)1 / n

versus

It is clear that the number of components should be integer. Therefore, if the result is not an integer number, then it should be automatically rounded off to the nearest integer number. B. Optimal Structure for Maximum Number of Voltage Steps With Constant Number of dc Voltage Sources The next objective is expressed as follows. Suppose that the number of dc voltage sources is constant and equal to Nsource . Find a topology, which provides the maximum number of voltage steps. Suppose that the proposed topology consists of a series of k submultilevel converters. Each of these consists of ni dc voltage sources (for i = 1, 2, . . . , k). Thus Nsource =

k

ni = n1 + n2 + · · · + nk .

(26)

i=1

Considering (21), the number of dc voltage sources can be written as follows: Nsource = n × k.

(27)

Using (24), the maximum number of voltage steps will be determined as follows: Nstep,1 = [(2n + 1)1/n ]N s o u r c e Nstep,2 = [(4n − 1)1/n ]N s o u r c e Nstep,3 = [(2n +1 − 1)1/n ]N s o u r c e .

(28)

Fig. 4 shows the variation of (2n + 1)1/n , (4n − 1)1/n , and − 1)1/n versus n. It is clear that the maximum number (2 of voltage steps for first, second, and third methods are obtained for n = 1. Thus, a structure consisting of units with one dc n +1

Suppose that Nstep is the number of voltage steps considered for voltage vo . In this case, the topology, which can produce Nstep steps with the minimum number of switches, should be determined. With respect to Section IV-A, it is evident that the maximum number of voltage steps is obtained for equal number of switches in the basic units. Thus, if the number of switches in each unit is assumed to be equal ton, then considering (21), (22), and (24), the total numbers of switches Nswitch with the three methods, can be, respectively, obtained as follows: Nswitch, 1 = (2n + 4)k = ln(Nstep ) ×

(2n + 4) ln(2n + 1)

Nswitch, 2 = (2n + 4)k = ln(Nstep ) ×

(2n + 4) ln(4n − 1)

Nswitch, 3 = (2n + 4)k = ln(Nstep ) ×

(2n + 4) . ln(2n +1 − 1)

(29)

Fig. 5 shows the variation of (2n+4)/ln(2n+1), (2n + 4)/ ln(4n − 1), and (2n + 4)/ln(2n +1 − 1) versus n. It is clear that the numbers of switches for a constant Nstep will be minimized at the minimum point of these figures. Therefore, n = 2 results in the minimum number of switches, to realize Nstep values for the first and the second methods. For the third method, the optimal value is theoretically obtained for n = ∞. V. COMPARISON OF THE PROPOSED TOPOLOGY WITH OTHER TOPOLOGIES In this section, the proposed topology is compared with two other topologies recommended in [20] and [21]. The first comparison index is the number of IGBTs. It is important to note that the presented topology in [20] has been used bidirectional switches that are composed of two IGBTs. But in the proposed topology of this paper and [21], the switches are composed of one IGBT. Therefore, to compare the different topologies, the numbers of IGBTs (instead of switches) are used in this paper.

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Fig. 7. Blocking voltages on switches to realize N ste p -step voltage in proposed topology and those presented in [20] and [21].

(30) can be considered as a criterion for comparison of different topologies considering the maximum voltage on switches [20]. A lower value indicates that a smaller voltage is applied to the terminal of switches, which is considered as an advantage. With respect to Fig. 2, the following equations can be obtained: Vswitch,u ,j = 2

n

Vj i ,

j = 1, . . . , k.

(31)

i=1

Therefore, the peak voltage of switches of the basic unit can be written as follows: Vswitch,U = 2

n k

Vj i = Vdc × (Nstep − 1).

(32)

j =1 i=1

The peak voltage of switches in the jth full-bridge converter can be calculated as follows: Fig. 6. Number of IGBTs to realizeN ste p -steps voltage by proposed topology using: (a) first; (b) second; and (c) third methods in comparison with topologies presented in [20] and [21].

It is noticeable that the number of IGBTs and the antiparallel diodes are the same. Fig. 6 compares the number of IGBTs NIGBT versus the number of output voltage steps Nstep for three methods of determination of dc voltage sources in the topology recommended in this paper and topologies presented in [20] and [21]. It is obvious that the proposed topology needs fewer IGBTs to realize Nstep steps for vo . The second comparison index is the blocking voltages on switches. The voltage and current ratings of switches in a multilevel converter play an important role in the cost and realization of the multilevel converter. In all topologies, currents of all switches are equal to the rated current of the load. This is, however, not the case for the voltage. Suppose that the peak voltage of switches Vswitch is represented by the following equation: Vswitch = Vswitch,U + Vswitch,B =

k j =1

Vswitch,u ,j +

k

Vswitch,b,j

(30)

j =1

where Vswitch ,U and Vswitch, B are the peak voltage of units and full-bridges switches, respectively. Also, Vswitch, u , j and Vswitch, b, j represent the peak voltage of switches in the jth basic unit and jth full-bridge converter, respectively. Therefore,

Vswitch,b,j = 2 ×

n

Vj i ,

j = 1, . . . , k.

(33)

i=1

Therefore, the peak voltage of switches of full-bridge converters can be obtained as follows: Vswitch,B =

k

Vswitch,b,j = Vdc × (Nstep − 1).

(34)

j =1

Considering (32) and (34), (30) can be rewritten as follows: Vswitch = 2Vdc × (Nstep − 1),

Nstep ≥ 2.

(35)

Fig. 7 compares the normalized blocking voltages on switches to realize Nstep -step voltage by the proposed topology and those presented in [20] and [21]. It is clear that the blocking voltage on switches in the proposed topology is less than that recommended in [20] for realizing Nstep -step voltage for vo . It should be noted that the proposed topology utilize multiple cascaded fullbridges in the output side of the converter while the presented topology in [20] and [21] utilize one full-bridge in the output side. According to (34), the overall peak voltage of the fullbridge converters in the proposed topology is equal to those presented in [20] and [21]. But, in topologies presented in [20] and [21], this voltage is related to only one full-bridge converter. This leads to restriction on the high-voltage applications. The last comparison index is the losses of switches. In the proposed topology, for half cycle, the antiparallel diodes and IGBTs of ON-switches are conduct for ϕ radian and (π − ϕ)


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Fig. 8. Normalized switching losses of the proposed topology and that presented in [21] versus N ste p -step voltage.

radian, respectively. ϕ is the power factor angle. The total conduction losses of the switches are calculated as follows: 2 2 Rd Im (2ϕ − sin(2ϕ)) Pcond = k(n + 2) Vd Im (1 − cos ϕ) + π 4 π β +1 β +1 +VT Im (1 + cos ϕ) + RT Im sin (ωt) dωt ϕ

(36) where Im is the peak value of the output current. VT and Vd are the threshold voltages of IGBTs and diodes, respectively. RT and Rd are the equivalent resistances of voltage drop across the IGBTs and diodes, respectively. β is a constant and depends on the used IGBTs. At a particular temperature, the semiconductor specifications from the manufacturer can be used to approximate semiconductor losses. For specified switches, the conduction losses depend on the load current and power factor. The total switching losses in the proposed topology can be obtained as follows: Vdc I f (tON + tOFF ) (37) Psw = (k + n)(2n + 1)k −1 3 where tON and tOFF are the rise and the fall times of the switches. Fig. 8 shows the normalized switching losses versus the number of output voltage steps for proposed topology. For calculation of losses, it is assuming the IGBTs and the diodes in both topologies are the same. This comparison shows that the proposed topology has less switching losses than [21]. The switching losses of topology presented in [20] depend on the utilized snubber circuit in switches. Therefore, this topology is not in this comparison. VI. DESIGN OF MULTILEVEL CONVERTER BASED ON PROPOSED TOPOLOGY This section outlines the design procedure of a multilevel converter based on the proposed topology and those recommended in [20] and [21]. The converter is a single-phase multilevel converter with a minimum of 45 voltage steps and a peak value of 240 V. In this design, the magnitudes of dc voltage sources are determined by the second proposed method. It should be noted that on-state voltage drops of switches have been neglected. The optimal multilevel structure for the minimum number of used switches based on the proposed topology (see Sections II–III) is

Fig. 9. Optimal multilevel structure with minimum number of used switches based on (a) proposed topology, (b) topology presented in [20] and (c) topology presented in [21].

presented in Fig. 9(a). As can be seen in this figure, the number of IGBTs and dc voltage sources are 16 and 4, respectively. In this design, the converter is able to generate 49 steps in the output voltage. The structure of the optimal multilevel converter with the minimum number of used switches designed based on the topology presented in [20] is shown in Fig. 9(b). This topology requires bidirectional switches with the capability of blocking voltage and conducting current in both directions. The bidirectional switch arrangement, which consists of two common emitter IGBTs and two antiparallel diodes has been used for this topology. It is noticeable that in the full-bridge circuit, similar to other two topologies, unidirectional switches are used. In this structure, the number of IGBTs and dc voltage sources are 22 and 6, respectively, and the number of voltage steps is 53. If this design is accomplished based on the topology presented in [21], 28 switches with 12 dc voltage sources should be used, as been shown in Fig. 9(c). In this converter, the number of voltage steps is 47. The blocking voltage on all of switches in Fig. 9(a), (b), and (c) are 960, 1674.4, and 956.8 V, respectively. It is worth to note that the sum of the blocking voltages on full-bridges switches for all topologies is almost the same and equal to 480 V. But, in the proposed topology, the blocking voltage on switches in each full-bridge converter is near to the maximum output voltage of adjoining units. On the other hand, the blocking voltage in [20] and [21] is near to the maximum output voltage of the converter. This problem restricts the multilevel converter for high-voltage applications.

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Fig. 12. Fig. 10.

THD of the output voltage waveform versus N ste p step.

Photo of prototype. TABLE II ON SWITCHES LOOK-UP TABLE

Fig. 11.

Control block diagram.

VII. SIMULATION AND MEASUREMENT RESULTS To study the performance of the proposed multilevel converter, shown in Fig. 9(a), a single-phase 49-level prototype has been modeled and built. The PSCAD/EMTDC software has been used for simulations. Each switch is an antiparallel connection of an IGBT and a diode. The IGBTs used for the prototype are BUP306D with internal antiparallel diodes with voltage and current ratings equal to 1200 V and 20 A, respectively. The 89C52 microcontroller by ATMEL Company has been used to generate the switching pattern. The required dc voltage sources have been provided by cascaded connections of dc power supplies. Fig. 10 shows a photo of the prototype. There are several modulation techniques for multilevel converters [25]–[28]. In this paper, the fundamental frequencyswitching technique has been used. Fig. 11 shows the control block diagram of the converter. The main objective of the control system is the synthesis of the output voltage with minimum error with respect to the reference voltage. It is important to note that the calculation of the optimal switching angles for selective harmonics elimination or minimization of total harmonic distortion (THD) is not the objective of this paper. The THD of the sinusoidal stepped waveform is defined as follows:

∞

2 n =3,5,... Vo,n Vo,rm s = −1 (38) THD = Vo,1 Vo,1

where Vo,n is the rms of the n order component of the output voltage. Vo,rm s and Vo,1 being the rms values of the output voltage and the fundamental of the output voltage, respectively. The values of Vo,rm s and Vo,1 are calculated using the following equation, respectively: ⎞2 ⎛ √ ∞ Nstep 2 2Vdc ⎝ cos(nαi ) ⎠ (39) Vo,rm s = π n n =1 i=1 Vo,1 =

√ Nstep 2 2Vdc cos(αi ) π i=1

(40)

where the parameters α1 , α2 . . . αN s t e p are switching angles and given by the following equation:

i − 0.5 i = 1, 2, . . . , Nstep . αi = arcsin Nstep Fig. 12 shows the relation between the voltage step and the THD. Table II shows the ON switches look-up table for different voltage levels (steps). This converter is able to generate all even and odd voltage steps (from −24 to 24 pu for 10-V base). As an example, the following voltage waveform should be generated: ⎧ ⎪ ⎨100 cos(100πt) + 80 cos(300πt), 0 ≤ t < 20 ms 20 ≤ t < 40 ms vo (t) = 120 + 60 cos(100πt), ⎪ ⎩ −160 sin(100πt), 40 ≤ t < 60 ms.


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Fig. 13. Output voltage waveforms: (a) simulation and (b) measurement (Time/div = 10 ms).

Fig. 13 shows the simulated and measured output voltage waveforms. As can be seen, the proposed converter can generate desired voltage waveforms. In order to investigate waveforms of output voltages produced by different basic units and submultilevel converters and the output current, the converter has been designed and adjusted to generate a 50 Hz, 29-level sinusoidal waveform. The test has been performed on an R–L load (with R = 107 Ω and L = 55 mH). Considering the high number of voltage levels and due to limitations of available dc voltage sources in the laboratory, the amplitude of prototype dc voltage source of lower unit is small. Therefore, conduction losses of IGBTs are near to the amplitude of dc voltage sources. To avoid large distortions, voltages of the experimental prototype are measured on no-load condition. Fig. 14 shows simulation and measurement results. The results have a good agreement with each other. There is a small difference between the amplitudes of the simulation and experimental results due to the voltage drops on switches of the prototype. As shown in Fig. 14, the output voltage of each basic unit has always zero or a positive value. The ac outputs of full-bridge converter have been connected in series such that the synthesized voltage waveform is the sum of outputs of fullbridge converters. Considering the output voltage and current waveforms, it is obvious that there is a phase difference between the output voltage and current waveform, which is due to the inductive characteristic of the load. As can be seen in these waveforms, the output current has a low THD, meaning near sinusoidal waveform. Since the load of the converter is almost a low pass filter (R–L), the output current contains less high order harmonics than the output voltage. For this case, THDs of the output voltage and current based on simulations are 1.742% and 0.417%, respectively. To generate a desired output with high power quality, the number of voltage steps should be increased or other switching technique should be applied to the converter.

VIII. CONCLUSION A new configuration for multilevel converter has been proposed, which is based on the cascaded connection of submultilevel converters. The suggested structure extends the design flexibility and possibilities to optimize it for various objectives. The proposed topology has been optimized in this paper for utilizing a minimum number of switches and voltage sources. A

Fig. 14. Simulation (left figure) and measurement (right figure) results (Time/div = 5 ms) and (Voltage/div = 10 V): (a) output voltage of the first basic unit; (b) output voltage of the second basic unit; (c) output voltage of the first submultilevel converter; (d) output voltage of the second submultilevel converter; and (e) top and bottom: converter output voltage and current.

comparison among the proposed converter and other topologies has been provided. It is shown that the proposed topology, not only has lower number of switches and components, compared to other topologies, but also the full-bridge converters operate at a lower voltage. This extends the applications of the proposed converter for high voltages. The operation and performance of the proposed topology has been simulated and experimentally verified on a single-phase

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Javad Ebrahimi (S’10) was born in Isfahan, Iran, in 1986. He received the B.Sc. degree in electrical engineering from the University of Tabriz, Tabriz, Iran, in 2008, and the M.S. degree in electrical engineering from the Amirkabir University of Technology (AUT), Tehran, Iran, in 2010, graduating with first class honors, where he is currently working toward the Ph.D. degree at Electrical Engineering Department. His current research interests include the analysis and control of power electronic converters, multilevel converters, FACTS devices, and distributed generation.

Ebrahim Babaei (M’10) was born in Ahar, Iran, in 1970. He received the B.S. degree in electronics engineering and the M.S. degree in electrical engineering both from the Department of Engineering, University of Tabriz, Tabriz, Iran, in 1992 and 2001, respectively, graduating with first class honors. He received the Ph.D. degree in electrical engineering from the Department of Electrical and Computer Engineering, University of Tabriz, in 2007. In 2004, he joined the Faculty of Electrical and Computer Engineering, University of Tabriz, where he has been an Assistant Professor since 2007. He is the author of more than 80 journal and conference papers. His current research interests include the analysis and control of power electronic converters, matrix converters and multilevel converters, FACTS devices, and power system dynamics.

Gevorg B. Gharehpetian (M’00–SM’08) was born in Tehran, Iran, in 1962. He received the B.S. and M.S. degrees in electrical engineering in 1987 and 1989 from Tabriz University, Tabriz, Iran, and the Amirkabir University of Technology (AUT), Tehran, respectively, graduating with first class honors. He received the Ph.D. degree in electrical engineering from Tehran University, Tehran, in 1996. In 1989, he was with the Electrical Engineering Department, AUT, as a Lecturer. He was with High Voltage Institute of RWTH Aachen, Aachen, Germany. He was an Assistant Professor position in AUT from 1997 to 2003, was holding the position of an Associate Professor from 2004 to 2007, and has been a Professor since 2007. He is the author of more than 400 journal and conference papers. His teaching and research interests include power system and transformers transients, FACTS devices, and HVdc transmission. Dr. Gharehpetian was selected by the Ministry of Higher Education as the Distinguished Professor of Iran in 2008 and was awarded the National Prize. As a Ph.D. student, he has received scholarship from DAAD (German Academic Exchange Service) from 1993 to 1996.