applications for =Parate delay-line components, since it carsbe integrated directly into. LSI or VLSI components implemented in eomimon MOS technologies.
IEEE
JOURNAL
OF SOLID-STATE
CIRCUITS,
VOL.
SC-20,
NO.
6, DECEMBER
1265
1985
A Novel Precision MOS Synchronous Delay Line MEL
&vtract common SDL is
— A novel delay
synchronous
delay line (SDL)
lines
which are implemented hnplernentedin MOS. Thus the SDL
is deseribed.
BAZES
Unlike
in hybrid technologies, the obviates the need in certain
applications for =Parate delay-line components, since it carsbe integrated directly into LSI or VLSI components implemented in eomimon MOS technologies.
The SDL
Dl?AM
controller,
DR!AM
control
reference. makes
variations.
The number
analysis
the system
that is intrinsic
pulses for
as a delay
to the SDL
design also
temperature,
and processing
and the delays they provide
experimentally,
are
a linear relationship clock. This
as was tbe low sensitivity
and voltage-supply parameters
tbe
clock
A delay analysis predicts
was confirmed the circuit
tkigger
by the taps and tbe input reference
to temperature
defines
utilizes
of taps on the SDL
the delays provided
of the SDL
precision
to supply-voltage,
design limits.
relationship
SDL
feedback
insensitive
for the first time in A commercial
it provided
The
negative
within
between Iitmar
signals.
tie
it very
arbitrary
was implemented
in which
variations.
that determine
A closed-loop
stable and optimum
operation.
do not occur at appropriate titnes. In such cases, it too would be necessary to create new timing edges at the appropriate lines.
times through
The delay circuits timing
be highly
precise
ponents
T
mands
together
of integrated-circuit
to create complex
precise specifications
logic
of the timing
corm
systems de-
relationships
of
the signals flowing between the cotiponents. In order to meet these specifications, a central clock is generally required in the system in order to provide a common timing reference for all of the components in the system. The clock
causes the triggering
ponents
and,
of output
at some later
time,
signals in some com-
causes the sampling
of
those signals in other components. Since there
are only
period,
it is impossible
trigger,
within
tial output between
the often
gether
in a system
The most comtnon
implement
precision
edges within
of lumped
fabricated
technologies,
This
circuit paper
NMOS
in common
non-hybrid
at the
Rather,
system
level
triggering
relationship of more than
two such output signals within a single clock period, it is necessary to create additional timing edges from the refer-
integrated-
the delay lines in
the
form
of
describes in
or CMOS.
a novel
common
precision
MOS
delay
line
for
technologies,
such
Siflce the delay line does not require
as any
special circuit components beyond those readily implementable @ MOS technologies, it may be implemented directly as a self-contained circuit function in an integrated MOS circuit. It thereby obviates the need for special delay-line
circuit
in practice intervals
sigi-tals which have a precise timing
delay
components.
implementation
voltage,
signal
to-
used to
inductor-capacitor
such as MOS.
be provided
separate
to
use a clock
technology
components and bipolar input and output buffers [1]. Since hybrid technologies must’ be used to fabricate such delay lines, the delay lines cannot be integrated into LSI or VLSI
more than two sequen-
to directly
a single clock period,
one clock
stringent
interconnected
delay lines for use in logic systems is a
combination
components
in many system applicatiotis.
The delay line is capable of generating
two clock
them. In order to perform
signals must, in general,
to meet
of the components
must INTERCONNECTION
THE
output
order
requirements
circuit
INTRODUCTION
in
timing
hybrid
& delay
or delay lines used to create additional
edges for triggering
components I.
the use of delay circuits
limited,
with
number
precision
temperature,
The delay troller
LSI
chipsl
MOS
[2], in which
though
edges at arbitrary
and with low sensitivity and processing
line is presently
manufactured
an arbitra~,
of timing
to supply-
variations.
in use in two commercially
dynamic
RAM
(DRAM)
the delay line provides
contiming
ence clock signal. These timing edges are created by delaying, through the use of a delay circuit, one of the edges of
edges at precise times for triggering the DRAM control signals. The precision with which the delay line provides timing
the reference
edges
more additional would
clock by a precise length timing
take the form
tap would time from
provide
of time.
edges are required,
of a tapped a timing
If two or
the delay circuit
delay line, in which
edge delayed
the clock edge at the input
each
by a specified
to the delay line.
In certain cases, the problem may not be that timing edges are lacking, but rather that the existing timing edges Manuscript received January 8, 1985; revised July 9, 1985. The author is with Intel Israel Ltd., Haifa 31015, Israel.
0018-9200/85
for
the
DRAkf
must
DRAM
access time,
providing
adeqwtte
production-testing
the delay line in the generation signals in the DRAM controllers
while
be adequate
to
at the
same time
margins.
The role of
of the DRAM control is illustrated in Fig. 1.
Two pulses are provided by the delay line for triggering the DRAM control signals. First, RAS is triggered off of the falling edge of the system clock. After a precise delay time, 1Intel 8207 and 8208.
/1200-1265
controllers
minimize
$01.00
01985
IEEE
1266
IEEE
SYSTEM CLOCK
JOURNAL
OF SOLID-STATE
VOL.
SC-20,
NO.
6, DECEMBER
1985
/////
///!/
/////
CIRCUITS,
FIRsT SOL PuLSS
SECONO SDL PULSE
/
\ ‘RCD
– ---+ I
tRA”-d
I
i=-
r ROW ~
COLUMN
I
tAsr+
ROW
x
bl-k
> CR~, the constant simplifies to Tp(CcTRL/CRA ).
phases. The sampled
amplification. Each circuit samples from the VCDL on alternate clock
outputs
are then low-pass
filtered
and
fed back to the VCDL as VCTRL. The low-pass filtering necessary for stable closed-loop operation of the SDL.
is
(3), the effective
If the total
B. Circuit
the clock
P&
is sampled
operates
goes high. Then
as follows.
Say Tz goes low and ql
the NOR gates in the VCDL
begin switch-
ing, in the following order and in the indicated N~l-low, N~l —high, N~2 —low, N~2 —high; N~3 —high,
N~4 —low,
and Ndd —high.
directions: NA3 —low,
When ql goes low
and Tz goes high, the voltage present at that instant on N~4 is sampled and held on capacitor C~~, after being amplified
in the network
N~(~ and transistors volt age on
composed
of NOR gates N~ ~ and
Q~l and Q~2. Immediately
Nk ~ is sampled
and held
after
on capacitor
the CR~,
capacitor c~~ is connected to capacitor CCTRL through pass transistor Q~3. The sampled voltage is thereby low-pass filtered to produce Vc~RL. A precise calculation of the filter made with the filter, figure
the aid of the z-transform which
equals
is illustrated
C~~ /(C~,
time constant equivalent
in Fig. 3. The factor
+ CCTRL). From
may be circuit
of
B in the
the illustration,
period
and held thereby
increase.
of the filter
the VCDL
is seen to time
is significantly
TP, then a voltage
slightly
( Vcc is nominally
used to implement
gins increasing,
Operation
The SDL
delay through
than
technology
time constant
the SDL).
less
less than
5 V in the
VCTRL then be-
causing the total delay through
When
the
total
delay
through
the
VCDL
to
VCDL voltage
becomes approximately equal to TP, the sampled begins decreasing. VCTRL then begins leveling off
the
until a steady-state value is reached which maintains the total delay at approximately TP. Similarly, if the total delay through period
than
the clock
TP, then a voltage equal to V~~ is sampled
the VCDL
is significantly
greater
and held.
VCTRL then begins decreasing, thereby causing the total delay through the VCDL to decrease. When the total delay through
the VCDL
becomes
approximately
equal
to TP,
the sampled voltage goes above V~~. VCTRL then begins leveling off until a steady-state value is reached which maintains the total delay at approximately TP. Thus the total delay through the VCDL is maintained through negative feedback at approximately TP. The negative feedback also greatly reduces the SDL sensitivity to variations in supply total
voltage,
temperature,
delay through
the VCDL
and processing, remains
so that
relatively
the
constant
1268
with
IEEE
a high
degree of precision,
even for commercial
re-
JOURNAL
OF SOLID-STATE
Substituting
CIRCUITS,
VOL.
SC-20,
NO.
6, DECEMBER
1985
(4) into (6) yields
quirements. Simultaneously
with the sampling
operation
,$,;
on capacitor
C~~ with Q2 going high, the NOR gates in the VCDL
begin T OUT
switching in the following order and in the indicated directions: N~l —low, N~l —high, N~2 —low, N~z —high, N~3 —low, N~3 —high, N~4 —low, and N~4 —high. On this clock phase, the sampling operation is performed on capacitor CR ~, after being amplified by NOR gates N~5 and
Another appearing
N~6 and transistors
included
Q~l and Q~2. When
cpz goes low and
=~(TP-TE),
,
,gl
z=1,2,.
o., N.
(7)
$
correction must be made for the buffer delay T~ at each tap to the delay line. This delay, when in (7), gives
to ‘CTRL? and the ‘% goes high, caPacitor CR B is connected low-pass-filtering operation is again performed just as in
the case of CR~ and Cc~RL. CR~ and CRB are designed
to
be equal,
is
so that on each clock phase the time constant
,j T OUT
[
;
=U(TP-TE)+TB,
approximately given by TP( Cc~RL /CR~ ) = TP( Cc-RL/ for Cc-~~ >> CR, where CR is the C,B) = T,(C ~-RL/CR), common value of C~~ and CR~. Since the SDL is symmetrical about its horizontal axis,
The buffer
its operation provided that
error TE, especially input.
clock down
is identical on each phase of the clock, both clock phases are identical. Hence, the
phases are generated by two, thereby
by dividing
making
III.
DELAY
Ej ]=~
them both identical.
is exactly
given
the error by which TE is equal and-hold
delay through
the total VCDL
to the propagation
networks
(4) the VCDL,
and TE is
delay deviates from
delay through
up to capacitors
TP.
the sample-
CR~ and CRB, plus the
delay time through the divide-by-two circuit. In practice, the load capacitors in the VCDL are all identical, while the sizes of the NOR gates may be varied in order NOR
to vary gate
the delay
sizes
the
for those taps furthest
from the VCDL
case where all delay elements are identical,
i=l,2,
~(Tp-T~)+TB,
I =
IV. An
Tv is the total
T~ is seen to cancel out somewhat
CLOSED-LOOP
STABILITY
obtained
is S1: S2:
at each
. . . : SN, where
tap.
If the ratio
S, is the
size
equivalent
illustrated
feedback-control
network
in Fig. 4. The parameter
CR /(CcT~~
+ CR ). The parameter
of
F represents
to
av~MpL /dTP.
The parameter
dence of the sampled
voltage
T~, produced
From function
the feedback-control is derived to be
‘CTRL(Z)
of
is given by
A represents
network,
l–[l–
the SDL
criteria
i=l,2,.
... N.
(5)
h(n)
W
The impulse The delay TOUT, appearing the start
at the i th delay element after
of a new phase is equal
delays up to and including
response
to the sum of all the
that element,
F[l–
B(A+l)]
”-’,
i=l,2,.
The
from an analy-
the inverse z trans-
n >0.
(11)
response given by (11) can have four essen-
decaying
for
that is
and exponentially , =
the right-hand
tial modes of behavior as a function of [1 – B(A + l)]. From (11), the impulse response will be exponentially
11- B(A+l)Il.
the impulse
(12)
response will
(13) be nonoscillatory
BAZES: iiovEL
pmcIsION
Mos
SYNCHRONOUS
DEL*Y
1269
LINE
Tp
t
1
I
[ Fig. 4.
Equivalent feedback-control network of SDL.
fo,r 1–B(A+l)>O and oscillatory
(14)
for, l–B(A+l)
From
(12)–(15),
delineated
A Fig. 5.
Region 2 —Exponential
Photomicrograph
decay: VI.
cCTRL/CR
Region
~
3 —Exponentially
A
>
–
decaying
+
1>
A
>
The sensitivity
oscillations:
and
supply
CCTRL/CR
A > Optimum
operation
growing
2cCTRL/cR
oscillations:
+
is obtained
the
Region
for values of A approaching
slowest
proaching
correction
is obtained
– 1. The response time
can be estimated
by substituting
cCTRL/cR
W)-
into
response values of A approaching CCTRL
/CR
the
for
2, where
Cc~RL/C~, values
to circuit
of
while A
ap-
disturbances
in the values for A and
values of A approaching time approaches zero, while for – 1 the response time approaches
For
infinity. In the implementation .DRAM controllers, ation was attained about
of the SDL in the 8207 and 8208
it was observed that Region 2 operfor values of CcT~~ /CR greater than
25.
V.
Equation and
are the load capacitors area.
rectangular capacitors
devices
in the photomicrograph
in the SDL.
is the dominating
The area of the load
component
in the total
SDL
(8) predicts
8208
DRAM
of
the SDL
was observed
of tR~~ (refer to Fig. 1) on TP of temperature
a linear
relationship
between
(8), the slope of the resulting
is a direct
However,
function
the intercept
by the SDL circuit tics of the logic
and
of the SDL
circuit
parameters.
of the curve is influenced
parameters, path
leading
tRCD
straight-line not only
but also by the characterisfrom
the SDL
tap to the
output pad. Hence, the slope of the tRc~-versus-TP curve gives a very precise quantification of the SDL behavior, while the characteristics of the intercept reflect the SDL behavior only weakly. Nevertheless, a sensitivity analysis of both the slope and intercept was carried out. Measurements ues of
of tRc. were made at the following
val-
TP: 125 nS, 145 nS, 165 nS, 190 nS, and 210 nS.
Beyond 210 nS, the present implementation of the SDL “saturates, “ i.e., further increases in TP result in small or for this phenomenon no increases in tRCD.The explanation is that
SDL PHOTOMICROGRAPH
A photomicrograph of the 8207 DRAM controller, in which the SDL was implemented for the first time, appears in Fig. 5. The location of the SDL on the die is indicated in the figure with an arrow. large
in temperature
the
of the SDL on the die was
for various combinations
TP. From
curve
large
The
the performance the dependence
in
supply voltage. Since CAS is triggered by the second SDL of TP directly tap, the behavior of tRcD as a function reflects the SDL behavior.
1-
in
was measured
Since direct probing
was measured
circuit disturbances have the least effect on operation. In Region 2, the most rapid correction for circuit disturbances is obtained
the first
RESULTS
of the SDL to variations
voltage
impractical, indirectly:
Region 4 —Exponentially
EXPERIMENTAL
die containing
~
controller. 2cCTRL/cR
of DRAM controller SDL implementation.
VCTRL reaches a maximum value
of
TP, and further
of nearly
increases
V&
for some
in TP cannot
be
accompanied by further increases in Vc~~L. The point at which the SDL saturates is entirely a function of the load capacitors on the NOR gates: the greater the size of the load capacitors,
the
larger
the
value
of
TP at which
the SDL
saturates. The measurements of tRCD were made at all combinations of the following temperatures and supply voltages: – 35°C, 25”C,, and 85”C; 4.5 V, 5.0 V, and 5.5 V.
IEEE
1270 TABLE I SLOPE(S), INTERCEPT(I), AND STANDARDDEVIATION (o),
OF SOLID-STATE
Slope Maximum
AND SUPPLY VOLTAGE, OF THE BEST-FIT STRAIGHT LINE FOR tRcDVERSUS TP
AS A FIJNCTION
JOURNAL
OF TEMPERATURE
VOL.
SC-20,
NO
sensitivity y to supply-voltage 4.7 percent /V
Maximum L:c
CIRCUITS,
sensitivity
6, DECEMBER
1985
variations:
(@ – 35°C)
to temperature
variations:
(v)
s
0.13
0,468
0.438
0.404
I
27.3
27.3
25.0
nS
Intercept
a
1,7
12
1.8
nS
Maximum
45
percent/°C
sensitivity
to supply-voltage
15,7 percent /V sensitivity
Maximum
‘28.6
]23.6
1
u
I
25.0
nS
18
nS
variations:
(@ - 35”C)
to temperature
0.09 percent/°C
1
1
I
15511
(@4.5 V).
variations:
(@5.O V).
,
0.8
0.4
B. Discussion
of Experimental
The standard technique
TABLE II SENSITIVITIESOF SLOPEANII INTERCEPTTO SUPPLY-VOLTAGEVARIATIONS (IN %/V)
behavior
deviation
represents
calculated
both
with
the least-squares
the nonlinearity
over the range of measurements
the measurements deviation linear
Results
themselves.
was calculated
behavior
that
substantiated experimentally. The maximum sensitivity
the
SDL
In all cases, the standard
to be under
of the SDL
of
and the error in 2 nS, so that
is predicted
the
by (8) was
of the slope to temperature
and supply-voltage variations was observed to be only a few percent over large ranges of temperature and supply TABLE III SENSITIVITIESOF SLOPEAND INTERCEPT‘ro TEMPERATUREVARIATIONS(IN %/°C)
voltage. Thus delays generated by the SDL are significantly more precise than those observed in ordinary MOS circuits. This
low sensitivity
direct
result
to operating-parameter
of the negative
feedback
variations
inherent
is a
in the SDL
design. While includes
the intercept effects
is, nevertheless, The best-fit calculated
supply
voltage
standard
the measured points of temperature and
straight line through for each combination
was
using the least-squares
deviation
of the measured
technique, points
while
from
the
the line
is of secondary
interest—its
of the logic paths external worthwhile
to comment
behavior
to the SDL—it on the relatively
low sensitivity of the intercept to temperature and supplyvoltage variations. The low sensitivity stems from the fact the delay of that tRcD is composed of three components: RAS
from
the SDL;
the falling
edge of CLK;
and the delay
of CAS
the delay caused by
from
the output
of the
was also calculated. The sensitivities of the intercept and of the slope of the line to temperature and supply-voltage
SDL. The value of t ~c~ is equal to the delay caused by the
variations
This difference
were then calculated
from
the measured
data.
SDL tions
A. Measured The
slopes, intercepts,
and
standard
The sensitivities voltage The
were
calculated
sensitivities
age variations ties of the slope tabulated The ment
maximum from
from
are tabulated
of the t~c~-
in temperature the data
of the slope
and
tabulated
intercept
in Table
and intercept
in Table
are,
of the slope and intercept to variations
and SUPPIY in Table
I.
to supply-volt-
II, while
to temperature
the sensitivivariations
are
111. sensitivities
Tables
II and
over III,
the
in operating
devia-
tions for best-fit straight lines through the measured values of t~cD versus TP, as a function of temperature and supply volt age, are tabulated in Table I. versus- TP curve
in delays between
component
CAS and RAS.
tends to be insensitive
conditions,
since variations
to varia-
in the RAS
and CAS delays tend to cancel each other out.
Dependence of t~c~ on TP
calculated
plus the d~ference
range
as follows.
of
measure-
VII.
CONCLUSIONS
A novel precision MOS SDL has been described. The SDL produces delays that are linearly related to the reference clock
period.
An
arbitrary
number
of taps (within
design limits) can be made to the SDL. The SDL employs negative feedback to correct the output delays with respect to’ the reference clock period and with respect to variations in operating parameters. A closed-loop circuit analysis was developed to define the circuit parameters that determine the stability of SDL operation. Experimental observations confirm the linear behavior of the SDL and its low sensitivity to temperature and supply-voltage variations.
BAZES:
NOVEL
PRECISION
MOS SYNCHRONOUS
DELAY
LINE
~I&a~y&es,”
Component
Catalog,
Automatic
Coil Corp., Hiafiah,
M.’ Bazes, J. Nadir, D. Perlmutter, B. Mantel, and O. Z&, “A programmable NMOS DRAM controller for microcomputer systems with duaf-port memory and error checking and correction,” IEEE J. Solid-Stute Circuits, vol. SC-18, pp. 164-172, Apr. 1983. [3] 2164A Data Sheet, Intel Corp., Santa Clara, CA, Apr. 1982. charge redistribution [4.] J. L. McCreary and P. R. Gray, “Ail-MOS anrdog-to-digitaf conversion techmques— Part I,” IEEE J. Solid-S~ate UCG. Circuils, vol. SC-10, pp. 371–379? ‘-‘L7‘7’/J. [5] J. Caves, M. Co~eland, C. Ralur m, and S. Rosenbaum, “Sampled analog filtering u;ing switched capacitors as resistor elements,” l~EE J. Solid-State Circuits,, vol. SC-12, pp. 592-599, Dec. 1977. [2,]
Bazes received the B.S. degree in chemistry from the University of Cfllfornia, Los Angeles, and the M.S. degree in engineering science from the University of California, Berkeley. Since 1977 he has been with Intel Israel Ltd., Haifa, Israel, where he has been engaged in the definition, design, and development of LSI and VLSI components. He has performed the redesign of the 8080A Microprocessor and led the designs of the 8206 Error Checking and Correction Unit. the 8207 Dual-Port DRAM Controller, and other LSI and VLSI components. Mel
REFERENCES [1]
1271
—
